CN202362691U - Low dropout linear regulator - Google Patents
Low dropout linear regulator Download PDFInfo
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- CN202362691U CN202362691U CN2011205116082U CN201120511608U CN202362691U CN 202362691 U CN202362691 U CN 202362691U CN 2011205116082 U CN2011205116082 U CN 2011205116082U CN 201120511608 U CN201120511608 U CN 201120511608U CN 202362691 U CN202362691 U CN 202362691U
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Abstract
The utility model belongs to the technical field of power management, and discloses a low dropout linear regulator, which particularly comprises an error amplifier, a first impedance unit, a second impedance unit and a sampling network. The low dropout linear regulator is characterized by further comprising an N-shaped regulating tube, a power under-voltage comparator, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube. A P-shaped regulating tube is replaced by the N-shaped regulating tube, so that load jump is directly reflected to gate-source voltage of the regulating tube without passing through a feedback loop, and rapid response to load change is realized. Besides, as pressure drop of the LDO (low dropout regulator) with the N-shaped regulating tube is large, performances such as the efficiency and the like of the LDO can be affected, and the problem of power supply shortage is solved by the aid of the power under-voltage comparator.
Description
Technical field
The utility model belongs to the power management techniques field, is specifically related to the design of a kind of low pressure difference linear voltage regulator (LDO, Low Dropout Regulator).
Background technology
Low pressure difference linear voltage regulator can provide the power supply of output ripple and low for noise-sensitive such as mimic channel and radio circuits, and structure is simple relatively, and peripheral component is few, thereby is widely used in the on-chip system chip.In most the application, need to give the next door of each circuit module to put a LDO who is not mounted with output capacitance, the raising that the optimization of like this each circuit module power supply being supplied power can bring the entire system performance.
Traditional LDO is as shown in Figure 1, and wherein, VREF is the reference voltage that reference circuit produces, and EA is an error amplifier, and MP is a PMOS output adjustment pipe, and R1 and R2 are feedback resistance, and RL, CL are respectively output resistance and electric capacity.This circuit comes regulated output voltage VOUT through the negative feedback of error amplifier and output adjustment pipe.
For traditional LDO circuit shown in Figure 1; When load generation transition (ns level); Have two kinds of mechanism to come regulated output voltage: the one, required transient current when load transient being provided through big load capacitance CL; Thereby regulated output voltage adopts big load capacitance will increase area of chip, has improved cost; The 2nd, through the gate source voltage V of feedback control loop adjustment P type adjustment pipe
GSThe responsive load transition, in order to reach quick response, loop must have bigger bandwidth.
For linear voltage regulator for digital circuit power supply because load current changes very fast and amplitude greatly, require LDO that loop response speed is fast arranged, and accuracy requirement is not high relatively.At present, academia has also proposed the scheme of many raising LDO transient responses, such as adopting the buffer level to expand bandwidth, adopts speed dicyclo control structure to improve corresponding speed etc.But the defective that these schemes exist is the circuit structure more complicated, and has increased extra power consumption.
The utility model content
The purpose of the utility model is in order to solve the defective that existing low pressure difference linear voltage regulator response speed exists, to have proposed a kind of low pressure difference linear voltage regulator.
To achieve these goals; The technical scheme of the utility model is: a kind of low pressure difference linear voltage regulator; Comprise: error amplifier, first impedance unit, second impedance unit and sampling network; It is characterized in that, also comprise N type adjustment pipe, line under-voltage comparer, PMOS pipe and the 2nd PMOS pipe
Wherein, the forward of error amplifier output termination first reference voltage, the grid of output termination N type adjustment pipe; The drain electrode of N type adjustment pipe connects external power source, and source electrode is as the output terminal of linear voltage regulator; The output terminal of one termination linear voltage regulator of first impedance unit, an end of the negative input of another termination error amplifier and second impedance unit, the other end ground connection of second impedance unit; The source electrode of the one PMOS pipe connects external power source, and drain electrode connects the grid of N type adjustment pipe, and grid connects the output terminal of line under-voltage comparer; The source electrode of the 2nd PMOS pipe connects external power source, and the output terminal of drain connection property voltage stabilizer, grid connect the output terminal of line under-voltage comparer; The negative input of supply voltage under-voltage comparator connects second reference voltage, and positive input connects the output terminal of sampling network; The input termination external power source of sampling network.
The beneficial effect of the utility model: the low pressure difference linear voltage regulator of the utility model utilizes N type adjustment pipe to replace P type adjustment pipe, makes the load saltus step be directly reflected into the gate source voltage of adjustment pipe, need not to realize the quick response to load variations through feedback control loop; Owing to adopt the LDO pressure drop of N type adjustment pipe bigger, can influence the performances such as efficient of LDO simultaneously, the utility model has solved the problem of power supply electricity shortage again by the line under-voltage comparer.
Description of drawings
Fig. 1 is existing LDO electrical block diagram.
Fig. 2 is the LDO basic structure synoptic diagram of the utility model.
Fig. 3 is the structural representation of the LDO implementation of the utility model embodiment.
Fig. 4 is the another kind of implementation structural representation of the LDO of the utility model embodiment.
Fig. 5 is the LDO transient state simulation waveform figure of the utility model.
Fig. 6 is the line under-voltage comparer simulation waveform figure of the utility model.
Embodiment
Below in conjunction with accompanying drawing and concrete embodiment the utility model is done further to set forth.
The LDO basic structure synoptic diagram of the utility model is as shown in Figure 2; Specifically comprise: error amplifier, the first impedance unit RF1, second impedance unit RF2 and the sampling network; Also comprise N type adjustment pipe MN0, line under-voltage comparer, PMOS pipe MP1 and the 2nd PMOS pipe MP2; Wherein, the forward of the error amplifier output termination first reference voltage V REF1, the grid of output termination N type adjustment pipe; The drain electrode of N type adjustment pipe meets external power source VDD, and source electrode is as the output terminal of linear voltage regulator; The output terminal of the termination linear voltage regulator of the first impedance unit RF1, the end of the negative input of another termination error amplifier and the second impedance unit RF2, the other end ground connection of the second impedance unit RF2; The source electrode of the one PMOS pipe MP1 connects external power source, and drain electrode connects the grid of N type adjustment pipe MN0, and grid connects the output terminal of line under-voltage comparer; The source electrode of the 2nd PMOS pipe MP2 meets external power source VDD, and the output terminal of drain connection property voltage stabilizer, grid connect the output terminal of line under-voltage comparer; The negative input of supply voltage under-voltage comparator meets the second reference voltage V REF2, and positive input connects the output terminal of sampling network; The input termination external power source VDD of sampling network.
Here, error amplifier is used to regulate the grid voltage of N type adjustment pipe MN0; The output circuit of N type adjustment pipe MN0 is used to drive load; The supply voltage under-voltage comparator is used to solve the problem of the power supply electricity shortage that brings more greatly owing to the LDO DROPOUT voltage that adopts N type adjustment pipe, and the supply voltage under-voltage comparator can adopt conventional comparator configuration.
Fig. 3 has provided the structural representation of a LDO implementation, and the first impedance unit RF1 here, the second impedance unit RF2 are respectively first resistance R 1, second resistance R 2.
Fig. 4 has provided the structural representation of the another kind of implementation of LDO; The first impedance unit RF1 here, the second impedance unit RF2 can realize through the PMOS pipe that diode connects; Concrete can realize through PMOS pipe MP11, MP12, MP13 and the MP14 that four diode connect; Concrete annexation is: the source electrode of MP11 is as an end of first impedance unit; The drain and gate of MP11 connects the source electrode of MP12, and the drain and gate of MP12 connects the source electrode of MP13, and the drain and gate of MP13 is connected as the other end of first impedance unit; The source electrode of MP14 connects an end of second impedance unit, and the drain and gate of MP14 is connected as the other end of second impedance unit.
Fig. 4 has also provided a kind of implementation of sampling network; Be specially: sampling network comprises the 3rd resistance R 3 and the 4th resistance R 4; Wherein, One end of the 3rd resistance R 3 is as the input end of sampling network, and the other end links to each other the other end ground connection of the 4th resistance R 4 as the output terminal of sampling network and with an end of the 4th resistance R 4.
The principle of work of the low pressure difference linear voltage regulator of the utility model is: when input voltage when higher, if output load is stable, the output voltage of LDO is by the control of error amplifier loop, the feedback voltage V Fb of loop equals reference voltage V REF1.
When output load became heavy duty by underload, output voltage descended, i.e. the source voltage of N type adjustment pipe MN0 descends, and then its gate source voltage V
GSRaise, simultaneously,, the grid voltage of N type adjustment pipe MN0 is raise, further make its gate source voltage V through the feedback control loop of error amplifier
GSRaising, adjustment pipe MN0 output current is increased fast, is the required transient current of heavy duty so that load to be provided by the underload saltus step, makes output voltage recover stable fast.
When output load became underload by heavy duty, output voltage rose, i.e. the source voltage of N type adjustment pipe MN0 rises, and then its gate source voltage V
GSDescend,, the grid voltage of N type adjustment pipe MN0 is descended, further make its gate source voltage V through the feedback control loop of error amplifier
GSReduce, adjustment pipe MN0 output current is reduced fast, make output voltage recover stable fast.
When input voltage was higher, power supply sampled voltage LDO_SW was higher than reference voltage V REF2, and the output terminal of line under-voltage comparer is a high level, and MP1 and MP2 are in off state; When the difference of supply voltage and LDO output voltage was managed the pressure drop on the MN0 less than the adjustment of N type, sampled voltage LDO_SW was lower than reference voltage V REF2, and the line under-voltage comparer is output as low level, MP1 and MP2 conducting.The grid voltage of N type adjustment pipe MN0 is drawn high in the MP1 conducting, and error amplifier output is kept, and after supply voltage recovered, error amplifier just need not restart can get into duty immediately; The MP2 conducting provides extra power supply branch road, and output is stabilized in:
VOUT＝VDD-I
load×R
on (1-1)
Wherein, I
LoadBe load current, R
OnIt is the conducting resistance of MP2.VREF1 and VREF2 are the reference voltage that the outside reference circuit provides, and concrete size can be confirmed according to designing requirement.
As shown in Figure 5, the transient state simulation waveform figure of LDO, load generation transition, the about 500mV of peak value saltus step of output voltage, about 500ns of response time, as can be seen from the figure, the transient response of the LDO of the utility model is fine, has load response ability fast.
As shown in Figure 6; The simulation waveform figure of line under-voltage comparer, wherein, the VOUT of solid line representes is the simulation result of VDD when rising; Dotted line is represented is the simulation result of VDD when descending; As can be seen from the figure, the about 0.5V in sluggish space, comparer can effectively solve the problem of power supply electricity shortage.
To sum up can find out; The low pressure difference linear voltage regulator of the utility model adopts N type adjustment pipe to replace P type adjustment pipe, makes the load saltus step be directly reflected into the gate source voltage of adjustment pipe, comes regulated output voltage in order to the control output current; Need not to realize quick response to load variations through feedback control loop; Adopted the line under-voltage holding circuit, effectively solved because the problem of the power supply electricity shortage that the LDO pressure drop of adopting the adjustment of N type to manage brings more greatly.In addition, the linear voltage regulator of the utility model is simple in structure, has also avoided the demand of the external big electric capacity of output needs of LDO.The digital circuit that the linear voltage regulator of the utility model can be used in simulation or the hybrid digital-analog integrated circuit is partly supplied power.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help the principle of reader understanding's the utility model, should to be understood that the protection domain of the utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these teachings of the utility model, and these distortion and combination are still in the protection domain of the utility model.
Claims (5)
1. low pressure difference linear voltage regulator comprises: error amplifier, first impedance unit, second impedance unit and sampling network, it is characterized in that, and comprise that also N type adjustment pipe, line under-voltage comparer, PMOS pipe and the 2nd PMOS manage,
Wherein, the forward of error amplifier output termination first reference voltage, the grid of output termination N type adjustment pipe; The drain electrode of N type adjustment pipe connects external power source, and source electrode is as the output terminal of linear voltage regulator; The output terminal of one termination linear voltage regulator of first impedance unit, an end of the negative input of another termination error amplifier and second impedance unit, the other end ground connection of second impedance unit; The source electrode of the one PMOS pipe connects external power source, and drain electrode connects the grid of N type adjustment pipe, and grid connects the output terminal of line under-voltage comparer; The source electrode of the 2nd PMOS pipe connects external power source, and the output terminal of drain connection property voltage stabilizer, grid connect the output terminal of line under-voltage comparer; The negative input of supply voltage under-voltage comparator connects second reference voltage, and positive input connects the output terminal of sampling network; The input termination external power source of sampling network.
2. low pressure difference linear voltage regulator according to claim 1 is characterized in that, described first impedance unit, second impedance unit are respectively first resistance, second resistance.
3. low pressure difference linear voltage regulator according to claim 1 is characterized in that, described first impedance unit, second impedance unit are specifically realized through the PMOS pipe that diode connects.
4. low pressure difference linear voltage regulator according to claim 3; It is characterized in that; Described first impedance unit, second impedance unit specifically realize that through PMOS pipe MP11, MP12, MP13 and the MP14 that four diode connect concrete annexation is: the source electrode of MP11 is as an end of first impedance unit, and the drain and gate of MP11 connects the source electrode of MP12; The drain and gate of MP12 connects the source electrode of MP13; The drain and gate of MP13 is connected as the other end of first impedance unit, and the source electrode of MP14 connects an end of second impedance unit, and the drain and gate of MP14 is connected as the other end of second impedance unit.
5. according to the arbitrary described low pressure difference linear voltage regulator of claim 1 to 4; It is characterized in that; Described sampling network comprises the 3rd resistance and the 4th resistance, and wherein, an end of the 3rd resistance is as the input end of sampling network; The other end links to each other the other end ground connection of the 4th resistance as the output terminal of sampling network and with an end of the 4th resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205116082U CN202362691U (en) | 2011-12-09 | 2011-12-09 | Low dropout linear regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205116082U CN202362691U (en) | 2011-12-09 | 2011-12-09 | Low dropout linear regulator |
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| CN202362691U true CN202362691U (en) | 2012-08-01 |
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| CN2011205116082U Expired - Fee Related CN202362691U (en) | 2011-12-09 | 2011-12-09 | Low dropout linear regulator |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495656A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Low dropout linear regulator |
| CN104035467A (en) * | 2013-03-05 | 2014-09-10 | 三星电子株式会社 | Bi-directional voltage positioning circuit, voltage converter and power supply device including the same |
| CN104765397A (en) * | 2014-01-02 | 2015-07-08 | 意法半导体研发(深圳)有限公司 | LDO (linear voltage regulator) for internal electric source and with improved load transient performance |
| WO2016026416A1 (en) * | 2014-08-19 | 2016-02-25 | 无锡华润上华半导体有限公司 | Low drop-out regulator circuit, chip and electronic device |
| CN105652942A (en) * | 2016-03-15 | 2016-06-08 | 西安紫光国芯半导体有限公司 | Voltage drop reduction device |
| CN106468932A (en) * | 2015-08-17 | 2017-03-01 | 天工方案公司 | Apparatus and method for the programmable low drop-out regulator of radio frequency electronics |
-
2011
- 2011-12-09 CN CN2011205116082U patent/CN202362691U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495656A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Low dropout linear regulator |
| CN104035467A (en) * | 2013-03-05 | 2014-09-10 | 三星电子株式会社 | Bi-directional voltage positioning circuit, voltage converter and power supply device including the same |
| US9438109B2 (en) | 2013-03-05 | 2016-09-06 | Samsung Electronics Co., Ltd. | Bi-directional voltage positioning circuit, voltage converter and power supply device including the same |
| CN104765397A (en) * | 2014-01-02 | 2015-07-08 | 意法半导体研发(深圳)有限公司 | LDO (linear voltage regulator) for internal electric source and with improved load transient performance |
| WO2016026416A1 (en) * | 2014-08-19 | 2016-02-25 | 无锡华润上华半导体有限公司 | Low drop-out regulator circuit, chip and electronic device |
| US9952609B2 (en) | 2014-08-19 | 2018-04-24 | Csmc Technologies Fabi Co., Ltd. | Low drop-out regulator circuit, chip and electronic device |
| CN106468932A (en) * | 2015-08-17 | 2017-03-01 | 天工方案公司 | Apparatus and method for the programmable low drop-out regulator of radio frequency electronics |
| US10642296B2 (en) | 2015-08-17 | 2020-05-05 | Skyworks Solutions, Inc. | Programmable low dropout regulators with fast transient response when programming output voltage |
| CN105652942A (en) * | 2016-03-15 | 2016-06-08 | 西安紫光国芯半导体有限公司 | Voltage drop reduction device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120801 Termination date: 20141209 |
|
| EXPY | Termination of patent right or utility model |