CN103532542A - Inverter circuit for clock tree - Google Patents

Abstract

The invention discloses an inverter circuit for a clock tree. The inverter circuit comprises a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube which are connected in series; grids of the PMOS tube and the NMOS tube are connected; drains of the PMOS tube and the NMOS tube are connected; the input of the inverter circuit is connected with the grids of the PMOS tube and the NMOS tube; the output of the inverter circuit is connected with the drains of the PMOS tube and the NMOS tube; the source of the PMOS tube is connected with a power supply; the source of the NMOS tube is grounded. The inverter circuit can be kept balanced in a delaying mode under the minimum work voltage of 1.0V.

Description

A kind of inverter circuit for Clock Tree

Technical field

The present invention relates to a kind of inverter circuit, particularly relate to a kind of for CMOS(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) inverter circuit in digital integrated circuit Clock Tree.

Background technology

Inverter is the important elementary cell in cmos digital integrated circuit, is also for example parts of buffer (Buffer) of other elementary cells.For the inverter of Clock Tree, there is certain feature, during rising edge and decline time delay need to keep balance, such clocked inverter unit can be called CLKINV unit.

The behavior under reference power supply voltage (VDD) is generally only considered in CLKINV unit in standard cell lib when design, and the behavior under low-voltage (as 1.0V) is not considered.Therefore, this CLKINV element circuit will lose efficacy when the lower work of low-voltage (as 1.0V).

Summary of the invention

The deficiency existing for overcoming above-mentioned prior art, the present invention's object is to provide a kind of inverter circuit for Clock Tree, and it can also can keep delay balance under minimum 1.0V operating voltage.

For reaching above-mentioned and other object, the present invention proposes a kind of inverter circuit for Clock Tree, this inverter circuit comprises the PMOS pipe and NMOS pipe of pair of series, this PMOS pipe is connected with the grid of this NMOS pipe, drain electrode is connected, and the input of this inverter circuit is connected on the grid of this PMOS pipe and this NMOS pipe, and output is connected on the drain electrode of this PMOS pipe and this NMOS pipe, the source electrode of this PMOS pipe connects power supply, the source ground of this NMOS pipe.

Further, this inverter circuit is based on the technological design of SMIC0.18 micron.

Further, the length of this PMOS pipe is 180nm～200nm, and the width of this PMOS pipe is 505nm～620nm.

Further, the length of this NMOS pipe is 180nm～200nm, and the width of this NMOS pipe is 220nm～265nm.

Further, the operating voltage range of this inverter circuit is 1.0V～1.8V.

Further, the operating temperature range of this inverter circuit is-40 ℃～80 ℃, meets all process corner requirements.

Compared with prior art, a kind of inverter circuit for Clock Tree of the present invention, by a PMOS pipe and a NMOS pipe are composed in series to CLKINV unit, and by its size is improved, in the time of can keeping rising edge when operating voltage is 1.0V～1.8V and decline delay balance, realized in low-voltage (as 1.0V) and also can keep the object of delay balance, when simultaneously the present invention can also keep rising edge when operating temperature range is-40 ℃～80 ℃ and decline delay balance, circuit size of the present invention is little, operating voltage is low, and area and power consumption are little.

Accompanying drawing explanation

Fig. 1 is threshold voltage U _tHthe schematic diagram that is related to channel length L and channel width W;

Fig. 2 is the circuit diagram of a kind of inverter circuit for Clock Tree of the present invention.

Embodiment

Below, by specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented or be applied by other different instantiation, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change not deviating under spirit of the present invention.

Before introducing the present invention, the lower theoretical foundation of the present invention of first explanation: the mutual conductance g of metal-oxide-semiconductor _mwhen ignoring wide impact of raceway groove tune, be square-law equation,

$g_m=\frac{{\∂I}_D}{{\∂U}_{\mathrm{GS}}}={\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right)(U_{\mathrm{GS}}-U_{\mathrm{TH}})=\sqrt{2{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right)I_D}=\frac{2I_D}{U_{\mathrm{GS}}-U_{\mathrm{TH}}}$

U wherein _gSfor gate source voltage, I _dfor drain current, U _tHfor threshold voltage,

for breadth length ratio, μ _nfor electron mobility, C _oxfor unit are gate capacitance.

And the characteristic frequency f of metal-oxide-semiconductor _tfor

wherein τ is the transit time of electronics in raceway groove.

wherein L is channel length, μ _nfor electron mobility, E is raceway groove electric field strength (E=U _dS/ L).

By τ substitution f _texpression formula has

$f_T=\frac{{\mathrm{\μ}}_n{U}_{\mathrm{DS}}}{2{\mathrm{\πL}}^2}$

More than analyze and show: the performance of metal-oxide-semiconductor field effect transistor and breadth length ratio (W/L) have very strong dependence:

in constant situation, g _mwith (U _gS-U _tH) linear, with I _dsquare root be directly proportional; At I _din constant situation, g _mwith (U _gS-U _tH) be inversely proportional to.When supply voltage reduces, the inverter size of library cells when constant, drain current I _dreduce, therefore its g _mto reduce, thereby occur that inverter rises, trailing edge failure phenomenon even slowly.

Channel length L is less, f _tand g _mlarger, and integrated level is higher, therefore, reduces device size and is conducive to improve device performance.Improve carrier mobility μ and be conducive to increase f _tand g _m, the μ of NMOS _nthan the μ of PMOS _plarge 2～4 times, so the performance of NMOS pipe is better than PMOS pipe.When supply voltage reduces, the inverter size of library cells

when constant, f _tto reduce, this causes occurring equally, and inverter rises, trailing edge failure phenomenon even slowly.

In long channel device (L>3～4 μ m), threshold voltage U<sub TranNum="122">tH</sub>little with the relation of channel length L and channel width W, and in short channel (L<3 μ m) device, U<sub TranNum="123">tH</sub>larger with the relation of L, W, U<sub TranNum="124">tH</sub>along with the increase of L, increase, along with the increase of W, reduce, as shown in Figure 1.Therefore reduce channel length L increase channel width and can suitably reduce threshold voltage U<sub TranNum="125">tH</sub>be beneficial to low voltage operating.

Fig. 2 is the circuit diagram of a kind of inverter circuit for Clock Tree of the present invention.As shown in Figure 2, a kind of inverter circuit CLKINV for Clock Tree of the present invention, comprise a cmos logic gate circuit with negative function, its overall structure comprises 2 transistors, a PMOS pipe and a NMOS pipe, that is,, between input In and output Out, there are a PMOS pipe MP and a NMOS pipe MN.Wherein, PMOS pipe MP connects with NMOS pipe MN, and the grid of MP and MN is connected, and drain electrode is connected, and the input In of inverter is connected on the grid of MP and MN, and output Out is connected on the drain electrode of MP and MN, and it is upper that the source electrode of MP is connected on power vd D, and the source class of MN is connected on ground GND.

In preferred embodiment of the present invention, the present invention is based on SMIC0.18 micron (μ m) technological design, the length of PMOS pipe MP is 190nm(nanometer) positive and negative 5% between, be about 180nm～200nm, in preferred embodiment of the present invention, the length of PMOS pipe MP is 180nm, and the width of PMOS pipe is 505nm～620nm; The length 190nm(nanometer of PMOS pipe MP) positive and negative 5% between, be about 180nm～200nm, in preferred embodiment of the present invention, the length of PMOS pipe MP is 180nm, the width of PMOS pipe MP is 505nm～620nm; The length of NMOS pipe MN is 190nm(nanometer) positive and negative 5% between, be about 180nm～200nm, in preferred embodiment of the present invention, the length of NMOS pipe MN is 180nm, the width of NMOS pipe MN is 220nm～265nm.The present invention's inverter circuit can work under 1.0V～1.8V voltage, and minimum operating voltage is 1.0V, and while under low pressure working, circuit power consumption is low, and its operating temperature range is-40 ℃～80 ℃, meets all process corner requirements.

In sum, a kind of inverter circuit for Clock Tree of the present invention, by a PMOS pipe and a NMOS pipe are composed in series to CLKINV unit, and by its size is improved, in the time of can keeping rising edge when operating voltage is 1.0V～1.8V and decline delay balance, realized in low-voltage (as 1.0V) and also can keep the object of delay balance, when simultaneously the present invention can also keep rising edge when operating temperature range is-40 ℃～80 ℃ and decline delay balance, circuit size of the present invention is little, operating voltage is low, and area and power consumption are little.

Compare with existing clocked inverter, circuit tool of the present invention has the following advantages:

(1) operating temperature range is-40 ℃～80 ℃, meets all process corner requirements.

(2) can under 1.0V～1.8V voltage, work, while under low pressure working, circuit power consumption is low.

(3) size of PMOS pipe and NMOS pipe is little, and area and the power consumption of circuit are little.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify and change above-described embodiment.Therefore, the scope of the present invention, should be as listed in claims.

Claims (6)

1. the inverter circuit for Clock Tree, it is characterized in that: this inverter circuit comprises the PMOS pipe and NMOS pipe of pair of series, this PMOS pipe is connected with the grid of this NMOS pipe, drain electrode is connected, the input of this inverter circuit is connected on the grid of this PMOS pipe and this NMOS pipe, output is connected on the drain electrode of this PMOS pipe and this NMOS pipe, and the source electrode of this PMOS pipe connects power supply, the source ground of this NMOS pipe.

2. a kind of inverter circuit for Clock Tree as claimed in claim 1, is characterized in that: this inverter circuit is based on the technological design of SMIC0.18 micron.

3. a kind of inverter circuit for Clock Tree as claimed in claim 2, is characterized in that: the length of this PMOS pipe is 180nm～200nm, and the width of this PMOS pipe is 505nm～620nm.

4. a kind of inverter circuit for Clock Tree as claimed in claim 2, is characterized in that: the length of this NMOS pipe is 180nm～200nm, and the width of this NMOS pipe is 220nm～265nm.

5. a kind of inverter circuit for Clock Tree as claimed in claim 2, is characterized in that: the operating voltage range of this inverter circuit is 1.0V～1.8V.

6. a kind of inverter circuit for Clock Tree as claimed in claim 2, is characterized in that: the operating temperature range of this inverter circuit is-40 ℃～80 ℃, meets all process corner requirements.

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