CN202423250U - 多芯片混合结构 - Google Patents

多芯片混合结构 Download PDF

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Publication number
CN202423250U
CN202423250U CN2011205709798U CN201120570979U CN202423250U CN 202423250 U CN202423250 U CN 202423250U CN 2011205709798 U CN2011205709798 U CN 2011205709798U CN 201120570979 U CN201120570979 U CN 201120570979U CN 202423250 U CN202423250 U CN 202423250U
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chip
mixed structure
base
chips
utility
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CN2011205709798U
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刘坚
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FUJIAN HESHUN MICROELECTRONIC Co Ltd
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FUJIAN HESHUN MICROELECTRONIC Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型涉及一种多芯片混合结构，包括带有引脚的底座、设于底座上的各芯片和引线，其特征在于：所述各芯片与底座引脚之间通过各自的粘结层连接，且各芯片之间通过内连接导线连接，所述引线还与其中之一或更多的芯片连接。本实用新型中多个IC芯片或其它芯片，根据功能需要，采用自隔离粘接层或连通粘接层，以及内连接导线的简单重新组合，可以直接实现IC功能的改变。

Description

多芯片混合结构
技术领域
本实用新型涉及一种多芯片混合结构，应用于芯片封装，属于芯片制造与封装领域。
背景技术
对于功率集成电路，为了拓展增加新的功能或增大功率或增加电流，往往需重新设计IC芯片或采用多个半导体器件或其它器件，这样经常会将带来设计制造以及使用空间和消耗材料资源的浪费。
发明内容
本实用新型的目的在于提供一种多芯片混合结构，从而实现在一个封装体内达到拓展增加IC新的功能或增大功率或增加电流的目的。
本实用新型的特征在于：一种多芯片混合结构，包括带有引脚的底座、设于底座上的各芯片和引线，其特征在于：所述各芯片与底座引脚之间通过各自的粘结层连接，且各芯片之间通过内连接导线连接，所述引线还与其中之一或更多的芯片连接。
本实用新型的优点：本实用新型中多个IC芯片或其它芯片，根据功能需要，采用自隔离粘接层或连通粘接层，以及内连接导线的简单重新组合，可以直接实现IC功能的改变。
附图说明
图1为本实用新型实施例结构剖视示意图。
具体实施方式
参考图1，一种多芯片混合结构，包括带有引脚的底座1、设于底座1上的各芯片2和引线3，所述各芯片2与底座1引脚之间通过各自的粘结层4连接，且各芯片2之间通过内连接导线5连接，所述引线3还与其中之一或更多的芯片2连接。
上述粘结层4为自隔离粘结层或连通粘结层。
上述底座1上还设有将芯片2、内连接导线5包覆住的塑胶体6。
具体实施过程：本实用新型在实施过程中，可以根据需要来选择粘结层的形式，可针对某一芯片选择自隔离粘结层、另一芯片选择连通粘结层，或全部芯片选择自隔离或连通，完全可以根据生产需要来进行选择；并且各芯片之间还可以通过内连接导线实现连接，从而满足某些设计需要，这样极大拓展增加IC新的功能或增大功率或增加电流。
以上所述仅为本实用新型的较佳实施例，凡依本实用新型申请专利范围所做的均等变化与修饰，皆应属本实用新型的涵盖范围。

Claims (3)

1.一种多芯片混合结构，包括带有引脚的底座、设于底座上的各芯片和引线，其特征在于：所述各芯片与底座引脚之间通过各自的粘结层连接，且各芯片之间通过内连接导线连接，所述引线还与其中之一或更多的芯片连接。
2.根据权利要求1所述的多芯片混合结构，其特征在于：所述粘结层为自隔离粘结层或连通粘结层。
3.根据权利要求1所述的多芯片混合结构，其特征在于：所述底座上还设有将芯片、内连接导线包覆住的塑胶体。
CN2011205709798U 2011-12-31 2011-12-31 多芯片混合结构 Expired - Lifetime CN202423250U (zh)

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Applications Claiming Priority (1)

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Granted publication date: 20120905