CN202394929U - Multi-base embedded multi-pin and electrostatic discharge loop packaging structure - Google Patents

Multi-base embedded multi-pin and electrostatic discharge loop packaging structure Download PDF

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Publication number
CN202394929U
CN202394929U CN 201120479943 CN201120479943U CN202394929U CN 202394929 U CN202394929 U CN 202394929U CN 201120479943 CN201120479943 CN 201120479943 CN 201120479943 U CN201120479943 U CN 201120479943U CN 202394929 U CN202394929 U CN 202394929U
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China
Prior art keywords
pin
chip
release ring
static release
electrostatic discharge
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Expired - Lifetime
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CN 201120479943
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Chinese (zh)
Inventor
王新潮
梁志忠
谢洁人
吴昊
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN 201120479943 priority Critical patent/CN202394929U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a multi-base embedded multi-pin and electrostatic discharge loop packaging structure which comprises a plurality of loops of outer pins (1) and an outer electrostatic discharge loop (2), wherein the front surface of each outer pin (1) forms an inner pin (4) in a multilayer electroplating mode; the inside of the outer electrostatic discharge loop (2) forms an inner base (3) in a multilayer electroplating mode; the front surface of the inner base (3) is provided with a chip (6); the front surface of the chip (6) is connected with the front surface of each inner pin (4) through a metal wire (7), and the front surface of the chip (6) is connected with the front surface of the chip (6) through a metal wire (7); and each outer pin (1) and the back surface of the outer electrostatic discharge loop (2) are respectively provided with a second metal layer (10). The multi-base embedded multi-pin and electrostatic discharge loop packaging structure disclosed by the utility model saves the high-temperature-resistant adhesive film on the back surface, and lowers the packaging cost; the optional varieties of products is great; the quality of metal wire bonding, and the stability of reliability of the product is good; and the binding capacity between the plastic packaging body and the metal pins is high, thereby realizing high-density capacity of the inner pins.

Description

Many base island embedded many circle pin static release ring encapsulating structures
Technical field
The utility model relates to a kind of how base island embedded many circle pin static release ring encapsulating structures, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 5) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, but also because such a lead frame must be affixed on the back layer of high temperature of the film, during the packaging process so that the loading process can use conductive or non-conductive adhesive material, and can not be used completely eutectic solder process technology and for loading, so choose the types of products have greater limitations;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 4) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; A kind of how base island embedded many circle pin static release ring encapsulating structures are provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that a kind of how base island embedded many circle pin static release ring encapsulating structures; Be characterized in: it comprises outer pin and outer static release ring; Said outer pin is provided with many circles; Said outer pin front forms interior pin through the multilayer plating mode; Said outer static release ring front forms interior static release ring through the multilayer plating mode, and said outer static release ring inside forms interior Ji Dao through the multilayer plating mode, and said interior Ji Dao has a plurality of; Front, basic island is provided with chip in said; Be connected with metal wire between said chip front side and the interior pin front, between chip front side and the interior static release ring front and between chip front side and the chip front side, said in Ji Dao and interior pin top and chip be encapsulated with plastic packaging material outward with metal wire, the zone between regional and outer pin and the outer pin between zone, outer static release ring and the outer pin of said outer pin periphery all is equipped with gap filler; And expose outside the gap filler at the back side of outer pin and outer static release ring, the outer pin outside exposing gap filler and outside the back side of static release ring be provided with second metal level.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
The composition of said second metal level can adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. according to the function of different chips.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because the back surface of the lead frame does not require such a layer of paste-resistant temperature of the film, so that during the process of the package in addition to the conductive or non-conductive adhesive material, but also with eutectic process as well as soft solder process for loading, so a wider choice of species;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
Description of drawings
Fig. 1 is a kind of how base island embedded many circle pin static release ring encapsulating structure sketch mapes of the utility model.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 4 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 5 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer pin 1
Outer static release ring 2
In basic island 3
Interior pin 4
Interior static release ring 5
Chip 6
Metal wire 7
Plastic packaging material 8
Conduction or non-conductive bonding material 9
Second metal level 10
Gap filler 11.
Embodiment
Referring to Fig. 1, Fig. 2; A kind of how base island embedded many circle pin static release ring encapsulating structures of the utility model; It comprises outer pin 1 and outer static release ring 2; Said outer pin 1 is provided with many circles; Static release ring 5 in pin 4 in said outer pin 1 front forms through the multilayer plating mode, said outer static release ring 2 fronts form through the multilayer plating mode, basic island 3 in said outer static release ring 2 inner fronts form through the multilayer plating mode; Basic island 3 has a plurality of in said; Basic island 3, interior pin 4 and interior static release ring 5 are referred to as the first metal layer in said, said in 3 fronts, basic island be provided with chip 6 through conduction or non-conductive bonding material 9, said chip 6 positive with interior pin 4 fronts between, chip 6 is positive with interior static release ring 5 fronts between and be connected with metal wire 7 between chip 6 fronts and chip 6 fronts; Basic island 3, interior pin 4 and interior static release ring 5 tops and chip 6 and the metal wire 7 outer plastic packaging materials 8 that are encapsulated with in said; Zone between peripheral zone, outer static release ring 2 and the outer pin 1 of said outer pin 1 and the zone between outer pin 1 and the outer pin 1 all are equipped with gap filler 11, and the back side of outer pin 1 and outer static release ring 2 exposes outside the gap filler 11, the outer pin 1 outside exposing gap filler 11 and outside the back side of static release ring 2 be provided with second metal level 10.
Basic island 3 in said outer static release ring 2 inner fronts can not form through the multilayer plating mode; Basic island 3 in if outer static release ring 2 inner fronts do not form, chip 6 directly is arranged at gap filler 11 fronts of outer static release ring 2 inside through conduction or non-conductive bonding material 9 at this moment.

Claims (1)

1. base island embedded many circle pin static release ring encapsulating structures more than a kind; It is characterized in that: it comprises outer pin (1) and outer static release ring (2); Said outer pin (1) is provided with many circles; Said outer pin (1) is positive to form interior pin (4) through the multilayer plating mode; Said outer static release ring (2) is positive to form interior static release ring (5) through the multilayer plating mode; Said outer static release ring (2) is inner to form interior Ji Dao (3) through the multilayer plating mode; Ji Dao (3) has a plurality of in said; Ji Dao (3) front is provided with chip (6) in said; Said chip (6) positive with interior pin (4) front between, chip (6) is positive with interior static release ring (5) front between and chip (6) positive with chip (6) front between be connected with metal wire (7), be encapsulated with plastic packaging material (8) outside said interior Ji Dao (3) and interior pin (4) top and chip (6) and the metal wire (7), the zone between regional and outer pin (1) and the outer pin (1) between zone, outer static release ring (2) and the outer pin (1) of said outer pin (1) periphery all is equipped with gap filler (11); And expose outside the gap filler (11) at the back side of outer pin (1) and outer static release ring (2), the outer pin (1) outside exposing gap filler (11) and outside the back side of static release ring (2) be provided with second metal level (10).
CN 201120479943 2011-11-28 2011-11-28 Multi-base embedded multi-pin and electrostatic discharge loop packaging structure Expired - Lifetime CN202394929U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201120479943 CN202394929U (en) 2011-11-28 2011-11-28 Multi-base embedded multi-pin and electrostatic discharge loop packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201120479943 CN202394929U (en) 2011-11-28 2011-11-28 Multi-base embedded multi-pin and electrostatic discharge loop packaging structure

Publications (1)

Publication Number Publication Date
CN202394929U true CN202394929U (en) 2012-08-22

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Application Number Title Priority Date Filing Date
CN 201120479943 Expired - Lifetime CN202394929U (en) 2011-11-28 2011-11-28 Multi-base embedded multi-pin and electrostatic discharge loop packaging structure

Country Status (1)

Country Link
CN (1) CN202394929U (en)

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Granted publication date: 20120822