CN202394906U - Single-island-exposed passive device package structure with single circle of pins - Google Patents
Single-island-exposed passive device package structure with single circle of pins Download PDFInfo
- Publication number
- CN202394906U CN202394906U CN 201120466180 CN201120466180U CN202394906U CN 202394906 U CN202394906 U CN 202394906U CN 201120466180 CN201120466180 CN 201120466180 CN 201120466180 U CN201120466180 U CN 201120466180U CN 202394906 U CN202394906 U CN 202394906U
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- CN
- China
- Prior art keywords
- pin
- passive device
- island
- chip
- dao
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a single-island-exposed passive device package structure with a single circle of pins. The package structure comprises an outer island (1) and an outer pin (2), wherein an inner pin (4) is formed on the front side of the outer pin (2) by multilayer plating; a chip (5) is arranged on the front side of the outer island (1); the front side of the chip (5) is connected with the front side of the inner pin (4) through a metal wire (6); a plastic package material (7) wraps the upper part of the inner pin (4) and the outer parts of the chip (5), the metal wire (6) and a passive device (11); and a second metal layer (9) is arranged on the back side of the outer island (1) and the outer pin (2). The single-island-exposed passive device package structure provided by the utility model has the beneficial effects that the need of a high-temperature resistant film on the back is avoided so as to lower the package cost and widen the range of optional products; the metal wire bonding quality and the product reliability have high stability; and the plastic package body has large metal pin binding capability, thereby realizing high-density capacity of the inner pin.
Description
Technical field
The utility model relates to the base island exposed type individual pen of a kind of list pin passive device encapsulating structure, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 5) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, but also because such a lead frame must be affixed on the back layer of high temperature of the film, during the packaging process so that the loading process can use conductive or non-conductive adhesive material, and can not be used completely eutectic solder process technology and for loading, so choose the types of products have greater limitations;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 4) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; The base island exposed type individual pen of a kind of list pin passive device encapsulating structure is provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that the base island exposed type individual pen of a kind of list pin passive device encapsulating structure; Be characterized in: it comprises outer Ji Dao and outer pin; Said outer pin front forms interior pin through the multilayer plating mode; Pin is the first metal layer in said; Said outer front, basic island is provided with chip, is connected with metal wire between said chip front side and the interior pin front, and cross-over connection has passive device between said interior pin and the interior pin; Pin top and chip, metal wire and passive device are encapsulated with plastic packaging material outward in said; Zone between peripheral zone, outer Ji Dao and the outer pin of said outer pin and the zone between outer pin and the outer pin are equipped with gap filler, and the back side of outer Ji Dao and outer pin exposes outside the gap filler, the outer Ji Dao outside exposing gap filler and outside the back side of pin be provided with second metal level.
Said outer front, basic island forms one or more interior Ji Dao through the multilayer plating mode, and basic island was positive in said chip was arranged at through conduction or non-conductive bonding material.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
The composition of said second metal level can adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. according to the function of different chips.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because the back surface of the lead frame does not require such a layer of paste-resistant temperature of the film, so that during the process of the package in addition to the conductive or non-conductive adhesive material, but also with eutectic process as well as soft solder process for loading, so a wider choice of species;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
Description of drawings
Fig. 1 is the base island exposed type individual pen of a kind of list of a utility model pin passive device encapsulating structure sketch map.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 4 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 5 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer basic island 1
Outer pin 2
In basic island 3
Plastic packaging material 7
Conduction or non-conductive bonding material 8
Second metal level 9
Embodiment
Referring to Fig. 1, Fig. 2; The base island exposed type individual pen of a kind of list of the utility model pin passive device encapsulating structure; It comprises outer basic island 1 and outer pin 2; Said outer 1 front, basic island through the multilayer plating mode form one or more in basic island 3; Pin 4 in outer pin 2 fronts form through the multilayer plating mode, basic island 3 is referred to as the first metal layer with interior pin 4 in said, said in 3 fronts, basic island be provided with chip 5 through conduction or non-conductive bonding material 8; Said chip 5 positive with interior pin 4 fronts between be connected with metal wire 6; Through conduction or 8 cross-over connections of non-conductive bonding material passive device 11 is arranged between pin 4 and the interior pin 4 in said, said in top and chip 5, metal wire 6 and the passive device 11 outer plastic packaging materials 7 that are encapsulated with of basic island 3 and interior pin 4, the zone between regional and outer pin 2 and the outer pin 2 between zone, outer basic island 1 and the outer pin 2 of said outer pin 2 peripheries is equipped with gap filler 10; And gap filler 10 outsides are exposed at the back side of outer basic island 1 and outer pin 2, the outer basic island of exposing gap filler 10 outsides 1 and outside the back side of pin 2 be provided with second metal level 9.
Said outer 1 front, basic island can be not yet through the multilayer plating mode form one or more in basic island 3, if 1 front, outer basic island do not form in basic island 3, this moment, chip 5 directly was arranged at the fronts on outer basic island 1 through conduction or non-conductive bonding material 8.
Claims (2)
1. the base island exposed type individual pen of list pin passive device encapsulating structure; It is characterized in that: it comprises outer Ji Dao (1) and outer pin (2); Said outer pin (2) is positive to form interior pin (4) through the multilayer plating mode; Pin (4) is the first metal layer in said; Said outer Ji Dao (1) front is provided with chip (5); Said chip (5) positive with interior pin (4) front between be connected with metal wire (6); Cross-over connection has passive device (11) between said interior pin (4) and the interior pin (4), the outer plastic packaging material (7) that is encapsulated with of said interior pin (4) top and chip (5), metal wire (6) and passive device (11), and zone between zone, outer Ji Dao (1) and the outer pin (2) of said outer pin (2) periphery and the zone between outer pin (2) and the outer pin (2) are equipped with gap filler (10); And gap filler (10) outside is exposed at the back side of outer Ji Dao (1) and outer pin (2), the outer Ji Dao (1) that exposes gap filler (10) outside and outside the back side of pin (2) be provided with second metal level (9).
2. the base island exposed type individual pen of a kind of list according to claim 1 pin passive device encapsulating structure; It is characterized in that: said outer Ji Dao (1) is positive to form one or more interior Ji Dao (3) through the multilayer plating mode, and said chip (5) is arranged at interior Ji Dao (3) front.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120466180 CN202394906U (en) | 2011-11-22 | 2011-11-22 | Single-island-exposed passive device package structure with single circle of pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120466180 CN202394906U (en) | 2011-11-22 | 2011-11-22 | Single-island-exposed passive device package structure with single circle of pins |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202394906U true CN202394906U (en) | 2012-08-22 |
Family
ID=46669811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120466180 Expired - Lifetime CN202394906U (en) | 2011-11-22 | 2011-11-22 | Single-island-exposed passive device package structure with single circle of pins |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202394906U (en) |
-
2011
- 2011-11-22 CN CN 201120466180 patent/CN202394906U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120822 |