CN202394931U - Packaging structure for multi-circle pins embedded in single-base island - Google Patents

Packaging structure for multi-circle pins embedded in single-base island Download PDF

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Publication number
CN202394931U
CN202394931U CN2011204799621U CN201120479962U CN202394931U CN 202394931 U CN202394931 U CN 202394931U CN 2011204799621 U CN2011204799621 U CN 2011204799621U CN 201120479962 U CN201120479962 U CN 201120479962U CN 202394931 U CN202394931 U CN 202394931U
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China
Prior art keywords
pin
pins
chip
interior
metal
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Expired - Lifetime
Application number
CN2011204799621U
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Chinese (zh)
Inventor
王新潮
梁志忠
谢洁人
吴昊
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN2011204799621U priority Critical patent/CN202394931U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

The utility model relates to a packaging structure for multi-circle pins embedded in a single-base island, which comprises outer pins (1), wherein the outer pins (1) are formed into multiple circles, the front surface of each outer pin (1) is formed into an inner pin (3) by way of multi-layer electroplating, a chip (4) is arranged between the inner pins (3), the front surface of the chip (4) and the front surface of the inner pin (3) are connected by using a metal wire (5), the upper parts of an inner base island (2) and the inner pins (3) as well as the chips (4) and the metal wires (5) are respectively packaged with a molding compound (6), and the back surface of the outer pin (1) is provided with a second metal layer (9). The structure disclosed by the utility model has the advantages that: a high-temperature-resistant film on the back surface of the structure is saved, thereby lowering the packaging cost; the variety of selectable products is wide; the bonding quality of the metal wires and the stability of product reliability are good; and the binding capacities of a molding body and the metal pins are large, thereby realizing the high-density capacity of the inner pins.

Description

Single base island embedded many circle leaded packages
Technical field
The utility model relates to the base island embedded many circle leaded packages of a kind of list, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 2) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 4) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, but also because such a lead frame must be affixed on the back layer of high temperature of the film, during the packaging process so that the loading process can use conductive or non-conductive adhesive material, and can not be used completely eutectic solder process technology and for loading, so choose the types of products have greater limitations;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 3) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; Provide a kind of list base island embedded many circle leaded packages, it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that the base island embedded many circle leaded packages of a kind of list; Be characterized in: it comprises outer pin, and said outer pin is provided with many circles, and said outer pin front forms interior pin through the multilayer plating mode; Be provided with chip between pin and the interior pin in said; Be connected with metal wire between said chip front side and the interior pin front, said in pin top and chip be encapsulated with plastic packaging material outward with metal wire, the zone between regional and the outer pin and the outer pin of said outer pin periphery is equipped with gap filler; And expose outside the gap filler at the back side of outer pin, and the back side of the outer pin outside exposing gap filler is provided with second metal level.
Form interior Ji Dao through the multilayer plating mode between pin and the interior pin in said, basic island was positive in said chip was arranged at.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
The composition of said second metal level can adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. according to the function of different chips.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because the back surface of the lead frame does not require such a layer of paste-resistant temperature of the film, so that during the process of the package in addition to the conductive or non-conductive adhesive material, but also with eutectic process as well as soft solder process for loading, so a wider choice of species;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
Description of drawings
Fig. 1 is the base island embedded many circle leaded package sketch mapes of a kind of list of the utility model.
Fig. 2 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 3 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 4 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer pin 1
In basic island 2
Interior pin 3
Chip 4
Metal wire 5
Plastic packaging material 6
Gap filler 7
Conduction or non-conductive bonding material 8
Second metal level 9.
Embodiment
Referring to Fig. 1; The base island embedded many circle leaded packages of a kind of list of the utility model; It comprises outer pin 1, and said outer pin 1 is provided with many circles, pin 3 in said outer pin 1 front forms through the multilayer plating mode; Basic island 2 in forming through the multilayer plating mode between pin 3 and the interior pin 3 in said; Basic island 2 is referred to as the first metal layer with interior pin 3 in said, said in 2 fronts, basic island be provided with chip 4 through conduction or non-conductive bonding material 8, said chip 4 positive with interior pin 3 fronts between be connected with metal wire 5; Basic island 2 and interior pin 3 tops and chip 4 and the metal wire 5 outer plastic packaging materials 6 that are encapsulated with in said; Zone that said outer pin 1 is peripheral and the zone between outer pin 1 and the outer pin 1 are equipped with gap filler 7, and the back side of outer pin 1 exposes outside the gap filler 7, and the back side of the outer pin 1 outside exposing gap filler 7 is provided with second metal level 9.
Basic island 2 in also can not forming between pin 3 and the interior pin 3 in said through the multilayer plating mode; If basic island 2 in not forming between interior pin 3 and the interior pin 3, gap filler 7 fronts in chip 4 directly is arranged at through conduction or non-conductive bonding material 8 at this moment between pin 3 and the interior pin 3.

Claims (2)

1. base island embedded many circle leaded packages of a list; It is characterized in that: it comprises outer pin (1); Said outer pin (1) is provided with many circles; Said outer pin (1) is positive to form interior pin (3) through the multilayer plating mode, is provided with chip (4) between pin (3) and the interior pin (3) in said, is connected with metal wire (5) between said chip (4) front and interior pin (3) front; The outer plastic packaging material (6) that is encapsulated with of pin (3) top and chip (4) and metal wire (5) in said; Zone that said outer pin (1) is peripheral and the zone between outer pin (1) and the outer pin (1) are equipped with gap filler (7), and the back side of outer pin (1) exposes outside the gap filler (7), and the back side of the outer pin (1) outside exposing gap filler (7) is provided with second metal level (9).
2. the base island embedded many circle leaded packages of a kind of list according to claim 1; It is characterized in that: form interior Ji Dao (2) through the multilayer plating mode between pin (3) and the interior pin (3) in said, said chip (4) is arranged at interior Ji Dao (2) front.
CN2011204799621U 2011-11-28 2011-11-28 Packaging structure for multi-circle pins embedded in single-base island Expired - Lifetime CN202394931U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011204799621U CN202394931U (en) 2011-11-28 2011-11-28 Packaging structure for multi-circle pins embedded in single-base island

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011204799621U CN202394931U (en) 2011-11-28 2011-11-28 Packaging structure for multi-circle pins embedded in single-base island

Publications (1)

Publication Number Publication Date
CN202394931U true CN202394931U (en) 2012-08-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011204799621U Expired - Lifetime CN202394931U (en) 2011-11-28 2011-11-28 Packaging structure for multi-circle pins embedded in single-base island

Country Status (1)

Country Link
CN (1) CN202394931U (en)

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Granted publication date: 20120822

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