CN202394901U - Multi-base-island exposure type single-circle-pin packaging structure - Google Patents
Multi-base-island exposure type single-circle-pin packaging structure Download PDFInfo
- Publication number
- CN202394901U CN202394901U CN2011204661448U CN201120466144U CN202394901U CN 202394901 U CN202394901 U CN 202394901U CN 2011204661448 U CN2011204661448 U CN 2011204661448U CN 201120466144 U CN201120466144 U CN 201120466144U CN 202394901 U CN202394901 U CN 202394901U
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- Prior art keywords
- pin
- dao
- pins
- chip
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a multi-base-island exposure type single-circle-pin packaging structure which includes outer base islands (1) and outer pins (2). A plurality of the outer base islands (1) is arranged, and the outer pins (2) are arranged in a circle. Inner pins (4) are formed on the front faces of the outer pins (2) in a multi-layer electroplating mode. The front faces of the outer base islands (1) are provided with chips (5). The front faces of the chips (5) are connected with the front faces of the inner pins (4) via metal wires (6), and the front faces of the chips (5) are connected with one another via the metal wires (6). The back faces of the outer base islands (1) and the outer pins (2) are provided with a second metal layer (9). The beneficial effects are that a high temperature resistant film on the back is saved, so the packaging cost is reduced; the selectable product types are various; the metal wire bonding quality is excellent, and the reliability and the stability of a product are excellent; and the bonding capability of a plastic packaging body and metal pins is strong, so the high density capability of the inner pins is realized.
Description
Technical field
The utility model relates to a kind of how base island exposed type individual pen leaded package, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 2) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 4) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, also because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; So the load technology in encapsulation process can only be used conduction or nonconducting bonding material; And the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 3) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; A kind of how base island exposed type individual pen leaded package is provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that a kind of how base island exposed type individual pen leaded package; Be characterized in: it comprises outer Ji Dao and outer pin; Said outer Ji Dao is provided with a plurality of, and said outer pin is provided with a circle, and said outer pin front forms interior pin through the multilayer plating mode; Said outer front, basic island is provided with chip; Be connected with metal wire between said chip front side and the interior pin front and between chip front side and the chip front side, said in pin top and chip be encapsulated with plastic packaging material outward with metal wire, the zone between regional and outer pin and the outer pin between zone, outer Ji Dao and the outer pin of said outer pin periphery is equipped with gap filler; And expose outside the gap filler at the back side of outer Ji Dao and outer pin, the outer Ji Dao outside exposing gap filler and outside the back side of pin be provided with second metal level.
Said outer front, basic island forms interior Ji Dao through the multilayer plating mode, and basic island was positive in said chip was arranged at.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
The composition of said second metal level can adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. according to the function of different chips.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because but the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet; So the technology in encapsulation process is except using conduction or nonconducting bonding material; Can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable kind is wider;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
Description of drawings
Fig. 1 is a kind of how base island exposed type individual pen leaded package sketch map of the utility model.
Fig. 2 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 3 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 4 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer basic island 1
In basic island 3
Chip 5
Metal wire 6
Conduction or non-conductive bonding material 8
Second metal level 9
Embodiment
Referring to Fig. 1; A kind of how base island exposed type individual pen leaded package of the utility model; It comprises outer basic island 1 and outer pin 2; Said outer basic island 1 is provided with a plurality of, and said outer pin 2 is provided with a circle, basic island 3 in said outer 1 front, basic island forms through the multilayer plating mode; Pin 4 in said outer pin 2 fronts form through the multilayer plating mode; Basic island 3 is referred to as the first metal layer with interior pin 4 in said, said in 3 fronts, basic island be provided with chip 5 through conduction or non-conductive bonding material 8, said chip 5 positive with interior pin 4 fronts between and be connected with metal wire 6 between chip 5 fronts and chip 5 fronts; Basic island 3 and interior pin 4 tops and chip 5 and the metal wire 6 outer plastic packaging materials 7 that are encapsulated with in said; Zone between peripheral zone, outer basic island 1 and the outer pin 2 of said outer pin 2 and the zone between outer pin 2 and the outer pin 2 are equipped with gap filler 10, and the back side of outer basic island 1 and outer pin 2 exposes outside the gap filler 10, the outer basic island 1 outside exposing gap filler 10 and outside the back side of pin 2 be provided with second metal level 9.
Basic island 3 in said outer 1 front, basic island also can not form through the multilayer plating mode, if 1 front, outer basic island do not form in basic island 3, this moment, chip 5 directly was arranged at the fronts on outer basic island 1 through conduction or non-conductive bonding material 8.
Claims (2)
1. base island exposed type individual pen leaded package more than a kind; It is characterized in that: it comprises outer Ji Dao (1) and outer pin (2); Said outer Ji Dao (1) is provided with a plurality of; Said outer pin (2) is provided with a circle; Said outer pin (2) is positive to form interior pin (4) through the multilayer plating mode; Said outer Ji Dao (1) front is provided with chip (5); Said chip (5) positive with interior pin (4) front between and chip (5) positive with chip (5) front between is connected with metal wire (6), be encapsulated with plastic packaging material (7) outside said interior pin (4) top and chip (5) and the metal wire (6), the zone between regional and outer pin (2) and the outer pin (2) between zone, outer Ji Dao (1) and the outer pin (2) of said outer pin (2) periphery is equipped with gap filler (10); And expose outside the gap filler (10) at the back side of outer Ji Dao (1) and outer pin (2), the outer Ji Dao (1) outside exposing gap filler (10) and outside the back side of pin (2) be provided with second metal level (9).
2. a kind of how base island exposed type individual pen leaded package according to claim 1 is characterized in that: said outer Ji Dao (1) is positive to form interior Ji Dao (3) through the multilayer plating mode, and said chip (5) is arranged at interior Ji Dao (3) front.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011204661448U CN202394901U (en) | 2011-11-22 | 2011-11-22 | Multi-base-island exposure type single-circle-pin packaging structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011204661448U CN202394901U (en) | 2011-11-22 | 2011-11-22 | Multi-base-island exposure type single-circle-pin packaging structure |
Publications (1)
Publication Number | Publication Date |
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CN202394901U true CN202394901U (en) | 2012-08-22 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN2011204661448U Expired - Lifetime CN202394901U (en) | 2011-11-22 | 2011-11-22 | Multi-base-island exposure type single-circle-pin packaging structure |
Country Status (1)
Country | Link |
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CN (1) | CN202394901U (en) |
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2011
- 2011-11-22 CN CN2011204661448U patent/CN202394901U/en not_active Expired - Lifetime
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Legal Events
Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20120822 |