CN202394908U - Base-free chip upside-down packaging structure - Google Patents
Base-free chip upside-down packaging structure Download PDFInfo
- Publication number
- CN202394908U CN202394908U CN2011204661842U CN201120466184U CN202394908U CN 202394908 U CN202394908 U CN 202394908U CN 2011204661842 U CN2011204661842 U CN 2011204661842U CN 201120466184 U CN201120466184 U CN 201120466184U CN 202394908 U CN202394908 U CN 202394908U
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- China
- Prior art keywords
- pin
- chip
- outer pin
- lead frame
- front surface
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a base-free chip upside-down packaging structure which comprises outer pins (1), wherein the front surface of each outer pin (1) forms an inner pin (2) in a multilayer electroplating mode; a chip (3) is bridged between the front surface of the inner pin (2) and the front surface of the inner pin (2); a tin sphere (8) is arranged between the front surface of the inner pin (2) and the chip (3); the upper part of the inner pin (2) and the chip (3) is coated with a plastic sealing material (5); the peripheral region of the outer pin (1), and the region between the outer pin (1) and the outer pin (1) are embedded with a gap filler (6); and the back surface of each outer pin (1) is provided with a second metal layer (7). The utility model saves the high-temperature-resistant adhesive film on the back surface, and lowers the packaging cost; the quality of ball bonding, and the reliability and stability of the product are good; and the binding capacity between the plastic sealing body and the metal pins is high, thereby implementing high-density capacity of the inner pins.
Description
Technical field
The utility model relates to a kind of no basic island flip chip encapsulation structure, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 2) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 4) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, also because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; So need use the interior pin of 300 ℃ of high temperature tin materials and lead frame to carry out interconnected during the load operation in encapsulation process; And the lead frame back side is because will prevent must stick the flash that the plastic packaging operation in the dress technological process causes the soft glued membrane of high temperature resistance; Though be the high temperature resistance form; But also can only bear about 260 ℃ temperature, the interior pin that can not adapt to needed 300 ℃ of high temperature tin materials of flip-chip and lead frame fully carries out interconnected ability.
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 3) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature the interior pin of 300 ℃ of high temperature tin materials and lead frame carry out when interconnected; Easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; A kind of no basic island flip chip encapsulation structure is provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of flip-chip bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that a kind of no basic island flip chip encapsulation structure; Be characterized in: it comprises outer pin; Said outer pin front forms interior pin through the multilayer plating mode, and cross-over connection has chip between said interior pin front and the interior pin front, is provided with the tin ball between said interior pin front and the chip; Pin top and chip are encapsulated with plastic packaging material outward in said; Zone that said outer pin is peripheral and the zone between outer pin and the outer pin all are equipped with gap filler, and the back side of outer pin exposes outside the gap filler, and the outer pin back side outside exposing gap filler is provided with second metal level.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
The composition of said second metal level can adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. according to different chips.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because but the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet; So carry out when interconnected at the interior pin of 300 ℃ of high temperature tin materials of the required use of flip-chip and lead frame, all-metal lead frame can not produce because of different material in correspondence distortion that high temperature produced;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 3, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
4, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
5, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the heat-sinking capability of chip is also quickened heat radiation because of reduced distances;
6, also because the distance of chip and interior pin significantly shortens and makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the distance of chip and interior pin has significantly shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
7, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
8, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
Description of drawings
Fig. 1 is a kind of no basic island of the utility model flip chip encapsulation structure sketch map.
Fig. 2 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 3 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 4 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Conduction or non-conductive bonding material 4
Embodiment
Referring to Fig. 1; A kind of no basic island of the utility model flip chip encapsulation structure, it comprises outer pin 1, pin 2 in said outer pin 1 front forms through the multilayer plating mode; Through conduction or 4 cross-over connections of non-conductive bonding material chip 3 is arranged between pin 2 fronts and interior pin 2 fronts in said; Be provided with tin ball 8 between pin 2 fronts and the chip 3 in said, said interior pin 2 tops and the chip 3 outer plastic packaging materials 5 that are encapsulated with, the zone of said outer pin 1 periphery and the zone between outer pin 1 and the outer pin 1 all are equipped with gap filler 6; And expose outside the gap filler 6 at the back side of outer pin 1, and outer pin 1 back side outside exposing gap filler 6 is provided with second metal level 7.
Claims (1)
1. no basic island flip chip encapsulation structure; It is characterized in that: it comprises outer pin (1); Said outer pin (1) is positive to form interior pin (2) through the multilayer plating mode; Cross-over connection has chip (3) between said interior pin (2) front and interior pin (2) front; Be provided with tin ball (8) between pin (2) front and the chip (3) in said, the outer plastic packaging material (5) that is encapsulated with of said interior pin (2) top and chip (3), zone that said outer pin (1) is peripheral and the zone between outer pin (1) and the outer pin (1) all are equipped with gap filler (6); And expose outside the gap filler (6) at the back side of outer pin (1), and outer pin (1) back side outside exposing gap filler (6) is provided with second metal level (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204661842U CN202394908U (en) | 2011-11-22 | 2011-11-22 | Base-free chip upside-down packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204661842U CN202394908U (en) | 2011-11-22 | 2011-11-22 | Base-free chip upside-down packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202394908U true CN202394908U (en) | 2012-08-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204661842U Expired - Lifetime CN202394908U (en) | 2011-11-22 | 2011-11-22 | Base-free chip upside-down packaging structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN202394908U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489792A (en) * | 2013-08-06 | 2014-01-01 | 江苏长电科技股份有限公司 | Encapsulation-etching three-dimensional system-level chip inversion encapsulation structure and process method |
-
2011
- 2011-11-22 CN CN2011204661842U patent/CN202394908U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489792A (en) * | 2013-08-06 | 2014-01-01 | 江苏长电科技股份有限公司 | Encapsulation-etching three-dimensional system-level chip inversion encapsulation structure and process method |
| CN103489792B (en) * | 2013-08-06 | 2016-02-03 | 江苏长电科技股份有限公司 | First be honored as a queen and lose three-dimensional systematic flip chip encapsulation structure and process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170111 Address after: Tianjin free trade zone (Dongjiang Bonded Port) No. 6865 North Road, 1-1-1802-7 financial and trade center of Asia Patentee after: Xin Xin finance leasing (Tianjin) Co., Ltd. Address before: 214434 Binjiang Middle Road, Jiangyin Development Zone, Jiangsu, China, No. 275, No. Patentee before: Jiangsu Changdian Sci. & Tech. Co., Ltd. |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd. Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd. Contract record no.: 2017320000152 Denomination of utility model: Base-free chip upside-down packaging structure Granted publication date: 20120822 License type: Exclusive License Record date: 20170614 |
|
| EC01 | Cancellation of recordation of patent licensing contract | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd. Contract record no.: 2017320000152 Date of cancellation: 20200416 |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200424 Address after: 214434, No. 78, mayor road, Chengjiang, Jiangsu, Jiangyin, Wuxi Patentee after: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port Area) Patentee before: Xin Xin finance leasing (Tianjin) Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120822 |