CN202394927U - Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure - Google Patents

Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure Download PDF

Info

Publication number
CN202394927U
CN202394927U CN2011204799388U CN201120479938U CN202394927U CN 202394927 U CN202394927 U CN 202394927U CN 2011204799388 U CN2011204799388 U CN 2011204799388U CN 201120479938 U CN201120479938 U CN 201120479938U CN 202394927 U CN202394927 U CN 202394927U
Authority
CN
China
Prior art keywords
pin
release ring
static release
chip
interior
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2011204799388U
Other languages
Chinese (zh)
Inventor
王新潮
梁志忠
谢洁人
吴昊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN2011204799388U priority Critical patent/CN202394927U/en
Application granted granted Critical
Publication of CN202394927U publication Critical patent/CN202394927U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure, comprising outer pins (1) and an outer electrostatic discharge ring (2), wherein an inner pin (4) is formed on the front face of each outer pin (1) in a multi-layer electroplating manner; inner base islands (3) are formed inside the outer electrostatic discharge ring (2) in the multi-layer electroplating manner; a chip (6) is arranged on the front face of each inner base island (3); the front face of the chip (6) and the front face of the inner pin (4), and the front faces of the chips (6) are connected by metal wires (7), respectively; a passive device (12) is spanned between the inner pins (4); and a second metal layer (10) is arranged between the rear faces of the outer pin (1) and the outer electrostatic discharge ring (2). The multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure has the following advantages that: a high-temperature resistant coating on the rear face is omitted so that the packaging cost is reduced; the quality of the bonding of the metal wire and the stability of the reliability of the product are good; and the high-density capability of the inner pins is realized.

Description

Many base island embedded individual pen pin static release ring passive device encapsulating structures
Technical field
The utility model relates to a kind of how basic island individual pen pin static release ring passive device encapsulating structure, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 5) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, but also because such a lead frame must be affixed on the back layer of high temperature of the film, during the packaging process so that the loading process can use conductive or non-conductive adhesive material, and can not be used completely eutectic solder process technology and for loading, so choose the types of products have greater limitations;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 4) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; A kind of how base island embedded individual pen pin static release ring passive device encapsulating structure is provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that a kind of how base island embedded individual pen pin static release ring passive device encapsulating structure; Be characterized in: it comprises outer pin and outer static release ring; Said outer pin front forms interior pin through the multilayer plating mode; Said outer static release ring front forms interior static release ring through the multilayer plating mode; Said outer static release ring inside forms interior Ji Dao through the multilayer plating mode, said in Ji Dao have a plurality of, said in front, basic island be provided with chip; Be connected with metal wire between said chip front side and the interior pin front, between chip front side and the interior static release ring front and between chip front side and the chip front side; Cross-over connection has passive device between said interior pin and the interior pin, and said interior Ji Dao and interior pin top and chip and metal wire are encapsulated with plastic packaging material outward, and zone between zone, outer static release ring and the outer pin of said outer pin periphery and the zone between outer pin and the outer pin all are equipped with gap filler; And expose outside the gap filler at the back side of outer pin and outer static release ring, the outer pin outside exposing gap filler and outside the back side of static release ring be provided with second metal level.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
The composition of said second metal level can adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. according to the function of different chips.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because the back surface of the lead frame does not require such a layer of paste-resistant temperature of the film, so that during the process of the package in addition to the conductive or non-conductive adhesive material, but also with eutectic process as well as soft solder process for loading, so a wider choice of species;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
Description of drawings
Fig. 1 is a kind of how base island embedded individual pen pin static release ring passive device encapsulating structure sketch map of the utility model.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 4 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 5 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer pin 1
Outer static release ring 2
In basic island 3
Interior pin 4
Interior static release ring 5
Chip 6
Metal wire 7
Plastic packaging material 8
Conduction or non-conductive bonding material 9
Second metal level 10
Gap filler 11
Passive device 12.
Embodiment
Referring to Fig. 1, Fig. 2; A kind of how base island embedded individual pen pin static release ring passive device encapsulating structure of the utility model; It comprises outer pin 1 and outer static release ring 2; Pin 4 in said outer pin 1 front forms through the multilayer plating mode; Static release ring 5 in said outer static release ring 2 fronts form through the multilayer plating mode; Said outer static release ring 2 inner positive form through the multilayer plating mode in basic island 3, said in basic island 3 have a plurality ofly, basic island 3, interior pin 4 and interior static release ring 5 are referred to as the first metal layer in said; 3 fronts, basic island are provided with chip 6 through conduction or non-conductive bonding material 9 in said; Said chip 6 positive with interior pin 4 fronts between, chip 6 is positive with interior static release ring 5 fronts between and chip 6 positive with chip 6 fronts between be connected with metal wire 7, be encapsulated with plastic packaging materials 8 outside basic island 3, interior pin 4 and interior static release ring 5 tops and chip 6 and the metal wire 7 in said, the zone between regional and outer pin 1 and the outer pin 1 between zone, outer static release ring 2 and the outer pin 1 of said outer pin 1 periphery all is equipped with gap filler 11; And expose outside the gap filler 11 at the back side of outer pin 1 and outer static release ring 2, the outer pin 1 outside exposing gap filler 11 and outside the back side of static release ring 2 be provided with second metal level 10.
Basic island 3 in said outer static release ring 2 inner fronts can not form through the multilayer plating mode; Basic island 3 in if outer static release ring 2 inner fronts do not form, chip 6 directly is arranged at gap filler 11 fronts of outer static release ring 2 inside through conduction or non-conductive bonding material 9 at this moment.

Claims (1)

1. base island embedded individual pen pin static release ring passive device encapsulating structure more than a kind; It is characterized in that: it comprises outer pin (1) and outer static release ring (2); Said outer pin (1) is positive to form interior pin (4) through the multilayer plating mode; Said outer static release ring (2) is positive to form interior static release ring (5) through the multilayer plating mode; Said outer static release ring (2) is inner to form interior Ji Dao (3) through the multilayer plating mode; Ji Dao (3) has a plurality of in said; Ji Dao (3) front is provided with chip (6) in said; Said chip (6) positive with interior pin (4) front between, chip (6) is positive with interior static release ring (5) front between and be connected with metal wire (7) between chip (6) front and chip (6) front; Cross-over connection has passive device (12) between said interior pin (4) and the interior pin (4), the outer plastic packaging material (8) that is encapsulated with of said interior Ji Dao (3) and interior pin (4) top and chip (6) and metal wire (7), and zone between zone, outer static release ring (2) and the outer pin (1) of said outer pin (1) periphery and the zone between outer pin (1) and the outer pin (1) all are equipped with gap filler (11); And expose outside the gap filler (11) at the back side of outer pin (1) and outer static release ring (2), the outer pin (1) outside exposing gap filler (11) and outside the back side of static release ring (2) be provided with second metal level (10).
CN2011204799388U 2011-11-28 2011-11-28 Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure Expired - Lifetime CN202394927U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011204799388U CN202394927U (en) 2011-11-28 2011-11-28 Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011204799388U CN202394927U (en) 2011-11-28 2011-11-28 Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure

Publications (1)

Publication Number Publication Date
CN202394927U true CN202394927U (en) 2012-08-22

Family

ID=46669832

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011204799388U Expired - Lifetime CN202394927U (en) 2011-11-28 2011-11-28 Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure

Country Status (1)

Country Link
CN (1) CN202394927U (en)

Similar Documents

Publication Publication Date Title
CN202394926U (en) Multi-base embedded multi-loop-pin packaging structure
CN202394898U (en) Single-base-island exposure type single-circle-pin packaging structure
CN202394868U (en) Packaging structure of passive devices of single-base-island exposed type multi-circle pin electrostatic discharge rings
CN202394925U (en) Structure for packaging static releasing rings by embedding single circle of pin through plurality of base islands
CN202394904U (en) Single-base exposed single-loop-pin electrostatic discharge loop passive device packaging structure
CN202394897U (en) Encapsulation structure of multi-base-island exposed type single-circle pin passive device
CN202394927U (en) Multi-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure
CN202394932U (en) Single-base island embedded single-circle pin electrostatic discharge ring-passive device packaging structure
CN202394877U (en) Multiple base island embedded single-circle pin and passive device packaging structure
CN202394928U (en) Multi-base island embedded multi-circle pin passive device packaging structure
CN202394876U (en) Passive device packaging structure embedded with single base island and provided with multi-ring pins and electrostatic release ring
CN202394874U (en) Single base island embedded multi-circle pin and electrostatic discharge ring packaging structure
CN202394873U (en) Single-base-island exposure type single-circle-pin ball grid array packaging structure
CN202394934U (en) Structure for packaging static releasing ring by embedding single circle of pin through single base island
CN202394902U (en) Multi-base-island exposure type single-circle-pin electrostatic release ring packaging structure
CN202394894U (en) Multiple base-exposed single-pin circle electrostatic discharge ring passive device packaging structure
CN202394914U (en) Multiple base island exposed single-circle pin and ball grid array packaging structure
CN202394930U (en) Single-base island embedded single-circle pin passive device packaging structure
CN202394899U (en) Single-base-island exposure type single-circle-pin electrostatic release ring packaging structure
CN202394923U (en) Encapsulation structure of multi-basic island embedded type passive device with multi-coil pins and static release coils
CN202394866U (en) Packaging structure of multi-base-island exposed type multi-circle pin electrostatic discharge rings
CN202394929U (en) Multi-base embedded multi-pin and electrostatic discharge loop packaging structure
CN202394906U (en) Single-island-exposed passive device package structure with single circle of pins
CN202394895U (en) Single-base-island exposure type multi-circle-pin electrostatic release ring packaging structure
CN202394875U (en) Passive device packaging structure embedded with single base island and provided with multi-ring pins

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20120822