CN202309631U

CN202309631U - Two-path error amplifier

Info

Publication number: CN202309631U
Application number: CN2011204418013U
Authority: CN
Inventors: 吴剑辉; 詹桦; 吴建兴
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2011-11-09
Filing date: 2011-11-09
Publication date: 2012-07-04
Anticipated expiration: 2021-11-09

Abstract

The utility model discloses a two-path error amplifier. The two-path error amplifier comprises a first error amplifier and a second error amplifier; the first error amplifier comprises first current sources, a first differential input geminate transistor, a first active load and a mirror image tube; and the second error amplifier comprises fourth current sources, a second differential input geminate transistor and a second active load. By adjusting the structure of the two-path error amplifier, and the two current sources are added in the first error amplifier or the second error amplifier, and current values in the two-path error amplifier are set, so that a correct direct current bias point of the first error amplifier or the second error amplifier can be set in a constant current mode, thereby the first error amplifier or the second error amplifier in the constant current mode works in a normal saturation zone; and when the two-path error amplifier is applied in the constant voltage and constant current, an output port of the two-path error amplifier can always supply a stable operating voltage.

Description

A kind of two-way error amplifier

Technical field

The utility model relates to the error amplifier technology, relates in particular to a kind of structure of two-way error amplifier.

Background technology

Some circuit need be realized constant voltage and constant current function simultaneously; Usually need to use the two-way error amplifier; As shown in Figure 1, it is the module diagram of a kind of two-way error amplifier in the prior art, and said current error amplifier 11 comprises positive input IN+, negative input IN-and output; Said voltage error amplifier 12 comprises positive input VN+, negative input VN-and output, and the output of said voltage error amplifier 12 links to each other with the output of current error amplifier 11, and is connected in output port OUT.

Two-way error amplifier shown in Figure 1 has and only has two kinds of operating states:

First kind is constant voltage mode, and the positive input voltage VN+ of voltage error amplifier 12 equals the positive input voltage IN+ of its negative input voltage VN-, current error amplifier 11 less than its negative input voltage IN-;

Second kind is constant current mode, and the positive input voltage IN+ of current error amplifier 11 equals the positive input voltage VN+ of its negative input voltage IN-, voltage error amplifier 12 less than its negative input voltage VN-.

Fig. 2 is a kind of concrete realization sketch map of the circuit of two-way error amplifier as shown in Figure 1.As shown in Figure 2; Said current error amplifier 11 comprises the first current source I12, PMOS pipe M12 and the 2nd PMOS pipe M22, NMOS pipe M32, the 2nd NMOS pipe M42 and the 3rd NMOS pipe M52; The grid of said PMOS pipe M12 is managed the negative input IN-of the grid of M22 as said voltage error amplifier as the positive input IN+ of said current error amplifier, said the 2nd PMOS; The drain electrode of said the 3rd NMOS pipe M52 and the output of said voltage error amplifier 12 link to each other, and as output port OUT;

Said voltage error amplifier 12 comprises the second current source I11, the 3rd PMOS pipe M11 and the 4th PMOS pipe M21, the 3rd NMOS pipe M31 and the 4th NMOS pipe M41; The grid of said the 4th PMOS pipe M21 is managed the negative input mouth VN-of the grid of M11 as said voltage error amplifier as the positive input VN+ of said voltage error amplifier, said the 3rd PMOS; The drain electrode of said the 4th PMOS pipe M21 links to each other with the drain electrode of said the 4th NMOS pipe M41; And link to each other with the output of said current error amplifier 11, as output port OUT.

Wherein, For voltage error amplifier 12; M11 and coupling identical with the M21 breadth length ratio, M31 is identical with the M41 breadth length ratio and coupling; When said two-way error amplifier was operated in constant voltage mode, the voltage of the negative input mouth VN-of the voltage of the positive input VN+ of said voltage error amplifier 12 and said voltage error amplifier equated;

For current error amplifier 11; M12 and coupling identical with the M22 breadth length ratio, M32 is identical with the M42 breadth length ratio and coupling, M52 as output; When said two-way error amplifier was operated in constant current mode, the voltage of the voltage of the positive input IN+ of said current error amplifier 11 and the negative input IN-of said current error amplifier equated:

When the two-way error amplifier was operated in constant current mode, the positive input voltage VN+ of voltage error amplifier 12 was less than its negative input voltage VN-, so the output current of voltage error amplifier equals I11.The drain-source current of M52 is the output current I11 that the output current of current error amplifier equals voltage error amplifier in the current error amplifier; But M52 is with the connected mode between M42 and the voltage error amplifier; M52 makes the grid voltage of M52 uncertain, can't set correct direct current biasing point, so can not guarantee to be operated in the saturation region always; When constant current mode, the output port OUT of two-way error amplifier can not provide stable voltage like this.

The utility model content

The utility model is to the deficiency of prior art; A kind of structure of two-way error amplifier is provided; Current value through each current source in setting voltage error amplifier and the current error amplifier; Thereby set the correct direct current biasing point of current error amplifier, the current error amplifier when making constant current mode can be operated in normal saturation region always.

For solving the problems of the technologies described above; The utility model provides a kind of two-way error amplifier; Comprise first error amplifier and second error amplifier; The output of said first error amplifier is connected with the output of said second error amplifier, and as the output port of two-way error amplifier, said first error amplifier comprises:

First current source links to each other with external power source or with ground;

First difference input is to pipe, and two ends are respectively as the positive input and the negative input of said first error amplifier, and wherein an end links to each other with said first current source;

First active load; The two ends parallel connection inserts second current source and the 3rd current source; One end of said first active load links to each other to managing with the input of first difference, and when first current source linked to each other with external power source, the other end of first active load linked to each other with ground; When first current source linked to each other with ground, the other end of said first active load linked to each other with external power source;

Be used for the mirror image pipe with the current mirror output of said active load, the one of which end links to each other with active load, and the other end is as the output of first error amplifier;

Said second error amplifier comprises:

The 4th current source links to each other with external power source or with ground;

Second difference input is to pipe, and two ends are respectively as the positive input and the negative input of said second error amplifier, and wherein an end links to each other with said the 4th current source;

Second active load; One end links to each other to managing with the input of second difference, and when first current source linked to each other with external power source, the other end of said second active load linked to each other with ground; When first current source linked to each other with ground, the other end of said second active load linked to each other with external power source.

As optional scheme, said first error amplifier further comprises:

Said first current source links to each other with external power source;

Said first difference input comprises PMOS pipe and the 2nd PMOS pipe to pipe; The grid of said PMOS pipe is as the positive input of said first error amplifier; The said second gate pmos utmost point is as the negative input of said first error amplifier, and the source electrode of said PMOS pipe links to each other with said first current source with the source electrode of said the 2nd PMOS pipe jointly;

Said first active load comprises NMOS pipe and the 2nd NMOS pipe; The drain electrode of said NMOS pipe links to each other with the drain electrode of its grid with said PMOS pipe; The drain electrode of said the 2nd NMOS pipe links to each other with the drain electrode of its grid with said the 2nd PMOS pipe, the source electrode common ground of the source electrode of said the 2nd NMOS pipe and said NMOS pipe;

Said mirror image pipe comprises the 3rd NMOS pipe, and the grid of said the 3rd PMOS pipe links to each other with the grid of said the 2nd NMOS pipe and drains as the output of said first error amplifier;

The two ends of said second current source link to each other with source electrode with the drain electrode of said NMOS pipe respectively;

The two ends of said the 3rd current source link to each other with source electrode with the drain electrode of said the 2nd NMOS pipe respectively.

Further; The said first current source current value is I1, and the current value of said second current source and said the 3rd current source is I2, and satisfies I1＞2 * I2; Said PMOS pipe is identical with the breadth length ratio of said the 2nd PMOS pipe; Said NMOS pipe is identical with said the 2nd NMOS pipe breadth length ratio, and the breadth length ratio of said the 3rd NMOS pipe is N a times of said the 2nd NMOS pipe breadth length ratio, and wherein N is a positive number.

Further; When the magnitude of voltage of the positive input of said first error amplifier equals the magnitude of voltage of negative input of said first error amplifier; The drain-source current of the drain-source current of said PMOS pipe and said the 2nd PMOS pipe is I1/2; The drain-source current of said NMOS pipe is I2 with the drain-source current of said the 2nd NMOS pipe, and the drain-source current that said the 3rd NMOS manages is N * (I1/2-I2).

As optional scheme, said first error amplifier further comprises:

Said first current source links to each other with ground;

Said first difference input comprises NMOS pipe and the 2nd NMOS pipe to pipe; The grid of said NMOS pipe is as the positive input of said first error amplifier; The grid of said the 2nd NMOS pipe is as the negative input of said first error amplifier, and the source electrode of said NMOS pipe links to each other with said first current source with the source electrode of said the 2nd NMOS pipe jointly;

Said first active load comprises PMOS pipe and the 2nd PMOS pipe, and the drain electrode of said PMOS pipe links to each other with the drain electrode of its grid with said NMOS pipe; The drain electrode of said the 2nd PMOS pipe links to each other with the drain electrode of its grid with said the 2nd NMOS pipe, and the source electrode of said the 2nd PMOS pipe links to each other with external power source with the source electrode of said PMOS pipe jointly;

Said mirror image pipe comprises the 3rd PMOS pipe, and the grid of said the 3rd PMOS pipe links to each other with the grid of said the 2nd PMOS pipe, and drain electrode is as the output of said first error amplifier;

The two ends of said second current source link to each other with source electrode with the drain electrode of said PMOS pipe respectively;

The two ends of said the 3rd current source link to each other with source electrode with the drain electrode of said the 2nd PMOS pipe respectively.

As optional scheme, said first error amplifier further comprises:

Said first current source links to each other with external power source;

Said first difference input comprises PNP pipe and the 2nd PNP pipe to pipe; The base stage of said PNP pipe is as the positive input of said first error amplifier; The base stage of said the 2nd PNP pipe is as the negative input of said first error amplifier, and the emitter of said PNP pipe links to each other with said first current source with the emitter of said the 2nd PNP pipe jointly;

Said first active load comprises NMOS pipe and the 2nd NMOS pipe, and the drain electrode of said NMOS pipe links to each other with the collector electrode of said PNP pipe; The drain electrode of said the 2nd NMOS pipe links to each other with the collector electrode of said the 2nd PNP pipe, the source electrode common ground of the source electrode of said the 2nd NMOS pipe and said NMOS pipe;

Said mirror image pipe comprises the 3rd NMOS pipe, and its grid links to each other with the grid of said the 2nd NMOS pipe, and the drain electrode of said the 3rd NMOS pipe is as the output of said first error amplifier;

As optional scheme, said second error amplifier further comprises:

The 4th current source links to each other with external power source;

The input of second difference comprises the 3rd PMOS pipe and the 4th PMOS pipe to pipe; The grid of said the 3rd PMOS pipe is as the negative input of said second error amplifier; The grid of said the 4th PMOS pipe links to each other, drains as the output of said second error amplifier with the source electrode of said the 3rd PMOS pipe as positive input, the source electrode of said second error amplifier, and the source electrode of said the 3rd PMOS pipe and the 4th PMOS pipe links to each other with said the 4th current source jointly;

Said second active load comprises the 4th NMOS pipe and the 5th NMOS pipe; The drain electrode of said the 4th NMOS pipe links to each other with the drain electrode of its grid with said the 3rd PMOS pipe; The grid of said the 5th NMOS pipe links to each other with the grid of said the 4th NMOS pipe; The source electrode common ground of the source electrode of said the 5th NMOS pipe and said the 4th NMOS pipe, the drain electrode of said the 5th NMOS pipe links to each other with the drain electrode of said the 4th PMOS pipe.

Further; The said first current source current value is I1, and the current value of said second current source and said the 3rd current source is I2, and satisfies I1＞2 * I2; The current value of said the 4th current source is N * (I1/2-I2); Said the 3rd PMOS pipe is identical with the breadth length ratio of said the 4th PMOS pipe, and said the 4th NMOS pipe is identical with the breadth length ratio of said the 5th NMOS pipe, and wherein N is a positive number.

Further, the magnitude of voltage of the positive input of said second error amplifier is during less than the magnitude of voltage of the negative input of said second error amplifier, and the drain-source current value of said the 4th PMOS pipe is N * (I1/2-I2).

As optional scheme, said second error amplifier further comprises:

The 4th current source links to each other with external power source;

The input of second difference comprises the 3rd PNP pipe and the 4th PNP pipe to pipe; The base stage of said the 3rd PNP pipe is as the negative input of said second error amplifier; The base stage of said the 4th PNP pipe as the emitter of the positive input of said second error amplifier, said the 3rd PNP pipe link to each other with the 4th current source jointly with the emitter of said the 4th PNP pipe, the collector electrode of said the 4th PNP pipe is as the output of said second error amplifier, the collector electrode that said the 3rd PNP manages links to each other with said the 4th current source;

Said second active load comprises the 4th NMOS pipe and the 5th NMOS pipe; The drain electrode of said the 4th NMOS pipe is connected with its grid and drain electrode links to each other with the collector electrode of said the 3rd PNP pipe; The grid of said the 5th NMOS pipe links to each other with the grid of said the 4th NMOS pipe; The source electrode common ground of the source electrode of said the 5th NMOS pipe and said the 4th NMOS pipe, the drain electrode of said the 5th NMOS pipe links to each other with the collector electrode of said the 4th PNP pipe.

Optional, said first error amplifier is the current error amplifier, said second error amplifier is a voltage error amplifier; Also can be, said first error amplifier be a voltage error amplifier, and said second error amplifier is the current error amplifier.

With said first error amplifier is the current error amplifier; Said second error amplifier is that voltage error amplifier is an example; The magnitude of voltage of positive input that equals the voltage of the negative input of said voltage error amplifier, said current error amplifier when the magnitude of voltage of the positive input of said voltage error amplifier is less than the magnitude of voltage of the negative input of said current error amplifier; When being constant voltage mode; The said first current source current value is I1, and the current value of said second current source and said the 3rd current source is I2, and satisfies I1＞2 * I2; The drain-source current of the drain-source current of said the 4th PMOS pipe and said the 5th NMOS pipe is that 1/2 * N * (I1/2-I2), therefore the output current of said voltage error amplifier equals 0; Because the drain-source current of said the 3rd NMOS pipe equals 0; The output current of said current error amplifier equals 0; Output current when the output current when this electric current just in time equals voltage error amplifier and is operated in the saturation region, the output current of promptly said current error amplifier equal said voltage error amplifier and be operated in the saturation region.

Simultaneously; When the magnitude of voltage of the positive input of the said voltage error amplifier magnitude of voltage less than the negative input of the magnitude of voltage of the positive input of the voltage of the negative input of said voltage error amplifier, said current error amplifier and said current error amplifier equates; When being constant current mode; The drain-source current of said the 4th PMOS pipe is N * (I1/2-I2); Drain-source current when said the 3rd NMOS pipe of the output current when this electric current just in time equals the current error amplifier and is operated in the saturation region is operated in the saturation region; Output current when therefore the output current of said voltage error amplifier equals said current error amplifier and is operated in the saturation region, thus make in the current error amplifier the 3rd NMOS pipe can set correct direct current biasing point, and then make it be operated in normal saturation region.

Said first error amplifier is the current error amplifier, when said second error amplifier is voltage error amplifier, can realize above-mentioned functions equally.

Than prior art, the utility model is through adjusting the mutual conductance of current error amplifier when having reduced constant current mode to the structure of current error amplifier in the two-way error amplifier; Through in said current error amplifier, increasing by two current sources and setting each current value in the two-way error amplifier; Setting the correct direct current biasing point of current error amplifier under the constant current mode, thereby the current error amplifier when making constant current mode is operated in normal saturation region.

Description of drawings

Below in conjunction with accompanying drawing and embodiment present technique is further specified.

Fig. 1 is the module diagram of a kind of two-way error amplifier in the prior art.

Fig. 2 is the circuit diagram of two-way error amplifier as shown in Figure 1.

Fig. 3 is the module diagram of two-way error amplifier described in the utility model one embodiment.

Fig. 4 is the circuit diagram of two-way error amplifier among first embodiment.

Fig. 5 is the circuit diagram of two-way error amplifier among second embodiment.

Fig. 6 is the circuit diagram of two-way error amplifier among the 3rd embodiment.

Embodiment

For the content that makes the utility model is clear more understandable,, the content of the utility model is described further below in conjunction with Figure of description.Certainly the utility model is not limited to this specific embodiment, and the general replacement that those skilled in the art knew also is encompassed in the protection range of the utility model.

Secondly, the utility model utilizes sketch map to carry out detailed statement, and when the utility model instance was detailed, for the ease of explanation, sketch map did not amplify according to general ratio is local, should be with this as the qualification to the utility model.

Fig. 3 is the module diagram of two-way error amplifier described in the utility model one embodiment.As shown in Figure 3; Said two-way error amplifier comprises first error amplifier 21 and second error amplifier 22; Two inputs of said first error amplifier 21 are respectively as the positive input IN+ and the negative input IN-of said first error amplifier 21; Two inputs of said second error amplifier 22 are respectively as the positive input VN+ and the negative input VN-of said second error amplifier 22; The output of said first error amplifier 21 is connected with the output of said second error amplifier 22, and is connected in output port OUT; When the magnitude of voltage of the positive input VN+ of said second error amplifier 22 equals the magnitude of voltage of negative input IN-of first error amplifier 21 less than the magnitude of voltage of the positive input IN+ of the magnitude of voltage of the negative input VN-of second error amplifier 22 and said first error amplifier 21, the output current that the output current Iv of second error amplifier is constant when equaling second error amplifier and being operated in the saturation region; The magnitude of voltage of positive input IN+ of magnitude of voltage and first error amplifier 21 of negative input VN-that the magnitude of voltage of the positive input VN+ of second error amplifier 22 equals second error amplifier 22 is during less than the magnitude of voltage of the negative input IN-of first error amplifier 21, the output current that the output current Ic of first error amplifier is constant when equaling first error amplifier and being operated in the saturation region.

Two-way error amplifier as shown in Figure 3 is when being used to realize constant current, constant voltage function; Can be that first error amplifier 21 is that current error amplifier, second error amplifier 22 are voltage error amplifier, also can be that first error amplifier 21 is the current error amplifier for voltage error amplifier, second error amplifier 22.

Fig. 4 is a kind of circuit diagram among first embodiment of two-way error amplifier as shown in Figure 3; As shown in Figure 4; First error amplifier 21 comprises the first current source I22, and the difference input is to pipe M14, M24, active load M34, M44; The two ends of active load M34, M44 respectively and meet constant-current source-second current source I34 and the 3rd current source I44;, and link to each other the current mirror of active load M44 output through mirror image pipe M54, as the output port OUT of two-way error amplifier with the output of second error amplifier to second error amplifier 22.

As shown in Figure 4, be the current error amplifier with said first error amplifier 21, said second error amplifier 22 is an example for voltage error amplifier, wherein,

Said current error amplifier 21 comprises:

The one PMOS manages M14, and its grid is as the positive input IN+ of said current error amplifier;

The one NMOS manages M34, and its drain electrode is connected with its grid, and its drain electrode links to each other with the drain electrode of said PMOS pipe M14;

The 2nd PMOS manages M24, and its grid is as the negative input IN-of said current error amplifier, and its source electrode links to each other with the source electrode of said PMOS pipe M14;

The 2nd NMOS manages M44, and its drain electrode is connected with its grid and its drain electrode links to each other with the drain electrode of said the 2nd PMOS pipe M24, and the source electrode of said the 2nd NMOS pipe M44 links to each other with the source electrode of said NMOS pipe M34; In addition, after the source electrode of the source electrode of said NMOS pipe M34, said the 2nd NMOS pipe M44 and the source electrode of said the 3rd NMOS pipe M54 link to each other, common ground;

The 3rd NMOS manages M54, and its grid links to each other with the grid of said the 2nd NMOS pipe M44, and the drain electrode of said the 3rd NMOS pipe M54 is as the output of said voltage error amplifier, promptly as output port OUT.

The first current source I22, its two ends link to each other with the source electrode of said PMOS pipe M14 with external power source VDD;

The second current source I34, its two ends link to each other with the drain electrode of said NMOS pipe M34 and the source electrode of said NMOS pipe M34;

The 3rd current source I44, its two ends link to each other with the drain electrode of said the 2nd NMOS pipe M44 and the source electrode of said the 2nd NMOS pipe M44.

Said voltage error amplifier 22 comprises:

The 3rd PMOS manages M13, and its grid is as the negative input VN-of said voltage error amplifier;

The 4th NMOS manages M33, and its drain electrode is connected with its grid, and its drain electrode links to each other with the drain electrode of said the 3rd PMOS pipe M13;

The 4th PMOS manages M23; Its grid is as the positive input VN+ of said voltage error amplifier; Its source electrode links to each other with the source electrode of said the 3rd PMOS pipe M13, and the drain electrode of said the 4th PMOS pipe M23 is output port OUT as the output of said current error amplifier;

The 5th NMOS manages M43; Its grid links to each other with the grid of said the 4th NMOS pipe M33; The source electrode of said the 5th NMOS pipe M43 links to each other and ground connection with the source electrode of said the 4th NMOS pipe M33, and the drain electrode of said the 5th NMOS pipe M43 links to each other with the drain electrode of said the 4th PMOS pipe M23;

The 4th current source I21, its two ends link to each other with the source electrode of said the 3rd PMOS pipe M13 with external power source VDD.

Two-way error amplifier shown in Figure 4 has and only has two kinds of operating states:

First kind is constant voltage mode, and the positive input voltage VN+ of voltage error amplifier 22 equals the positive input voltage IN+ of its negative input voltage VN-, current error amplifier 21 less than its negative input voltage IN-;

Second kind is constant current mode, and the positive input voltage IN+ of current error amplifier 21 equals the positive input voltage VN+ of its negative input voltage IN-, voltage error amplifier 22 less than its negative input voltage VN-.

For current error amplifier 21; The current value of setting the said first current source I22 is I1; The current value of setting said second current source I34 and said the 3rd current source I44 is I2; Set current constant I1, I2 in the present embodiment, and satisfy I1＞2 * I2, said current constant is specifically to confirm numerical value according to the electric current of side circuit need of work.The breadth length ratio of said PMOS pipe M14 and said the 2nd PMOS pipe M24 is identical and mate; Said NMOS pipe M34 is identical with said the 2nd NMOS pipe M44 breadth length ratio; The breadth length ratio of said the 3rd NMOS pipe M54 is N times that said the 2nd NMOS manages the M44 breadth length ratio for

; Be wherein N be positive number, be generally natural number.For voltage error amplifier 22; The current value of setting said the 4th current source I21 is N * (I1/2-I2); Said the 3rd PMOS pipe M13 is identical with the breadth length ratio of said the 4th PMOS pipe M23, and said the 4th NMOS pipe M33 is identical with the breadth length ratio of said the 5th NMOS pipe M43.

When the two-way error amplifier is operated in constant voltage mode; The magnitude of voltage of the magnitude of voltage of the positive input VN+ of said voltage error amplifier and the negative input VN-of said voltage error amplifier equates; The drain-source current Ids13 of the drain-source current Ids23 of said the 4th PMOS pipe M23 and the 3rd PMOS pipe M13 equates; Ids23=Ids13=1/2 * I21=1/2 * N * (I1/2-I2); The drain-source current Ids33 of the drain-source current Ids43 of said the 5th NMOS pipe M43 and the 4th NMOS pipe M33 equates; Ids43=Ids33=1/2 * I21=1/2 * N * (I1/2-I2), therefore the drain-source current Ids43 of the drain-source current Ids23 of the 4th PMOS pipe M23 and the 5th NMOS pipe M43 equates that the output current of voltage error amplifier equals 0.The magnitude of voltage of the positive input IN+ of said current error amplifier is less than the magnitude of voltage of the negative input IN-of said current error amplifier; The drain-source current Ids23 of said the 3rd NMOS pipe M54 equals 0; Output current when this electric current just in time equals voltage error amplifier and is operated in the saturation region, the output current that the output current of promptly said current error amplifier is constant when equaling said voltage error amplifier and being operated in the saturation region.

Dual error amplifier when operating in constant current mode, the current error amplifier 21 of the positive input terminal IN + is equal to the voltage of the negative input voltage IN-, the current source I22 of the first current value I1, and the said first PMOS transistors M14 and M24 of the second PMOS transistor width to length ratio of the same, said first PMOS transistor M14 of the drain-source current Ids14 and second PMOS transistors M24, drain-source current Ids24 equal, that Ids14 = Ids24 = I1 / 2; Also, because of the second current source I34 and I44 said third current source current values are I2, so the first NMOS transistor M34 of the drain-source current Ids34 and second NMOS transistors M44 drain-source current Ids44 are: Ids34 = Ids14-I34 = I1/2-I2 = Ids24-I44 = Ids44, namely the first NMOS transistor M34 of the drain-source current Ids34 and second NMOS transistors M44 drain-source current equal; Also, because the second NMOS transistors M44 width to length ratio is

third NMOS transistor M54 width to length ratio

Therefore, the third NMOS transistor M54 of the drain-source current Ids54 = N × Ids44 = N × (I1/2-I2).The magnitude of voltage of the positive input VN+ of said voltage error amplifier 21 is less than the magnitude of voltage of negative input VN-; Be VN+＜VN-; The drain-source current Ids23=I21=N of said the 4th PMOS pipe M23 * (I1/2-I2); Dying has Ids23=Ids54=N * (I1/2-I2); Drain-source current Ids54 when said the 3rd NMOS pipe of the output current when this electric current just in time equals the current error amplifier and is operated in saturation region M54 is operated in the saturation region, the output current that therefore output current of said voltage error amplifier is constant when equaling said current error amplifier and being operated in the saturation region, again because the grid voltage of the 3rd NMOS pipe M54 confirm; Thereby make M54 can set correct direct current biasing point, and then make it be operated in normal saturation region.

Fig. 5 is as a kind of circuit diagram among second embodiment of two-way error amplifier shown in Figure 3; A kind of conversion figure for two-way error amplifier circuit sketch map as shown in Figure 4; The differential pair tube that is about to first error amplifier 21 by PMOS manage M14, M24 replaces with PNP pipe Q14 and the 2nd PNP pipe Q24; With the differential pair tube of second error amplifier 22 by PMOS manage M13, M23 replaces with the 3rd PNP pipe Q13 and the 4th PNP pipe Q23, can realize the function of two-way error amplifier equally.

Fig. 6 is the another kind of conversion figure of two-way error amplifier circuit sketch map as shown in Figure 4; First error amplifier 21 comprises active load M34 ', M44 '; Active load M34 ', M44 ' two ends are respectively and meet constant-current source I34 ', I44 ';, and link to each other the current mirror of active load M44 ' output through mirror image pipe M54 ', as the output port OUT of two-way error amplifier with the output of second error amplifier to second error amplifier 22.

Fig. 6 is as a kind of circuit diagram among the 3rd embodiment of two-way error amplifier shown in Figure 3; Being the another kind of conversion figure of two-way error amplifier circuit sketch map as shown in Figure 4, is the current error amplifier with said first error amplifier 21, and said second error amplifier 22 is an example for voltage error amplifier; As shown in Figure 6; On the basis of first embodiment, the said first a current source I22 ' end links to each other other end ground with the source electrode of said NMOS pipe M14 ';

Said current error amplifier 21 comprises:

The one NMOS manages M14 ', and its grid is as the positive input IN+ of said current error amplifier;

The one PMOS manages M34 ', and its drain electrode is connected with its grid, and its drain electrode links to each other with the drain electrode of said NMOS pipe M14 ';

The 2nd NMOS manages M24 ', and its grid is as the negative input IN-of said current error amplifier, and its source electrode links to each other with the source electrode of said NMOS pipe M14 ';

The 2nd PMOS manages M44 ', and its drain electrode is connected with its grid and its drain electrode links to each other with the drain electrode of said the 2nd NMOS pipe M24 ', and the source electrode of said the 2nd PMOS pipe M44 ' links to each other with the source electrode of said PMOS pipe M34 '; In addition, after the source electrode of the source electrode of said PMOS pipe M34 ', said the 2nd PMOS pipe M44 ' and the source electrode of said the 3rd PMOS pipe M54 ' link to each other, meet external power source VDD jointly;

The 3rd PMOS manages M54 ', and its grid links to each other with the grid of said the 2nd PMOS pipe M44 ', and the drain electrode of said the 3rd PMOS pipe M54 ' is as the output of said voltage error amplifier, promptly as output port OUT.

The first current source I22 ', its two ends link to each other with the source electrode of ground with said NMOS pipe M14 ';

The second current source I34 ', its two ends link to each other with the drain electrode of said PMOS pipe M34 ' and the source electrode of said PMOS pipe M34 ';

The 3rd current source I44 ', its two ends link to each other with the drain electrode of said the 2nd PMOS pipe M44 ' and the source electrode of said the 2nd PMOS pipe M44 '.

Said voltage error amplifier 22 comprises:

The 3rd NMOS manages M13 ', and its grid is as the negative input VN-of said voltage error amplifier;

The 4th PMOS manages M33 ', and its drain electrode is connected with its grid, and its drain electrode links to each other with the drain electrode of said the 3rd NMOS pipe M13 ';

The 4th NMOS manages M23 '; Its grid is as the positive input VN+ of said voltage error amplifier; Its source electrode links to each other with the source electrode of said the 3rd NMOS pipe M13 ', and the drain electrode of said the 4th NMOS pipe M23 ' is output port OUT as the output of said current error amplifier;

The 5th PMOS manages M43 '; Its grid links to each other with the grid of said the 4th PMOS pipe M33 '; The source electrode of said the 5th PMOS pipe M43 ' links to each other with the source electrode of said the 4th PMOS pipe M33 ' and meets external power source VDD, and the drain electrode of said the 5th PMOS pipe M43 ' links to each other with the drain electrode of said the 4th NMOS pipe M23 ';

The 4th current source I21 ', its two ends link to each other with the source electrode of ground with said the 3rd NMOS pipe M13 '.

Two-way error amplifier shown in Figure 6 has and only has two kinds of operating states:

For current error amplifier 21; The current value of setting the said first current source I22 is I1; The current value of setting said second current source I34 ' and said the 3rd current source I44 ' is I2; Set current constant I1, I2 in the present embodiment, and satisfy I1＞2 * I2, said current constant is specifically to confirm numerical value according to the electric current of side circuit need of work.The breadth length ratio of said NMOS pipe M14 ' and said the 2nd NMOS pipe M24 ' is identical and mate; Said PMOS pipe M34 ' is identical with said the 2nd PMOS pipe M44 ' breadth length ratio; The breadth length ratio of said the 3rd PMOS pipe M54 ' is N times that said the 2nd NMOS manages M44 ' breadth length ratio for ; Be

wherein N be positive number, be generally natural number.For voltage error amplifier 22; The current value of setting said the 4th current source I21 is N * (I1/2-I2); Said the 3rd NMOS pipe M13 ' is identical with the breadth length ratio of said the 4th NMOS pipe M23 ', and said the 4th PMOS pipe M33 ' is identical with the breadth length ratio of said the 5th PMOS pipe M43 '.

When the two-way error amplifier is operated in constant voltage mode; The magnitude of voltage of the magnitude of voltage of the positive input VN+ of said voltage error amplifier and the negative input VN-of said voltage error amplifier equates; The drain-source current Ids13 ' of the drain-source current Ids23 ' of said the 4th NMOS pipe M23 ' and the 3rd NMOS pipe M13 ' equates; Ids23 '=Ids13 '=1/2 * I21=1/2 * N * (I1/2-I2); The drain-source current Ids33 ' of the drain-source current Ids43 ' of said the 5th PMOS pipe M43 ' and the 4th PMOS pipe M33 ' equates; Ids43 '=Ids33 '=1/2 * I21=1/2 * N * (I1/2-I2), therefore the drain-source current Ids43 ' of the drain-source current Ids23 ' of the 4th NMOS pipe M23 ' and the 5th PMOS pipe M43 ' equates that the output current of voltage error amplifier equals 0.The magnitude of voltage of the positive input IN+ of said current error amplifier is less than the magnitude of voltage of the negative input IN-of said current error amplifier; The drain-source current Ids23 ' of said the 3rd PMOS pipe M54 ' equals 0; Output current when this electric current just in time equals voltage error amplifier and is operated in the saturation region, the output current that the output current of promptly said current error amplifier is constant when equaling said voltage error amplifier and being operated in the saturation region.

Dual error amplifier when operating in constant current mode, the current error amplifier 21 of the positive input terminal IN + is equal to the voltage of the negative input voltage IN-, the first current source I22 'of the current value I1, and said first NMOS transistor M14 'and the second NMOS transistors M24' width to length ratio of the same, said first NMOS transistor M14 'drain-source current Ids14' and second NMOS transistors M24 'drain-source current Ids24 'are equal, that Ids14' = Ids24 '= I1 / 2; but since the second current source I34' and said third current source I44 'of the current values are I2, the first PMOS transistor M34' drain-source Current Ids34 'and second PMOS transistors M44' drain-source current Ids44 'are: Ids34' = Ids14'-I34 '= I1/2-I2 = Ids24'-I44' = Ids44 ', ie, the first PMOS transistor M34' of drain-source current Ids34 'and second PMOS transistors M44' drain-source current Ids44 'equal; Also, because the second NMOS transistors M44' width to length ratio is

third NMOS transistor M54 'width to length ratio

it is the third PMOS transistor M54 ' The drain-source current Ids54 '= N × Ids44' = N × (I1/2-I2).The magnitude of voltage of the positive input VN+ of said voltage error amplifier 21 is less than the magnitude of voltage of negative input VN-; Be VN+＜VN-; Drain-source current Ids23 '=I21 '=N of said the 4th NMOS pipe M23 ' * (I1/2-I2); Dying has Ids23 '=Ids54 '=N * (I1/2-I2); Drain-source current Ids54 ' when said the 3rd PMOS pipe of the output current when this electric current just in time equals the current error amplifier and is operated in saturation region M54 ' is operated in the saturation region, the output current that therefore output current of said voltage error amplifier is constant when equaling said current error amplifier and being operated in the saturation region, again because the grid voltage of the 3rd PMOS pipe M54 ' confirm; Thereby make M54 ' can set correct direct current biasing point, and then make it be operated in normal saturation region.

Therefore, through adjustment, like Fig. 4, Fig. 5, shown in Figure 6 to two-way error amplifier structure; In said current error amplifier, increase by two current sources and set each current value in the two-way error amplifier; Setting the correct direct current biasing point of current error amplifier under the constant current mode, thereby the current error amplifier when making constant current mode is operated in normal saturation region, when being applied to constant voltage, constant current; The output port OUT of two-way error amplifier can provide stable operating voltage always.And the said two-way error amplifier of the utility model can be widely used in having in the electric power management circuit of constant voltage and constant current functional requirement, like constant voltage/constant current type DC-DC transducer etc.

Though the utility model discloses as above with preferred embodiment; Right its is not in order to limit the utility model; Has common knowledge the knowledgeable in the technical field under any; In spirit that does not break away from the utility model and scope, when can doing a little change and retouching, so the protection range of the utility model is as the criterion when looking claims person of defining.

Claims

1. a two-way error amplifier comprises first error amplifier and second error amplifier, and the output of said first error amplifier is connected with the output of said second error amplifier, and as the output port of two-way error amplifier, it is characterized in that,

Said first error amplifier comprises:

Said second error amplifier comprises:

2. two-way error amplifier as claimed in claim 1 is characterized in that,

Said first current source links to each other with external power source;

Said mirror image pipe comprises the 3rd NMOS pipe, and the grid of said the 3rd NMOS pipe links to each other with the grid of said the 2nd NMOS pipe and drains as the output of said first error amplifier;

3. two-way error amplifier as claimed in claim 2 is characterized in that, the said first current source current value is I1; The current value of said second current source and said the 3rd current source is I2; And satisfy I1＞2 * I2, said PMOS pipe is identical with the breadth length ratio of said the 2nd PMOS pipe, and said NMOS pipe is identical with said the 2nd NMOS pipe breadth length ratio; The breadth length ratio of said the 3rd NMOS pipe is N a times of said the 2nd NMOS pipe breadth length ratio, and wherein N is a positive number.

4. two-way error amplifier as claimed in claim 3; It is characterized in that; When the magnitude of voltage of the positive input of said first error amplifier equals the magnitude of voltage of negative input of said first error amplifier; The drain-source current of said PMOS pipe is I1/2 with the drain-source current of said the 2nd PMOS pipe, and the drain-source current of said NMOS pipe is I2 with the drain-source current that said the 2nd NMOS manages, and the drain-source current that said the 3rd NMOS manages is N * (I1/2-I2).

5. two-way error amplifier as claimed in claim 1 is characterized in that,

Said first current source links to each other with ground;

6. two-way error amplifier as claimed in claim 1 is characterized in that,

Said first current source links to each other with external power source;

7. two-way error amplifier as claimed in claim 1 is characterized in that,

The 4th current source links to each other with external power source;

8. two-way error amplifier as claimed in claim 7 is characterized in that, the said first current source current value is I1; The current value of said second current source and said the 3rd current source is I2; And satisfy I1＞2 * I2, the current value of said the 4th current source is that N * (I1/2-I2), said the 3rd PMOS pipe is identical with the breadth length ratio of said the 4th PMOS pipe; Said the 4th NMOS pipe is identical with the breadth length ratio of said the 5th NMOS pipe, and wherein N is a positive number.

9. two-way error amplifier as claimed in claim 8; It is characterized in that; The magnitude of voltage of the positive input of said second error amplifier is during less than the magnitude of voltage of the negative input of said second error amplifier, and the drain-source current value of said the 4th PMOS pipe is N * (I1/2-I2).

10. two-way error amplifier as claimed in claim 1 is characterized in that,

The 4th current source links to each other with external power source;

The input of second difference comprises the 3rd PNP pipe and the 4th PNP pipe to pipe; The base stage of said the 3rd PNP pipe is as the negative input of said second error amplifier; The base stage of said the 4th PNP pipe as the emitter of the positive input of said second error amplifier, said the 3rd PNP pipe link to each other with the 4th current source jointly with the emitter of said the 4th PNP pipe, the collector electrode of said the 4th PNP pipe is as the output of said second error amplifier, the emitter that said the 3rd PNP manages links to each other with said the 4th current source;

11. like any described two-way error amplifier in the claim 1 to 10, it is characterized in that said first error amplifier is the current error amplifier, said second error amplifier is a voltage error amplifier.

12. like any described two-way error amplifier in the claim 1 to 10, it is characterized in that said first error amplifier is a voltage error amplifier, said second error amplifier is the current error amplifier.