CN202183911U - Novel printed circuit board superposed hole structure - Google Patents
Novel printed circuit board superposed hole structure Download PDFInfo
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- CN202183911U CN202183911U CN 201120294991 CN201120294991U CN202183911U CN 202183911 U CN202183911 U CN 202183911U CN 201120294991 CN201120294991 CN 201120294991 CN 201120294991 U CN201120294991 U CN 201120294991U CN 202183911 U CN202183911 U CN 202183911U
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- hole
- conductive layer
- electroplating hole
- conducting layer
- electroplating
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Abstract
Provided is a novel printed circuit board superposed hole structure, characterized by comprising sequentially from top to bottom: a first conducting layer, a first prepreg, a second conducting layer, an insulating layer, a third conducting layer, a second prepreg, and a fourth conducting layer, wherein an external electroplating hole is arranged between the second conducting layer and the third conducting layer; the upper end of the external electroplating hole is connected with the second conducting layer while the lower end of the external electroplate hole passes through the insulating layer to connect the third conducting layer; an internal electroplating hole is arranged between the first conducting layer and the fourth conducting layer; the internal electroplating hole is located inside the external electroplating hole; the upper end of the internal electroplating hole is connected with a first conducting layer while the lower end of the internal electroplating hole is connected with the fourth conducting layer; the second conducting layer is communicated to the internal electroplating hole; and the third conducting layer is communicated to the internal electroplating hole. After the external electroplating hole adopts resin to fill the hole, the external layer employs a secondary boring technology to form superposed through hole of more than two stage, thereby being capable of reducing 20% of the wiring area of the external layer, without increasing the cost of plate manufacturing and with the results of every reliability test meeting the standard of IPC.
Description
Technical field
The utility model relates to a kind of printed circuit board, more specifically to the folded pore structure of a kind of novel printed circuit board.
Background technology
Be accompanied by modern electronic product to " light, thin, little, multifunction " development, electronic device highly integrated; Interconnection technique is installed (CMT) technical development from through hole plug-in unit (THT) technology to mounted on surface (SMT) technology and chip, has quickened the exploitation of high density (HDI) printed circuit technique.
High density printed board processing had both comprised conventional single sided board/two-sided/multi-layer sheet process technology, had also comprised process technology, fine-line (0.02-0.10mm) manufacturing technology, electrical performance indexes and the reliability detection technique of buried via hole (the BTH)/blind hole (BVH) of small (less than 0.1mm).The application technology of above-mentioned many new technologies, new material, need promote mutual understanding, relearn, put into practice, innovate, advance the PCB development of technology the high-density printed circuit technology.
Electronic product requires " light, thin, little, multifunction ", and this has advanced the expansion of highly integrated I/O (input and output) number of IC device.And limited surface wiring space is restricted, and has then advanced conventional printed board processing to develop to two-sided or multi-layer sheet direction from single face.But the number of plies increases, thickness of slab increases, weight increases, through hole (TH) increases, and not only brings difficulty to wires design, a series of problems such as cause the processing cost of printed board sharply to rise simultaneously, the cycle is long, product qualified rate is low.Therefore, thinking is warded off in PCB routing design beginning in addition, adopts to bury/interconnection of blind hole realization wiring layer net.So both satisfied the wires design requirement, reduced surperficial through hole quantity again, made that wiring layer reduced, thickness of slab reduces, interlinking reliability improves, cost reduces high density printed board that Here it is.
To the different designs requirement, select different materials, different process technology for use, to adapt to multi-layered high-density printed board processing.This has broken the work flow of conventional printed board; The new approaches of printed board design and processing have been started; Brought new technological development and product development opportunity for printed board enterprise; Therefore this time new process technology revolution has attracted the concern of printed board industry, and high density printed board processing will become mainstream technology.
Introduce the relevant criterion of high density printed board below:
1, the key technical indexes:
Live width (L)/spacing (S): 0.02-0.10mm
Through-hole diameter (VIA): 0.05-0.10mm
Pad diameter (PAD): 0.10-0.30mm
Thickness of insulating layer: 0.03-0.10mm
The wiring number of plies: 6-20 layer
2, press textural classification: amount to 6 kinds
1 type: 1 [C] 0 or 1 [C] 1: through hole is only arranged from the surface to another surface
2 types: 1 [C] 0 or 1 [C] 1: central layer and superficial layer bury/blind hole
3 types: 2 [C] 0: bury/the blind hole through hole on central layer and surface
4 types: 1 [P] 0: do not have electric perforation
5 types: 2 [X] 2: no central layer, interlayer is with burying/the blind hole interconnection
6 types:: laminated construction (Alternal construction)
3, relevant criterion:
Single core of design standard: IPC-2225 and multicore sheet encapsulation printed board design standard; IPC-2226 high density interconnect substrate design standard.
Material standard: IPC-4104 high density structures and micro through hole material property and evaluation.
Single core of finished product standard: IPC-6015 and multicore sheet encapsulation printed board performance specification; IPC-6016 high density printed board performance requirement standard.
4, through-hole structure:
(1) VOI (VIA on IVH) structure
Go up to lay through hole (VIA) in interlayer via (IVH), promptly on the lead-out wire of IVH, lay VIA, through hole (Sprial VIA) structure twist, or directly on IVA, lay through hole.
(2) VOV (VIA on VIA) structure
Directly on VIA, lay VIA, present the stack shape, VOV lays mode can reduce the number of plies that connects up than VOI structure, can carry out more high-density wiring design.
(3)VIV(VIA?in?VIA)
Newly-designed through-hole structure is defined as hole mesopore VIV (VIA in VIA) structure at present, and develops it and manufacture flow process.This design promptly is on the position of former internal layer buried via hole, to increase via hole, still can accomplish the structural design of VOI and VOV on this basis.It is manufactured process need and solves boring aligning accuracy, aperture compensation and electroplate technological difficulties such as compensation control, resin filling perforation, just can be achieved.
Summary of the invention
The utility model technical problem to be solved provides the folded pore structure of a kind of novel printed circuit board, and the folded pore structure of this printed circuit board can effectively reduce outer field wiring area.The technical scheme that adopts is following:
A kind of novel printed circuit board is folded pore structure, it is characterized in that: comprise first conductive layer, first prepreg, second conductive layer, insulating barrier, the 3rd conductive layer, second prepreg, the 4th conductive layer from top to bottom successively; Be provided with outer electroplating hole between said second conductive layer and the 3rd conductive layer, outer electroplating hole upper end connects second conductive layer, and outer electroplating hole lower end is passed insulating barrier and connected the 3rd conductive layer; Be provided with interior electroplating hole between said first conductive layer and the 4th conductive layer; Electroplating hole is positioned at outer electroplating hole in said; Interior electroplating hole upper end connects first conductive layer; Interior electroplating hole lower end connects the 4th conductive layer, and said second conductive layer is communicated with interior electroplating hole, and said the 3rd conductive layer is communicated with interior electroplating hole.
A kind of more excellent scheme; Also be provided with resin bed between said outer electroplating hole madial wall and the interior electroplating hole lateral wall; The resin bed upper end is the first discoid plating sheet; The resin bed lower end is the second discoid plating sheet, and second conductive layer is communicated with interior electroplating hole through the first discoid plating sheet, and the 3rd conductive layer is communicated with interior electroplating hole through the second discoid plating sheet.It is circular that resin bed is, and the space between outer electroplating hole madial wall and the interior electroplating hole lateral wall is filled up.
The utility model beneficial effect against existing technologies is; Because after outer electroplating hole adopts the resin filling perforation; Use secondary drilling technology to form the folded through hole of string more than the second order at skin; It is about 20% to reduce outer wiring area, and plate is made processing cost and do not had increase, and each item reliability testing all meets the IPC standard.
Description of drawings
Accompanying drawing is the structural representation of the utility model preferred embodiment.
Embodiment
Shown in accompanying drawing; A kind of novel printed circuit board in this preferred embodiment is folded pore structure, comprises first conductive layer 1, first prepreg 2, second conductive layer 3, insulating barrier 4, the 3rd conductive layer 5, second prepreg 6, the 4th conductive layer 7 from top to bottom successively; Be provided with outer electroplating hole 9 between said second conductive layer 3 and the 3rd conductive layer 5, outer electroplating hole 9 upper ends connect second conductive layer 3, and outer electroplating hole 9 lower ends are passed insulating barrier 4 and connected the 3rd conductive layer 5; Electroplating hole 11 in being provided with between said first conductive layer 1 and the 4th conductive layer 7, said interior electroplating hole 11 is positioned at outer electroplating hole 9, and interior electroplating hole 11 upper ends connect first conductive layer 1, and interior electroplating hole 11 lower ends connect the 4th conductive layer 7.
Also be provided with resin bed 8 between said outer electroplating hole 9 madial walls and interior electroplating hole 11 lateral walls; Resin bed 8 upper ends are the first discoid plating sheet 12; Resin bed 8 lower ends are the second discoid plating sheet 10; Second conductive layer is communicated with interior electroplating hole 11 through the first discoid plating sheet 12, and the 3rd conductive layer 5 is communicated with interior electroplating hole 11 through the second discoid plating sheet 10.Said resin bed 8 is circular, and the space between outer electroplating hole 9 madial walls and interior electroplating hole 11 lateral walls is filled up.
Introduce the procedure of processing of the folded pore structure of printed circuit board below:
1, second conductive layer 3, insulating barrier 4, the 3rd conductive layer 5 are processed central layer;
2, central layer is holed, form outer hole;
3, externally electroplate in the hole, processes outer electroplating hole 9;
4, external then electroplating hole 9 carries out the resin filling perforation, and outer electroplating hole 9 usefulness resins are filled up, and forms resin bed 8, again resin bed 8 is carried out surperficial polish-brush, and the resin that will be positioned at outer electroplating hole 9 apertures polishes;
5, resin bed 8 top and bottom are carried out electroplating surface respectively, form the first discoid plating sheet 12 in resin bed 8 upper ends, form the second discoid plating sheet 10 in resin bed 8 lower ends;
6, first conductive layer 1, first prepreg 2, central layer, second prepreg 6, the 4th conductive layer 7 are carried out pressing, process four laminates;
7, pressing is good four-sheet structure is holed, and forms endoporus;
Endoporus is electroplated electroplating hole 11 in forming.
Owing to adopted novel VIV technology, in the above-mentioned steps 4, after externally electroplating hole 9 adopts the resin filling perforation, used secondary drilling technology to form the folded through hole VIV of the above string of second order outside in the electroplating hole 9.Through analyzing, it is about 20% to adopt new VIV technology can reduce outer wiring area, and plate is made processing cost and do not had increase.And reliability conclusion aspect, the VIV test plate that adopts above-mentioned steps to process is not all found the plate bursting layering in thermal shock (288 ℃ of * 10S*6Cycles) test, and string hole proof voltage and anti-CAF are all through test.All less than 10%, the reliability testing of VIV test plate each item all meets the IPC standard through (65 ℃ of 15Min/+125 ℃ of 15Min) 500 loop test metapore resistance change rates.
The preferred embodiment that the above is merely the utility model is not the practical range that is used for limiting the utility model; Be all equivalents of being done according to the claim scope of the utility model, be the utility model claim scope and cover.
Claims (2)
1. the folded pore structure of novel printed circuit board is characterized in that: comprise first conductive layer, first prepreg, second conductive layer, insulating barrier, the 3rd conductive layer, second prepreg, the 4th conductive layer from top to bottom successively; Be provided with outer electroplating hole between said second conductive layer and the 3rd conductive layer, outer electroplating hole upper end connects second conductive layer, and outer electroplating hole lower end is passed insulating barrier and connected the 3rd conductive layer; Be provided with interior electroplating hole between said first conductive layer and the 4th conductive layer; Electroplating hole is positioned at outer electroplating hole in said; Interior electroplating hole upper end connects first conductive layer; Interior electroplating hole lower end connects the 4th conductive layer, and said second conductive layer is communicated with interior electroplating hole, and said the 3rd conductive layer is communicated with interior electroplating hole.
2. novel printed circuit board as claimed in claim 1 is folded pore structure; It is characterized in that: also be provided with resin bed between said outer electroplating hole madial wall and the interior electroplating hole lateral wall; The resin bed upper end is the first discoid plating sheet; The resin bed lower end is the second discoid plating sheet, and second conductive layer is communicated with interior electroplating hole through the first discoid plating sheet, and the 3rd conductive layer is communicated with interior electroplating hole through the second discoid plating sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120294991 CN202183911U (en) | 2011-08-15 | 2011-08-15 | Novel printed circuit board superposed hole structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120294991 CN202183911U (en) | 2011-08-15 | 2011-08-15 | Novel printed circuit board superposed hole structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202183911U true CN202183911U (en) | 2012-04-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120294991 Expired - Fee Related CN202183911U (en) | 2011-08-15 | 2011-08-15 | Novel printed circuit board superposed hole structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202183911U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104640379A (en) * | 2013-11-08 | 2015-05-20 | 珠海方正科技多层电路板有限公司 | Printed circuit board and manufacturing method thereof |
| CN113301716A (en) * | 2021-06-01 | 2021-08-24 | 深圳市利迪亚电子有限公司 | Multilayer PCB with special-shaped holes and processing method |
-
2011
- 2011-08-15 CN CN 201120294991 patent/CN202183911U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104640379A (en) * | 2013-11-08 | 2015-05-20 | 珠海方正科技多层电路板有限公司 | Printed circuit board and manufacturing method thereof |
| CN113301716A (en) * | 2021-06-01 | 2021-08-24 | 深圳市利迪亚电子有限公司 | Multilayer PCB with special-shaped holes and processing method |
| CN113301716B (en) * | 2021-06-01 | 2022-03-29 | 深圳市利迪亚电子有限公司 | Multilayer PCB with special-shaped holes and processing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120404 Termination date: 20120815 |