CN202178922U - Stacked hole structure of printed-circuit board - Google Patents
Stacked hole structure of printed-circuit board Download PDFInfo
- Publication number
- CN202178922U CN202178922U CN 201120294990 CN201120294990U CN202178922U CN 202178922 U CN202178922 U CN 202178922U CN 201120294990 CN201120294990 CN 201120294990 CN 201120294990 U CN201120294990 U CN 201120294990U CN 202178922 U CN202178922 U CN 202178922U
- Authority
- CN
- China
- Prior art keywords
- conductive layer
- hole
- electroplating hole
- electroplating
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009713 electroplating Methods 0.000 claims abstract description 57
- 239000011347 resin Substances 0.000 claims abstract description 21
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 239000011148 porous material Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 13
- 238000012360 testing method Methods 0.000 abstract description 8
- 238000005553 drilling Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000011799 hole material Substances 0.000 description 61
- 239000010410 layer Substances 0.000 description 45
- 238000005516 engineering process Methods 0.000 description 18
- 238000013461 design Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 9
- 238000011161 development Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The utility model discloses a stacked hole structure of a printed-circuit board. The stacked hole structure sequentially comprises a first conductive layer, a first prepreg, a second conductive layer, an insulating layer, a third conductive layer, a second prepreg and a fourth conductive layer from up to bottom, wherein an outer electroplating hole is arranged between the second conductive layer and the third conductive layer; the second conductive layer is connected to the upper end of the outer electroplating hole; the lower end of the outer electroplating hole is connected to the third conductive layer after penetrating through the insulating layer; an inner electroplating hole is arranged between the first conductive layer and the fourth conductive layer and is located in the outer electroplating hole; the upper end of the inner electroplating hole is connected to the first conductive layer; the lower end of the inner electroplating hole is connected to the fourth conductive layer; and the third conductive layer is communicated with the inner electroplating hole. Compared with the prior art, the stacked hole structure has the beneficial effect as a two-order overlapping through hole is formed by using a secondary drilling process at the outer layer after the outer electroplating hole is filled with resin, the outer-layer wiring area can be reduced by about 20% without increasing the manufacturing cost of plates, and various reliability tests accord with the IPC (Institute of Printed Circuit) standards.
Description
Technical field
The utility model relates to a kind of printed circuit board, more specifically to the folded pore structure of a kind of printed circuit board.
Background technology
Be accompanied by modern electronic product to " light, thin, little, multifunction " development, electronic device highly integrated; Interconnection technique is installed (CMT) technical development from through hole plug-in unit (THT) technology to mounted on surface (SMT) technology and chip, has quickened the exploitation of high density (HDI) printed circuit technique.
High density printed board processing had both comprised conventional single sided board/two-sided/multi-layer sheet process technology, had also comprised process technology, fine-line (0.02-0.10mm) manufacturing technology, electrical performance indexes and the reliability detection technique of buried via hole (the BTH)/blind hole (BVH) of small (less than 0.1mm).The application technology of above-mentioned many new technologies, new material, need promote mutual understanding, relearn, put into practice, innovate, advance the PCB development of technology the high-density printed circuit technology.
Electronic product requires " light, thin, little, multifunction ", and this has advanced the expansion of highly integrated I/O (input and output) number of IC device.And limited surface wiring space is restricted, and has then advanced conventional printed board processing to develop to two-sided or multi-layer sheet direction from single face.But the number of plies increases, thickness of slab increases, weight increases, through hole (TH) increases, and not only brings difficulty to wires design, a series of problems such as cause the processing cost of printed board sharply to rise simultaneously, the cycle is long, product qualified rate is low.Therefore, thinking is warded off in PCB routing design beginning in addition, adopts to bury/interconnection of blind hole realization wiring layer net.So both satisfied the wires design requirement, reduced surperficial through hole quantity again, made that wiring layer reduced, thickness of slab reduces, interlinking reliability improves, cost reduces high density printed board that Here it is.
To the different designs requirement, select different materials, different process technology for use, to adapt to multi-layered high-density printed board processing.This has broken the work flow of conventional printed board; The new approaches of printed board design and processing have been started; Brought new technological development and product development opportunity for printed board enterprise; Therefore this time new process technology revolution has attracted the concern of printed board industry, and high density printed board processing will become mainstream technology.
Introduce the relevant criterion of high density printed board below:
1, the key technical indexes:
Live width (L)/spacing (S): 0.02-0.10mm
Through-hole diameter (VIA): 0.05-0.10mm
Pad diameter (PAD): 0.10-0.30mm
Thickness of insulating layer: 0.03-0.10mm
The wiring number of plies: 6-20 layer
2, press textural classification: amount to 6 kinds
1 type: 1 [C] 0 or 1 [C] 1: through hole is only arranged from the surface to another surface
2 types: 1 [C] 0 or 1 [C] 1: central layer and superficial layer bury/blind hole
3 types: 2 [C] 0: bury/the blind hole through hole on central layer and surface
4 types: 1 [P] 0: do not have electric perforation
5 types: 2 [X] 2: no central layer, interlayer is with burying/the blind hole interconnection
6 types:: laminated construction (Alternal construction)
3, relevant criterion:
Single core of design standard: IPC-2225 and multicore sheet encapsulation printed board design standard; IPC-2226 high density interconnect substrate design standard.
Material standard: IPC-4104 high density structures and micro through hole material property and evaluation.
Single core of finished product standard: IPC-6015 and multicore sheet encapsulation printed board performance specification; IPC-6016 high density printed board performance requirement standard.
4, through-hole structure:
(1) VOI (VIA on IVH) structure
Go up to lay through hole (VIA) in interlayer via (IVH), promptly on the lead-out wire of IVH, lay VIA, through hole (Sprial VIA) structure twist, or directly on IVA, lay through hole.
(2) VOV (VIA on VIA) structure
Directly on VIA, lay VIA, present the stack shape, VOV lays mode can reduce the number of plies that connects up than VOI structure, can carry out more high-density wiring design.
(3)VIV(VIA?in?VIA)
Newly-designed through-hole structure is defined as hole mesopore VIV (VIA in VIA) structure at present, and develops it and manufacture flow process.This design promptly is on the position of former internal layer buried via hole, to increase via hole, still can accomplish the structural design of VOI and VOV on this basis.It is manufactured process need and solves boring aligning accuracy, aperture compensation and electroplate technological difficulties such as compensation control, resin filling perforation, just can be achieved.
Summary of the invention
The utility model technical problem to be solved provides the folded pore structure of a kind of printed circuit board, and the folded pore structure of this printed circuit board can effectively reduce outer field wiring area.The technical scheme that adopts is following:
A kind of printed circuit board is folded pore structure, it is characterized in that: comprise first conductive layer, first prepreg, second conductive layer, insulating barrier, the 3rd conductive layer, second prepreg, the 4th conductive layer from top to bottom successively; Be provided with outer electroplating hole between said second conductive layer and the 3rd conductive layer, outer electroplating hole upper end connects second conductive layer, and outer electroplating hole lower end is passed insulating barrier and connected the 3rd conductive layer; Be provided with interior electroplating hole between said first conductive layer and the 4th conductive layer, said interior electroplating hole is positioned at outer electroplating hole, and interior electroplating hole upper end connects first conductive layer, and interior electroplating hole lower end connects the 4th conductive layer, and said the 3rd conductive layer is communicated with interior electroplating hole.
Also be provided with resin bed between said outer electroplating hole madial wall and the interior electroplating hole lateral wall, the resin bed upper end connects first prepreg, and the resin bed lower end is discoid plating sheet, and the 3rd conductive layer is communicated with interior electroplating hole through discoid plating sheet.Said resin bed is circular, and the space between outer electroplating hole madial wall and the interior electroplating hole lateral wall is filled up.
The utility model beneficial effect against existing technologies is; Because after outer electroplating hole adopts the resin filling perforation; Use secondary drilling technology to form the folded through hole of string more than the second order at skin; It is about 20% to reduce outer wiring area, and plate is made processing cost and do not had increase, and each item reliability testing all meets the IPC standard.
Description of drawings
Accompanying drawing is the structural representation of the utility model preferred embodiment.
Embodiment
Shown in accompanying drawing, a kind of printed circuit board in this preferred embodiment is folded pore structure, comprises first conductive layer 1, first prepreg 2, second conductive layer 3, insulating barrier 4, the 3rd conductive layer 5, second prepreg 6, the 4th conductive layer 7 from top to bottom successively; Be provided with outer electroplating hole 9 between said second conductive layer 3 and the 3rd conductive layer 5, outer electroplating hole 9 upper ends connect second conductive layer 3, and outer electroplating hole 9 lower ends are passed insulating barrier 4 and connected the 3rd conductive layer 5; Electroplating hole 11 in being provided with between said first conductive layer 1 and the 4th conductive layer 7, said interior electroplating hole 11 is positioned at outer electroplating hole 9, and interior electroplating hole 11 upper ends connect first conductive layer 1, and interior electroplating hole 11 lower ends connect the 4th conductive layer 7.
Also be provided with resin bed 8 between said outer electroplating hole 9 madial walls and interior electroplating hole 11 lateral walls, resin bed 8 upper ends connect first prepreg 2, and resin bed 8 lower ends are that discoid plating sheet 10, the three conductive layers 5 are communicated with interior electroplating hole 11 through discoid plating sheet 10.Resin bed 8 is circular, and the space between outer electroplating hole 9 madial walls and interior electroplating hole 11 lateral walls is filled up.
Introduce the procedure of processing of the folded pore structure of printed circuit board below:
1, second conductive layer 3, insulating barrier 4, the 3rd conductive layer 5 are processed central layer;
2, central layer is holed, form outer hole;
3, externally electroplate in the hole, processes outer electroplating hole 9;
4, external then electroplating hole 9 carries out the resin filling perforation, and outer electroplating hole 9 usefulness resins are filled up, and forms resin bed 8, again resin bed 8 is carried out surperficial polish-brush, and the resin that will be positioned at outer electroplating hole 9 apertures polishes;
5, electroplating surface is carried out in resin bed 8 lower ends, form discoid plating sheet 10;
6, first conductive layer 1, first prepreg 2, central layer, second prepreg 6, the 4th conductive layer 7 are carried out pressing, process four laminates;
7, pressing is good four-sheet structure is holed, and forms endoporus;
8, endoporus is electroplated electroplating hole 11 in forming.
Owing to adopted novel VIV technology, in the above-mentioned steps 4, after externally electroplating hole 9 adopts the resin filling perforation, used secondary drilling technology to form the folded through hole VIV of the above string of second order outside in the electroplating hole 9.Through analyzing, it is about 20% to adopt new VIV technology can reduce outer wiring area, and plate is made processing cost and do not had increase.And reliability conclusion aspect, the VIV test plate that adopts above-mentioned steps to process is not all found the plate bursting layering in thermal shock (288 ℃ of * 10S*6Cycles) test, and string hole proof voltage and anti-CAF are all through test.All less than 10%, the reliability testing of VIV test plate each item all meets the IPC standard through (65 ℃ of 15Min/+125 ℃ of 15Min) 500 loop test metapore resistance change rates.
The preferred embodiment that the above is merely the utility model is not the practical range that is used for limiting the utility model; Be all equivalents of being done according to the claim scope of the utility model, be the utility model claim scope and cover.
Claims (2)
1. the folded pore structure of printed circuit board is characterized in that: comprise first conductive layer, first prepreg, second conductive layer, insulating barrier, the 3rd conductive layer, second prepreg, the 4th conductive layer from top to bottom successively; Be provided with outer electroplating hole between said second conductive layer and the 3rd conductive layer, outer electroplating hole upper end connects second conductive layer, and outer electroplating hole lower end is passed insulating barrier and connected the 3rd conductive layer; Be provided with interior electroplating hole between said first conductive layer and the 4th conductive layer, said interior electroplating hole is positioned at outer electroplating hole, and interior electroplating hole upper end connects first conductive layer, and interior electroplating hole lower end connects the 4th conductive layer, and said the 3rd conductive layer is communicated with interior electroplating hole.
2. printed circuit board as claimed in claim 1 is folded pore structure; It is characterized in that: also be provided with resin bed between said outer electroplating hole madial wall and the interior electroplating hole lateral wall; The resin bed upper end connects first prepreg; The resin bed lower end is discoid plating sheet, and the 3rd conductive layer is communicated with interior electroplating hole through discoid plating sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120294990 CN202178922U (en) | 2011-08-15 | 2011-08-15 | Stacked hole structure of printed-circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120294990 CN202178922U (en) | 2011-08-15 | 2011-08-15 | Stacked hole structure of printed-circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202178922U true CN202178922U (en) | 2012-03-28 |
Family
ID=45868783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120294990 Expired - Fee Related CN202178922U (en) | 2011-08-15 | 2011-08-15 | Stacked hole structure of printed-circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202178922U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103857207A (en) * | 2012-11-30 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
| CN104023484A (en) * | 2014-05-09 | 2014-09-03 | 东莞市五株电子科技有限公司 | A method of manufacturing a printed circuit board stacked through-hole structure |
| CN104640379A (en) * | 2013-11-08 | 2015-05-20 | 珠海方正科技多层电路板有限公司 | Printed circuit board and manufacturing method thereof |
| WO2020085719A1 (en) * | 2018-10-26 | 2020-04-30 | 삼성전자 주식회사 | Substrate connection member comprising substrate having opening part, which encompasses region in which through wire is formed, and conductive member formed on side surface of opening part, and electronic device comprising same |
-
2011
- 2011-08-15 CN CN 201120294990 patent/CN202178922U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103857207A (en) * | 2012-11-30 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
| CN103857207B (en) * | 2012-11-30 | 2017-03-01 | 碁鼎科技秦皇岛有限公司 | Circuit board and preparation method thereof |
| CN104640379A (en) * | 2013-11-08 | 2015-05-20 | 珠海方正科技多层电路板有限公司 | Printed circuit board and manufacturing method thereof |
| CN104023484A (en) * | 2014-05-09 | 2014-09-03 | 东莞市五株电子科技有限公司 | A method of manufacturing a printed circuit board stacked through-hole structure |
| WO2020085719A1 (en) * | 2018-10-26 | 2020-04-30 | 삼성전자 주식회사 | Substrate connection member comprising substrate having opening part, which encompasses region in which through wire is formed, and conductive member formed on side surface of opening part, and electronic device comprising same |
| KR20200047050A (en) * | 2018-10-26 | 2020-05-07 | 삼성전자주식회사 | Electronic device and substrate connecting member comprising opening surrounding region where through wiring is formed and substrate having conductive member formed on the side of the opening |
| US11690179B2 (en) | 2018-10-26 | 2023-06-27 | Samsung Electronics Co., Ltd. | Substrate connection member comprising substrate having opening part, which encompasses region in which through wire is formed, and conductive member formed on side surface of opening part, and electronic device comprising same |
| KR102611780B1 (en) * | 2018-10-26 | 2023-12-11 | 삼성전자 주식회사 | Electronic device and substrate connecting member comprising opening surrounding region where through wiring is formed and substrate having conductive member formed on the side of the opening |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202183910U (en) | Printed circuit board laminated hole structure | |
| CN106328357B (en) | A kind of flat surface transformer based on double-sided printed-circuit board | |
| TW301004B (en) | ||
| CN103219139B (en) | Inductance structure | |
| US7843303B2 (en) | Multilayer inductor | |
| CN100530455C (en) | Electronic transformer/inductor devices and methods for making same | |
| CN103298258B (en) | Circuit board and there is the power supply change-over device of this circuit board | |
| CN106332447B (en) | A kind of induction structure and preparation method thereof for printed circuit board potting technology | |
| CN101631433A (en) | Implementation method of printing thick copper foil in PCB | |
| CN202178922U (en) | Stacked hole structure of printed-circuit board | |
| CN103260350A (en) | Blind buried orifice plate laminating method and blind buried orifice plate manufactured with blind buried orifice plate laminating method | |
| CN103517581A (en) | Manufacturing method of multilayer PCB board and multilayer PCB board | |
| CN106463226B (en) | magnetic plate | |
| CN108124381A (en) | A kind of pcb board and its processing method of special blind hole | |
| CN202183911U (en) | Novel printed circuit board stacked hole structure | |
| TWI578873B (en) | Manufacturing method of high-density multilayer board | |
| CN105761881A (en) | Planar winding coil for double-column magnetic core structure | |
| CN110167289A (en) | A kind of production method of multilayer circuit board | |
| US11122674B1 (en) | PCB with coin and dielectric layer | |
| CN205789371U (en) | It is applicable to the plane winding coil of twin columns core structure | |
| CN108684160A (en) | A kind of multistage blind hole HDI board manufacturing methods | |
| CN204836777U (en) | Multilayer high frequency blind hole PCB circuit board | |
| CN107454761A (en) | High density increasing layer multi-layer board manufacturing method | |
| CN103458629B (en) | Multilayer circuit board and preparation method thereof | |
| CN104780719A (en) | Method for embedding inductors in printed-circuit board and printed-circuit board adopted by method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120328 Termination date: 20120815 |