CN202178250U - Packaging structure of high-power chip - Google Patents
Packaging structure of high-power chip Download PDFInfo
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- CN202178250U CN202178250U CN2011203084373U CN201120308437U CN202178250U CN 202178250 U CN202178250 U CN 202178250U CN 2011203084373 U CN2011203084373 U CN 2011203084373U CN 201120308437 U CN201120308437 U CN 201120308437U CN 202178250 U CN202178250 U CN 202178250U
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- metal layer
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Abstract
The utility model discloses a packaging structure of a high-power chip, which belongs to the technical field of packaging structures of chips. The packaging structure of the high-power chip comprises the chip, a chip surface metal layer and a pin soldering lug, wherein the chip and the chip surface metal layer are connected by ohmic contact, and the chip surface metal layer is connected with the pin soldering lug through soldering tin with low melting point. The packaging structure of the high-power chip can prevent the generation of obvious additional impedance between the chip and the chip surface metal layer and prevent the concentration of equilibrium carriers in the chip from changing significantly. The soldering tin with the low melting point is adopted, thereby reducing the soldering temperature during the packaging of the chip, reducing the probability of generating bubbles and further enabling the soldering between the chip surface metal layer and the pin soldering lug to be firmer. The packaging structure of the high-power chip can provide greater power consumption on the premise of not changing the external dimensions of the chip.
Description
Technical field
The utility model relates to a kind of encapsulating structure of chip, particularly relates to a kind of encapsulating structure of high-power chip, belongs to the semiconductor package technical field.
Background technology
So-called " encapsulation technology " is a kind of technology that integrated circuit is packed with the plastics or the ceramic material of insulation.With CPU is example, and actual volume of seeing and outward appearance are not the size and the looks of real CPU core, but the product of elements such as CPU core after through encapsulation.For chip, encapsulation is necessary, also is vital.On the one hand because chip must be isolated from the outside, cause electric property to descend to the corrosion of chip circuit to prevent airborne impurity; On the other hand, the chip after the encapsulation also is more convenient for installing and transportation.Because the quality of encapsulation technology also directly has influence on design and the manufacturing of the performance of chip self performance and the PCB that is attached thereto (printed circuit board), so it is vital.
The shell that is meant that the installation semiconductor integrated circuit chip is used is also we can say in encapsulation; It not only plays a part to lay, fix, seal, protect chip and increased thermal conductivity ability; But also be link up the chip internal world and external circuit bridge---the contact on the chip is wired on the pin of package casing, and these pins connect through the lead on the printed circuit board (PCB) and other devices again.Therefore, for a lot of IC products, encapsulation technology all is unusual the key link.
Experimental data shows, the every raising 5% of the power of chip, and the stability of circuit improves 17%, and circuit is reduced by 23% by the probability that static, surge damage.Obviously, along with the continuous progress of science and technology, chip high-power, low-power consumption will be the development trend of following chip, yet how to realize that the encapsulation of high-power chip will be the difficult problem of pendulum in face of each engineer.At present, the chip of 45nm technology has been applied in the manufacturing of integrated circuit, through increasing chip area or continuing to reduce the power that live width can't significantly improve chip.Therefore, will be a breach of improving chip power through improving chip-packaging structure.
Scolding tin melt temperature commonly used is 380 ℃ in the existing industry, has a kind of X650 scolding tin under 360 ℃ temperature, can get into molten condition in the market.
The utility model content
The purpose of the utility model provides a kind of encapsulating structure of high-power chip, makes chip under the prerequisite that does not change overall dimension, and bigger power consumption is provided.
For realizing above purpose; The encapsulating structure of the utility model high-power chip; Comprise chip, chip surface metal level and pin weld tabs; Said chip is connected through ohmic contact with said chip surface metal level, and said chip surface metal level is connected with said pin weld tabs through low melting point scolding tin.
The utility model has been obtained following beneficial effect with respect to prior art: ohmic contact makes and does not produce tangible additional impedance between chip and the chip surface metal level, and can not make the equilibrium carrier concentration of chip internal that significant the change taken place; Welding temperature is high more, and the generation rate of bubble will be high more during welding, and the welding temperature when low melting point scolding tin has reduced Chip Packaging has reduced the generation probability of bubble, thereby makes that the welding between chip surface metal level and the pin weld tabs is more firm.
As the preferred version of the utility model, said low-melting alloy can be selected X650 scolding tin for use.Scolding tin melt temperature commonly used is 380 ℃ in the existing industry; And X650 scolding tin can get into molten condition under 360 ℃ temperature; The utility model is selected X650 scolding tin for use; Welding temperature when having reduced Chip Packaging has reduced the generation probability of bubble, thereby makes metal level and pin weld tabs weld more solid and reliable.
The throat thickness of said scolding tin is preferably 6-10um, and compared with prior art, the utility model has reduced the throat thickness of scolding tin, at the generation probability that guarantees further to have reduced under metal level and the situation that the pin weld tabs well is connected bubble.
Description of drawings
A kind of novel package structure sketch map of Fig. 1 the utility model.
Among the figure: 1. chip; 2. chip surface metal level; 3. pin weld tabs; 4. scolding tin.
Embodiment
Below in conjunction with accompanying drawing the utility model is described in further detail.
As shown in Figure 1; A kind of encapsulating structure of high-power chip; Comprise chip 1, chip surface metal level 2 and pin weld tabs 3, chip 1 and chip surface metal level 2 are connected through ohmic contact, and chip surface metal level 2 is connected with pin weld tabs 3 through low melting point scolding tin 4.
So-called ohmic contact is meant that metal contacts with semi-conductive; The resistance value of its contact-making surface is much smaller than the resistance of semiconductor itself; When making assembly operation, most voltage drop is not in the behaviour area and at contact-making surface, thereby this contact can not influence the I-E characteristic of device.
Chip is in encapsulation process, and the appearance of bubble is unavoidable in the scolding tin.Yet the appearance of bubble is prone to cause the current unevenness that flows through chip even, causes partial breakdown, and phenomenons such as partial discharge greatly reduce the power of chip.In order to improve the use power of chip, reducing the probability that bubble occurs in the scolding tin will be efficient ways.
The melt temperature of the scolding tin that industry is commonly used is 380 ℃; Experiment showed, that welding temperature is high more, the generation rate of bubble will be high more during welding; Therefore the utility model selects for use low melting point scolding tin 4 as the welding material between chip surface metal level 2 and the pin weld tabs 3, preferred X650 scolding tin.The melt temperature of X650 scolding tin is 360 ℃, has compared with prior art reduced welding temperature, has reduced the probability that bubble occurs from another aspect.With PESDUC9D5VU is example, and adopting the bubble density of the PESDUC9D5VU of existing encapsulating structure production is 6107/mm
3, the bubble density of the PESDUC9D5VU of the encapsulating structure production of the high-power chip that employing the utility model provides is 5190/mm3, and bubble density reduces by 15%, and chip power improves 12.33%.
In addition, the utility model is guaranteeing to reduce the bubbles volume in the scolding tin 4 through the thickness that reduces scolding tin 4 under chip surface metal level 2 and the pin weld tabs 3 good situation about being connected.As the preferred version of the utility model, the preferred 6-10um of the throat thickness of scolding tin 4.
The utility model is not limited to the foregoing description; On the basis of the disclosed technical scheme of the utility model; Those skilled in the art is according to disclosed technology contents; Do not need performing creative labour just can make some replacements and distortion to some technical characterictics wherein, these replacements and distortion are all in the protection range of the utility model.
Claims (3)
1. the encapsulating structure of a high-power chip; Comprise chip, chip surface metal level and pin weld tabs; It is characterized in that said chip is connected through ohmic contact with said chip surface metal level, said chip surface metal level is connected with said pin weld tabs through low melting point scolding tin.
2. the encapsulating structure of high-power chip according to claim 1 is characterized in that, said low melting point scolding tin is X650 scolding tin.
3. the encapsulating structure of high-power chip according to claim 2 is characterized in that, the throat thickness of said scolding tin is 6-10um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203084373U CN202178250U (en) | 2011-08-23 | 2011-08-23 | Packaging structure of high-power chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203084373U CN202178250U (en) | 2011-08-23 | 2011-08-23 | Packaging structure of high-power chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202178250U true CN202178250U (en) | 2012-03-28 |
Family
ID=45868118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203084373U Expired - Lifetime CN202178250U (en) | 2011-08-23 | 2011-08-23 | Packaging structure of high-power chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202178250U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105280565A (en) * | 2015-11-18 | 2016-01-27 | 南京皓赛米电力科技有限公司 | A power module structure capable of improving welding quality |
-
2011
- 2011-08-23 CN CN2011203084373U patent/CN202178250U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105280565A (en) * | 2015-11-18 | 2016-01-27 | 南京皓赛米电力科技有限公司 | A power module structure capable of improving welding quality |
| CN105280565B (en) * | 2015-11-18 | 2018-01-12 | 南京皓赛米电力科技有限公司 | A kind of power module architectures for improving welding quality |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120328 |