CN201945906U - CMOS (Complementary Metal-Oxide-Semiconductor Transistor) reference source suitable for battery protection chip of two lithium batteries - Google Patents
CMOS (Complementary Metal-Oxide-Semiconductor Transistor) reference source suitable for battery protection chip of two lithium batteries Download PDFInfo
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Abstract
The utility model discloses a CMOS (complementary metal-oxide-semiconductor transistor) reference source suitable for a battery protection chip of two lithium batteries, which comprises a startup circuit, a PTAT (proportional to absolute temperature) production circuit, a CTAT (complimentary to absolute temperature) production circuit, a reference 1 production circuit, a reference 2 production circuit and three turn-off control circuits. The CMOS reference source only comprises NMOS (N-channel metal oxide semiconductor) tubes, PMOS(N-channel metal oxide semiconductor ) tubes and resistors, and has no triodes; and the circuit structure and manufacture process are relatively simple. The resources output from the reference 1 production circuit and the reference 2 production circuit are respectively used as a protection resource of a protection chip comparator regarding overcharge, overdischarge and overcurrent. The CMOS reference source further has the advantages of low in temperature coefficient and power consumption, and is suitable for the realization of the CMOS technology.
Description
Technical field
The utility model relates to a kind of battery protection chip CMOS reference source, specifically is meant a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to.
Background technology
In simulation, digital-to-analogue mixing, digital circuit, all often can use reference source circuit.The stability of reference source circuit is directly connected to the performance of entire circuit.Low-power consumption, high precision, miniaturization are the development trends of current battery management chip, satisfy the inevitable requirement of using especially, and the low-power consumption of research battery management chip has important practical value.Traditional reference design adopts and exposes two shortcomings based on the bipolar transistor band-gap reference: chip occupying area is very big, is unfavorable for reducing cost; The model parameter of bipolar transistor is difficult to accurately extract.In traditional in addition mimic channel, metal-oxide-semiconductor is operated in the strong inversion district and also means the more power consumption of needs, the perform region can be expanded in low power dissipation design, in the hope of the balance between power consumption and the area.
The utility model content
The purpose of this utility model is to provide a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to, is used to protect chip comparator about overcharging overdischarge, the protection benchmark of excess current, realization low-temperature coefficient, low-power consumption.
The purpose of this utility model is achieved through the following technical solutions:
A kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to of the utility model comprise being connected to V in turn
DDPower supply and V
SSStart-up circuit between the ground connection, PTAT produces circuit, CTAT produces circuit, first reference generating circuit, second reference generating circuit, described PTAT produce circuit also respectively with first reference generating circuit, second reference generating circuit connects, described CTAT produces circuit and also is connected with second reference generating circuit, also comprise respectively and start-up circuit, PTAT produces first of circuit connection and switches off control circuit, produce circuit with CTAT respectively, first reference generating circuit, second of second reference generating circuit connection switches off control circuit, and is connected with the 3rd and switches off control circuit on described second reference generating circuit.
Described start-up circuit comprises three metal-oxide-semiconductors, i.e. MP1, MP2, MN1, and wherein the source electrode of MP1 is connected to V
DDPower supply, MP1 grid and drain electrode are connected to the grid of MP2 after being connected, and the grid of MP2 is connected to the grid of MN1, the source electrode of MN1 and drain and all be connected to V
SSGround connection, the source electrode of MP2 all produce circuit with PTAT with drain electrode and are connected, and simultaneously, the source electrode of MP2 and first switches off control circuit and is connected.
Described PTAT produces circuit and comprises 6 metal-oxide-semiconductors and 1 resistance, that is: MP3, MP4, MP5, MP6, MN2, MN3 and resistance R 1, and wherein MP3, MP4 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP5 source electrode connects the MP3 drain electrode, the MP6 source electrode connects the MP4 drain electrode, the continuous back of the grid of MP3, MP4, MP5, MP6 and first switches off control circuit and is connected, the MN2 tube grid is connected with the drain electrode of MP5 with the continuous back of drain electrode, and the drain electrode of MN3 links to each other with drain electrode, the grid of MP6 simultaneously, and the grid of MN2, MN3 links to each other, the source electrode of MN3 is with after resistance R 1 is connected, and is connected to V altogether with the source electrode of MN2
SSGround connection, the grid of MP6 is connected with CTAT generation circuit, first reference generating circuit, second reference generating circuit respectively as the output port that PTAT produces circuit with the continuous back of drain electrode.
Described CTAT produces circuit and comprises 6 metal-oxide-semiconductors and 1 resistance, i.e. MP7, MP8, MP9, MP10, MN4, MN5 and resistance R 2, and wherein the source electrode of MP7, MP9 links to each other as power input, is connected to V jointly
DDPower supply, the MP8 source electrode links to each other with the MP7 drain electrode, the MP10 source electrode links to each other with the MP9 drain electrode, MP7, input port as CTAT generation circuit after the grid of MP8 links to each other is connected with the output port that PTAT produces circuit, the grid of MP9, the grid of MP10, after linking to each other, the drain electrode of MP10 produces the output port of circuit as CTAT, this output port with after second output that switches off control circuit is connected respectively with first reference generating circuit, second reference generating circuit connects, the drain electrode of MP8 respectively with the tube grid of MN5, the drain electrode of MN4 connects, the drain electrode of MP10 is connected to the drain electrode of MN5, and the source electrode of MN5 is connected the back and is connected to V by resistance R 2 with the grid of MN4
SSGround connection, the source electrode of MN4 is connected to V
SSGround connection.
Described first reference generating circuit comprises 4 metal-oxide-semiconductors and a resistance, that is: MP11, MP12, MP13, MP14 and resistance R 3, and wherein MP11, MP13 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP12 source electrode is connected with the MP11 drain electrode, and the output port with CTAT generation circuit after the grid of MP11, MP12 links to each other is connected, the MP14 source electrode is connected with the MP13 drain electrode, and the output port with PTAT generation circuit after the grid of MP13, MP14 links to each other is connected, and the continuous back of the drain electrode of MP12, MP14 is as the output V of first reference generating circuit
REF1, simultaneously by resistance R 3 and V
SSGround connection.
Described second reference generating circuit comprises 8 metal-oxide-semiconductors and a resistance, that is: MP15, MP16, MP17, MP18, MN6, MN7, MN8, MN9 and resistance R 4, and wherein MP15, MP17 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP16 source electrode connects the MP15 drain electrode, MP15, output port with PTAT generation circuit after the grid of MP16 links to each other is connected, the MP18 source electrode connects the MP17 drain electrode, MP17, output port with CTAT generation circuit after the grid of MP18 links to each other is connected, MP16, after the drain electrode of MP18 links to each other respectively with the drain electrode of MN6, the grid of MN6, the grid of MN7 connects, the drain electrode of MN9 is connected with the source electrode of MN7, the source electrode of MN6 respectively with the drain electrode of MN8, the grid of MN8, the grid of MN9 connects, and simultaneously and the 3rd switch off control circuit and is connected the source electrode of MN8 and the source electrode of MN9 while and V
SSGround connection, the drain electrode of MN7 is as the output V of second reference generating circuit
REF2, simultaneously by resistance R 4 and V
DDPower supply connects.
Described first switches off control circuit comprises a metal-oxide-semiconductor, that is: MP19, the source electrode of MP19 and V
DDPower supply connects, and the grid of MP19 is connected with the PD signal, and the drain electrode of MN19 produces circuit with start-up circuit, PTAT respectively as first output port that switches off control circuit and is connected.
Described second switches off control circuit comprises a metal-oxide-semiconductor, that is: MP20, the source electrode of MP20 and V
DDPower supply connects, and the grid of MP20 is connected with the PD signal, and the drain electrode of MP20 is connected with CTAT generation circuit, first reference generating circuit, second reference generating circuit respectively as second output port that switches off control circuit.
The described the 3rd switches off control circuit comprises a metal-oxide-semiconductor, that is: MN10, the source electrode of MN10 and V
SSGround connection, the grid of MN10 is connected with the PDN signal, and the drain electrode of MN10 is connected with second reference generating circuit as the 3rd output port that switches off control circuit.
The output of start-up circuit is connected to the input end that PTAT produces circuit and CTAT generation circuit; can allow PTAT generation circuit and CTAT produce circuit in power supply electrifying works smoothly; the output terminal of PTAT generation circuit and CTAT generation circuit is connected to the input end of first reference generating circuit and second reference generating circuit; first reference generating circuit and second reference generating circuit utilize PTAT to produce circuit and CTAT produces the electric current generation reference voltage output that circuit is imported; first output terminal that switches off control circuit produces circuit with PTAT and is connected with CTAT generation circuit; second output terminal that switches off control circuit produces circuit with CTAT respectively; first reference generating circuit; second reference generating circuit connects; the 3rd output terminal that switches off control circuit is connected with second reference generating circuit; switch off control circuit by first; second switches off control circuit; external signal PD that the 3rd switches off control circuit go up to connect and PDN control entire circuit turn on and off first reference generating circuit; two output terminals of second reference generating circuit are exported two benchmark V that two joint li-ion cell protection chips need respectively
REF1And V
REF2, and satisfy V
REF1+ V
REF2=V
DD
Principle of work is as follows:
MP1, MP2, MN1 form start-up circuit, and in the moment of power supply electrifying, MP1 charges to MN1, the MP2 grid is dragged down, and be that PTAT produces circuit 2 filling electric currents by MP2 to bias structure, make biasing circuit break away from the degeneracy point.
Similar with band-gap reference, the COMS voltage-reference that is operated in sub-threshold region also is based on the principle that be directly proportional with temperature (PTAT) and inverse ratio (CTAT) voltage or electric current compensate mutually.Different with band-gap reference, PTAT and CTAT derive from the V that is biased in the sub-threshold region metal-oxide-semiconductor
GSWith △ V
GSBe operated in the metal-oxide-semiconductor I of sub-threshold region
DS-V
GSCharacteristic is described by following formula:
In following formula, W and L are respectively the wide length of metal-oxide-semiconductor;
μ is a mobility, C
OXBe the gate oxide electric capacity of unit area, V
TBe thermal voltage, V
T=kT/q, k are Boltzmann constant, and T is a temperature, and q is an electron charge, U
2Be the parameter relevant, V with technology
THBe cut-in voltage, V
GSBe the metal-oxide-semiconductor gate source voltage, n is the subthreshold value factor.
Constitute PTAT by metal-oxide-semiconductor MP3, MP4, MP5, MP6, MN2, MN3 and resistance R 1 and produce circuit, produce electric current I with positive temperature coefficient (PTC)
1, the difference of the gate source voltage of MN2, MN3 flows through R1, has formed electric current I
1
V
GS（MN2）=?V
GS（MN2）+?I
1?R1 (2)
Obtain by (2) formula
N is the subthreshold value factor,
, V
T=kT/q, k are Boltzmann constant, and T is a temperature, and q is an electron charge, (W/L)
MN3(W/L)
MN2Be respectively the breadth length ratio of MN3 pipe and MN2 pipe.
Formula (3) shows I
1It is electric current with positive temperature coefficient (PTC);
Constitute CTAT by metal-oxide-semiconductor MP7, MP8, MP9, MP10, MN4, MN5 and resistance R 2 and produce circuit, produce and V
GSA road relevant electric current I
2, V
GSHas negative temperature coefficient.
I
2=V
GS(MN4)/R2 (4)
V in the formula
GS (MN4)Be the gate source voltage of MN4 pipe, I
2=V
GS (MN4)/ R2.
In first reference generating circuit, metal-oxide-semiconductor MP11, MP12, MP13, MP14 mirror image obtain the two-way electric current I that PTAT produces circuit and the output of CTAT generation circuit
1And I
2, I
3=I
1, I
5=I
2, the electric current I of summation
7Flow through R3, obtain the reference voltage that needs.
(5)
In the formula: n is the subthreshold value factor, V
TBe thermal voltage, V
T=kT/q, k are Boltzmann constant, and T is a temperature, and q is an electron charge, (W/L)
MN3(W/L)
MN2Be respectively the breadth length ratio of MN3 pipe and MN2 pipe, V
GS (MN4)Gate source voltage for the MN4 pipe.
Obtain from formula (5), as long as rationally regulate metal-oxide-semiconductor MN2, MN3, MN4, resistance R 2, the resistance of R3 just can obtain the voltage reference of a zero-temperature coefficient.
In second reference generating circuit, metal-oxide-semiconductor MP15, MP16, MP17, MP18 mirror image obtain the two-way electric current I of biasing circuit output
1And I
2, I
4=I
1, I
6=I
2, the electric current I of summation
8Flow through the current mirror of forming by MN6, MN7, MN8, MN9, mirror image I
9=I
8
In the formula: V
DDBe supply voltage; N is the subthreshold value factor, V
TBe thermal voltage, V
T=kT/q, k are Boltzmann constant, and T is a temperature, and q is an electron charge, (W/L)
MN3(W/L)
MN2Be respectively the breadth length ratio of MN3 pipe and MN2 pipe, V
GS (MN4)Gate source voltage for the MN4 pipe.
Obtain from formula (6), as long as rationally regulate metal-oxide-semiconductor MN2, MN3, MN4, resistance R 2, the resistance of R4 just can obtain the voltage reference of a zero-temperature coefficient.
Obtain from formula (5), formula (6),
V
REF2=?V
DD-?V
REF1 (7)
Obtain V from formula (7)
REF1And V
REF2And just in time equal supply voltage V
DD, be applied to be used to protect chip comparator about overcharging overdischarge, the protection benchmark of excess current in the two joint li-ion cell protection chip designs.
First, second, third switches off control circuit controls turning on and off of entire circuit by external signal, can make base modules enter dormant state when not needing benchmark job, reduces the power consumption of entire circuit.PDN and PD signal are the level opposite signal, can produce by external module.
The utility model compared with prior art has following advantage and beneficial effect:
A kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to of 1 the utility model only comprise the NMOS pipe, and PMOS pipe and resistance do not have triode, and circuit structure is all relative with preparation technology simple.
A kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to of 2 the utility model; the benchmark of first reference generating circuit and the output of second reference generating circuit is used for protecting respectively chip comparator about overcharging; overdischarge, the protection benchmark of excess current, its temperature coefficient is low, low in energy consumption.
A kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to of 3 the utility model are applicable to that CMOS technology realizes.
Description of drawings
Fig. 1 is the utility model circuit diagram.
Mark and corresponding parts title in the accompanying drawing:
The 1-start-up circuit, 2-PTAT produces circuit, and 3-CTAT produces circuit, 4-first reference generating circuit, 5-second reference generating circuit, 6-the 3rd switches off control circuit, and 7-first switches off control circuit, and 8-second switches off control circuit.
Embodiment
The utility model is described in further detail below in conjunction with embodiment, but embodiment of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to of the utility model comprise being connected to V in turn
DDPower supply and V
SSStart-up circuit 1 between the ground connection, PTAT produce circuit 2, CTAT produces circuit 3, first reference generating circuit 4, second reference generating circuit 5: start-up circuit 1 comprises three metal-oxide-semiconductor MP1, MP2, MN1, and wherein the source electrode of MP1 is connected to V
DDPower supply, MP1 grid and drain electrode are connected to the grid of MP2 after being connected, and the grid of MP2 is connected to the grid of MN1, the source electrode of MN1 and drain and all be connected to V
SSGround connection, the source electrode of MP2 and drain electrode all with PTAT generation circuit 2 in MP3, MP4, the grid of MP5, MP6 be connected simultaneously, and the source electrode of MP2 and first switches off control circuit, and the drain electrode of MP19 is connected in 7; PTAT produces circuit and comprises 6 metal-oxide-semiconductors and 1 resistance promptly: MP3, MP4, MP5, MP6, MN2, MN3 and resistance R 1, wherein MP3, MP4 source electrode link to each other as power input, are connected to V jointly
DDPower supply, MP5 source electrode connect the MP3 drain electrode, and the MP6 source electrode connects the MP4 drain electrode, the grid of MN2 is connected with the drain electrode of MP5 with the continuous back of drain electrode, and the drain electrode of MN3 links to each other with drain electrode, the grid of MP6 simultaneously, and the grid of MN2, MN3 links to each other, the source electrode of MN3 is with after resistance R 1 is connected, and is connected to V altogether with the source electrode of MN2
SSGround connection, the grid of MP6 link to each other with drain electrode, and output port that the back produces circuit 2 as PTAT produces the grid of MP15 in the grid, second reference generating circuit 5 of the grid of MP13 in the grid, first reference generating circuit 4 of the grid of MP7 in the circuit 3 and MP8 and MP14 with CTAT respectively and the grid of MP16 is connected; CTAT produces circuit 3 and comprises that 6 metal-oxide-semiconductors and 1 resistance are MP7, MP8, MP9, MP10, MN4, MN5 and resistance R 2, and wherein the source electrode of MP7, MP9 links to each other as power input, is connected to V jointly
DDPower supply, the MP8 source electrode links to each other with the MP7 drain electrode, the MP10 source electrode links to each other with the MP9 drain electrode, MP7, output port with PTAT generation circuit 2 after the grid of MP8 links to each other is connected, the grid of MP9, the grid of MP10, after linking to each other, the drain electrode of MP10 produces the output port of circuit 3 as CTAT, this output port and second switch off control circuit 8 output be connected after respectively with first reference generating circuit 4 in the grid of MP11 and the grid of MP12, the grid of the grid of MP17 and MP18 is connected in second reference generating circuit 5, the drain electrode of MP8 respectively with the tube grid of MN5, the drain electrode of MN4 connects, the drain electrode of MP10 is connected to the drain electrode of MN5, and the source electrode of MN5 is connected the back and is connected to V by resistance R 2 with the grid of MN4
SSGround connection, the source electrode of MN4 is connected to V
SSGround connection; First reference generating circuit 4 comprises 4 metal-oxide-semiconductors and a resistance promptly: MP11, MP12, MP13, MP14 and resistance R 3, wherein MP11, MP13 source electrode link to each other as power input, are connected to V jointly
DDPower supply, MP12 source electrode and MP11 drain electrode is connected, the MP14 source electrode is connected with the MP13 drain electrode, and the grid of MP13, the MP14 back that links to each other is connected with the output port of PTAT generation circuit, after the drain electrode of MP12, MP14 is continuous as the output V of first reference generating circuit
REF1, simultaneously by resistance R 3 and V
SSGround connection; Second reference generating circuit 5 comprises 8 metal-oxide-semiconductors and a resistance promptly: MP15, MP16, MP17, MP18, MN6, MN7, MN8, MN9 and resistance R 4, wherein MP15, MP17 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP16 source electrode connects the MP15 drain electrode, output port with PTAT generation circuit after the grid of MP15, MP16 links to each other is connected, the MP18 source electrode connects the MP17 drain electrode, the drain electrode of MP16, MP18 is connected with the drain electrode of MN6, the grid of MN6, the grid of MN7 respectively after linking to each other, and the drain electrode of MN9 is connected with the source electrode of MN7, and the source electrode of MN6 is connected with the drain electrode of MN8, the grid of MN8, the grid of MN9 respectively, and simultaneously and the 3rd switch off control circuit and 6 is connected the source electrode of MN8 and the source electrode of MN9 while and V
SSGround connection, the drain electrode of MN7 is as the output V of second reference generating circuit
REF2, simultaneously by resistance R 4 and V
DDPower supply connects; First switches off control circuit 7 comprises a metal-oxide-semiconductor promptly: MP19, the source electrode of MP19 and V
DDPower supply connects, and the grid of MP19 is connected with the PD signal, and the drain electrode of MN19 is connected the grid connection of MP3, MP4, MP5, MP6 in the source electrode, PTAT generation circuit 2 of MP2 respectively with in the start-up circuit 1; Second switches off control circuit 8 comprises a metal-oxide-semiconductor promptly: MP20, the source electrode of MP20 and V
DDPower supply connects, the grid of MP20 is connected with the PD signal, and the drain electrode of MP20 produces the grid of MP17 in the grid, second reference generating circuit 5 of the grid of MP11 in the grid, first reference generating circuit 4 of the grid of MP9 in the circuit and MP10 and MP12 with CTAT respectively and the grid of MP18 is connected; The 3rd switches off control circuit 6 comprises a metal-oxide-semiconductor promptly: MN10, the source electrode of MN10 and V
SSGround connection, the grid of MN10 is connected with the PDN signal, and the grid of MN8 and the grid of MN9 are connected in the drain electrode of MN10 and second reference generating circuit 5.
The output of start-up circuit 1 is connected to the input end that PTAT produces circuit 2 and CTAT generation circuit 3; PTAT generation circuit 2 and CTAT generation circuit 3 are worked smoothly in power supply electrifying; the output terminal of PTAT generation circuit 2 and CTAT generation circuit 3 is connected to the input end of first reference generating circuit 4 and second reference generating circuit 5; first reference generating circuit 4 and second reference generating circuit 5 utilize PTAT to produce circuit 2 and CTAT produces the electric current generation reference voltage output that circuit 3 is imported; first switch off control circuit 7 output terminal and the PTAT produces circuit 2 and produces circuit 3 with CTAT and be connected; second switch off control circuit 8 the output terminal produces circuit 3 with CTAT respectively; first reference generating circuit 4; second reference generating circuit 5 connects; the 3rd switch off control circuit 6 output terminal is connected with second reference generating circuit 5; switch off control circuit 7 by first; second switches off control circuit 8; external signal PD that the 3rd switches off control circuit connects on 6 and PDN control entire circuit turn on and off first reference generating circuit 4; two output terminals of second reference generating circuit 5 are exported two benchmark V that two joint li-ion cell protection chips need respectively
REF1And V
REF2, and satisfy V
REF1+ V
REF2=V
DD
As described above, just can realize the utility model well.
Claims (9)
1. one kind is applicable to two joint li-ion cell protection chip CMOS reference sources, it is characterized in that: comprise being connected to V in turn
DDPower supply and V
SSStart-up circuit between the ground connection (1), PTAT produces circuit (2), CTAT produces circuit (3), first reference generating circuit (4), second reference generating circuit (5), described PTAT produce circuit (2) also respectively with first reference generating circuit (4), second reference generating circuit (5) connects, described CTAT produces circuit (3) and also is connected with second reference generating circuit (5), also comprise respectively and start-up circuit (1), first switch off control circuit (7) that PTAT produces that circuit (2) connects, produce circuit (3) with CTAT respectively, first reference generating circuit (4), what second reference generating circuit (5) connected second switches off control circuit (8), is connected with the 3rd switch off control circuit (6) on described second reference generating circuit (5).
2. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1, it is characterized in that: described start-up circuit (1) comprises three metal-oxide-semiconductors, that is: MP1, MP2, MN1, wherein the source electrode of MP1 is connected to V
DDPower supply, MP1 grid and drain electrode are connected to the grid of MP2 after being connected, and the grid of MP2 is connected to the grid of MN1, the source electrode of MN1 and drain and all be connected to V
SSGround connection, the source electrode of MP2 all is connected with PTAT generation circuit (2) with drain electrode, simultaneously, the source electrode of MP2 and first switch off control circuit (7) be connected.
3. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1; it is characterized in that: described PTAT produces circuit (2) and comprises 6 metal-oxide-semiconductors and 1 resistance; that is: MP3, MP4, MP5, MP6, MN2, MN3 and resistance R 1; wherein MP3, MP4 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP5 source electrode connects the MP3 drain electrode, the MP6 source electrode connects the MP4 drain electrode, the grid of MP3, MP4, MP5, MP6 link to each other back and first switch off control circuit (7) be connected, the MN2 tube grid is connected with the drain electrode of MP5 with the continuous back of drain electrode, and the drain electrode of MN3 links to each other with drain electrode, the grid of MP6 simultaneously, and the grid of MN2, MN3 links to each other, the source electrode of MN3 is with after resistance R 1 is connected, and is connected to V altogether with the source electrode of MN2
SSGround connection, the grid of MP6 is connected with CTAT generation circuit (3), first reference generating circuit (4), second reference generating circuit (5) respectively as the output port that PTAT produces circuit (2) with the continuous back of drain electrode.
4. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1; it is characterized in that: described CTAT produces circuit (3) and comprises 6 metal-oxide-semiconductors and 1 resistance; be MP7, MP8, MP9, MP10, MN4, MN5 and resistance R 2; wherein the source electrode of MP7, MP9 links to each other as power input, is connected to V jointly
DDPower supply, the MP8 source electrode links to each other with the MP7 drain electrode, the MP10 source electrode links to each other with the MP9 drain electrode, MP7, input port as CTAT generation circuit (3) after the grid of MP8 links to each other is connected with the output port that PTAT produces circuit (2), the grid of MP9, the grid of MP10, after linking to each other, the drain electrode of MP10 produces the output port of circuit (3) as CTAT, this output port with after second output that switches off control circuit (8) is connected respectively with first reference generating circuit (4), second reference generating circuit (5) connects, the drain electrode of MP8 respectively with the tube grid of MN5, the drain electrode of MN4 connects, the drain electrode of MP10 is connected to the drain electrode of MN5, and the source electrode of MN5 is connected the back and is connected to V by resistance R 2 with the grid of MN4
SSGround connection, the source electrode of MN4 is connected to V
SSGround connection.
5. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1; it is characterized in that: described first reference generating circuit (4) comprises 4 metal-oxide-semiconductors and a resistance; that is: MP11, MP12, MP13, MP14 and resistance R 3; wherein MP11, MP13 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP12 source electrode is connected with the MP11 drain electrode, and the output port with CTAT generation circuit (3) after the grid of MP11, MP12 links to each other is connected, the MP14 source electrode is connected with the MP13 drain electrode, and the output port with PTAT generation circuit (2) after the grid of MP13, MP14 links to each other is connected, and the continuous back of the drain electrode of MP12, MP14 is as the output V of first reference generating circuit (4)
REF1, simultaneously by resistance R 3 and V
SSGround connection.
6. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1; it is characterized in that: described second reference generating circuit (5) comprises 8 metal-oxide-semiconductors and a resistance; that is: MP15, MP16, MP17, MP18, MN6, MN7, MN8, MN9 and resistance R 4; wherein MP15, MP17 source electrode link to each other as power input, are connected to V jointly
DDPower supply, the MP16 source electrode connects the MP15 drain electrode, MP15, output port with PTAT generation circuit (2) after the grid of MP16 links to each other is connected, the MP18 source electrode connects the MP17 drain electrode, MP17, output port with CTAT generation circuit (3) after the grid of MP18 links to each other is connected, MP16, after the drain electrode of MP18 links to each other respectively with the drain electrode of MN6, the grid of MN6, the grid of MN7 connects, the drain electrode of MN9 is connected with the source electrode of MN7, the source electrode of MN6 respectively with the drain electrode of MN8, the grid of MN8, the grid of MN9 connects, and simultaneously and the 3rd switch off control circuit and is connected the source electrode of MN8 and the source electrode of MN9 while and V
SSGround connection, the drain electrode of MN7 is as the output V of second reference generating circuit (5)
REF2, simultaneously by resistance R 4 and V
DDPower supply connects.
7. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1 is characterized in that: described first switch off control circuit (7) comprise a metal-oxide-semiconductor, that is: MP19, the source electrode of MP19 and V
DDPower supply connects, and the grid of MP19 is connected with the PD signal, and the drain electrode of MN19 produces circuit (2) with start-up circuit (1), PTAT respectively as first output port that switches off control circuit (7) and is connected.
8. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1 is characterized in that: described second switch off control circuit (8) comprise a metal-oxide-semiconductor, that is: MP20, the source electrode of MP20 and V
DDPower supply connects, and the grid of MP20 is connected with the PD signal, and the drain electrode of MP20 is connected with CTAT generation circuit (3), first reference generating circuit (4), second reference generating circuit (5) respectively as second output port that switches off control circuit (8).
9. a kind of two joint li-ion cell protection chip CMOS reference sources that are applicable to according to claim 1 is characterized in that: the described the 3rd switch off control circuit (6) comprise a metal-oxide-semiconductor promptly: MN10, the source electrode of MN10 and V
SSGround connection, the grid of MN10 is connected with the PDN signal, and the drain electrode of MN10 is connected with second reference generating circuit (5) as the 3rd output port that switches off control circuit (6).
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| CN201120023675XU CN201945906U (en) | 2011-01-25 | 2011-01-25 | CMOS (Complementary Metal-Oxide-Semiconductor Transistor) reference source suitable for battery protection chip of two lithium batteries |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117088A (en) * | 2011-01-25 | 2011-07-06 | 成都瑞芯电子有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) reference source applicable to protective chip with two lithium batteries |
| CN111381625A (en) * | 2020-03-12 | 2020-07-07 | 上海华虹宏力半导体制造有限公司 | Reference source circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117088A (en) * | 2011-01-25 | 2011-07-06 | 成都瑞芯电子有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) reference source applicable to protective chip with two lithium batteries |
| CN102117088B (en) * | 2011-01-25 | 2012-09-05 | 成都瑞芯电子有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) reference source applicable to protective chip with two lithium batteries |
| CN111381625A (en) * | 2020-03-12 | 2020-07-07 | 上海华虹宏力半导体制造有限公司 | Reference source circuit |
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