CN201725787U - Novel plate compression joint double chip ceramic package - Google Patents
Novel plate compression joint double chip ceramic package Download PDFInfo
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- CN201725787U CN201725787U CN2010202130100U CN201020213010U CN201725787U CN 201725787 U CN201725787 U CN 201725787U CN 2010202130100 U CN2010202130100 U CN 2010202130100U CN 201020213010 U CN201020213010 U CN 201020213010U CN 201725787 U CN201725787 U CN 201725787U
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- cathode
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- anode
- chip
- gate lead
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- 239000000919 ceramic Substances 0.000 title claims abstract description 48
- 230000006835 compression Effects 0.000 title abstract description 5
- 238000007906 compression Methods 0.000 title abstract description 5
- 230000007704 transition Effects 0.000 claims abstract description 19
- 229910052573 porcelain Inorganic materials 0.000 claims description 21
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000007789 sealing Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 3
- 230000003026 anti-oxygenic effect Effects 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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Abstract
The utility model relates to a novel plate compression joint double-chip ceramic package which consists of a ceramic base, a transition electrode (7) and an upper cover, wherein the ceramic base mainly comprises an anode flange (1), a ceramic ring (2), an anode sealing ring (3), an anode electrode (4), a gate pole leading wire pipe I (5-1), a gate pole leading wire pipe II (5-2), a cathode leading wire pipe (6-1) and a cathode inserting piece (6-2); the transition electrode (7) is arranged between the ceramic base and the upper cover; the upper cover mainly comprises a cathode electrode (8) and a cathode flange (9); and the cathode flange (9) is concentrically welded at the outer edge of the cathode electrode (8). The novel plate compression joint double chip ceramic package provided by the utility model can achieve the effect of double-chip series connection packaging.
Description
(1) technical field
The utility model relates to a kind of novel ceramic package, relates in particular to a kind of compression joint type ceramic package that can encapsulate two chips in single flat device, belongs to electric and electronic technical field.
(2) background technology
Large power semiconductor device generally is made up of chip, shell, radiator.For the plate device of ceramic structure, all be the packaged type that adopts single chip, that is to say in a device, only to encapsulate a chip that this single packaged type advantage is that simple in structure, good heat dissipation effect, technological requirement are low; Shortcoming is that device volume is big, consumptive material is high, external circuit is many.Because be subjected to the restriction of individual devices capacity, when using, reality generally to adopt the serial or parallel connection of a plurality of devices, the large power semiconductor device of 6 inches this present maximum specification of picture, the individual devices capacity can reach 8500V/3000A, all will adopt the connection in series-parallel of up to a hundred devices when using on the project of transmitting and converting electricity of Three Gorges, the new device of therefore developing two or more Chip Packaging seems particularly urgent.The module package mode of employing high performance plastics shell can realize the assembled package of a plurality of chips at present, but all multifactor influences such as module package is withstand voltage owing to being subjected to, sealing, heat radiation, how therefore the general application that only is adapted at the middle low power field make the flat ceramic structure with high insulation, high strength, high sealing can realize that the composition encapsulation of two even a plurality of chips has become one of current main direction in the industry.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and a kind of novel plate crimped dual-chip encapsulated ceramic package that can realize two chip Series Packages is provided.
The purpose of this utility model is achieved in that a kind of novel plate crimped dual-chip encapsulated ceramic package, and described shell is made up of ceramic base, transition electrode and loam cake three parts;
Described ceramic base is mainly by anode flange, the porcelain ring, the anode seal ring, anode electrode, gate lead pipe one, gate lead pipe two, the cathode leg pipe, the negative electrode inserted sheet is formed, described anode seal ring inner edge is welded on the outer rim of anode electrode with one heart, the outer rim of described anode seal ring is welded on the lower surface of porcelain ring with one heart, anode flange is welded on the upper surface of porcelain ring with one heart, gate lead pipe one and gate lead pipe two levels are connected to the shell wall central authorities of porcelain ring, described cathode leg pipe level is connected to the shell wall central authorities of porcelain ring, and described negative electrode inserted sheet level is connected in the middle of the cathode leg pipe;
Described transition electrode places between ceramic base and the loam cake;
Described loam cake mainly is made up of cathode electrode and cathode flange, and cathode flange is welded on the outer rim of cathode electrode with one heart.
The utility model novel plate crimped dual-chip encapsulated ceramic package, the trigger end of a chip of described gate lead Guan Yiwei, the trigger end of described another chip of gate lead Guan Erwei.
The utility model novel plate crimped dual-chip encapsulated ceramic package, described cathode leg pipe and negative electrode inserted sheet are the cathode end of a chip, and described cathode leg pipe is connected with transition electrode.
The utility model novel plate crimped dual-chip encapsulated ceramic package, described porcelain ring adopts 95% aluminium oxide ceramics, has very high insulating properties.
The utility model novel plate crimped dual-chip encapsulated ceramic package, described anode electrode, transition electrode, cathode electrode, anode flange, anode seal ring and cathode flange adopt the oxygenless copper material of high conduction.
The utility model novel plate crimped dual-chip encapsulated ceramic package, all metal surfaces are electroplate with nickel.
The utility model novel plate crimped dual-chip encapsulated ceramic package, described gate lead pipe one, gate lead pipe two, cathode leg pipe and negative electrode inserted sheet adopt the iron-nickel alloy material that is complementary with the ceramic coefficient of expansion.
The beneficial effects of the utility model are:
(1) insulating properties height:, thereby have very high insulating properties because the porcelain ring adopts 95% aluminium oxide ceramics.
(2) perfect heat-dissipating: because the oxygenless copper material of described anode electrode, transition electrode, cathode electrode, anode flange, anode seal ring, the high conduction of cathode flange employing, be fit to high temperature vacuum brazing, and all electrodes all have super flat surface, can closely contact with chip, thereby increased area of dissipation, improve the ability of device radiating effect and thermal fatigue resistance.
(3) good airproof performance: because described gate lead pipe, cathode leg pipe, the negative electrode inserted sheet adopts the iron-nickel alloy material that is complementary with the ceramic coefficient of expansion, therefore after the welding can and pottery between form very high intensity and sealing.
(4) good in oxidation resistance:, thereby make it not only have high conduction and can have better antioxygenic property because all metal surfaces finally electroplate the thick semi-bright nickel of 3-7 μ.
(4) description of drawings
Fig. 1 is a general structure schematic diagram of the present utility model.
Fig. 2 is a ceramic base vertical view of the present utility model.
Fig. 3 is a upper cover top view of the present utility model.
Among the figure:
Anode flange 1, porcelain ring 2, anode seal ring 3, anode electrode 4, gate lead pipe one 5-1, gate lead pipe two 5-2, cathode leg pipe 6-1, negative electrode inserted sheet 6-2, transition electrode 7, cathode electrode 8, cathode flange 9.
(5) embodiment
Referring to Fig. 1, the utility model relates to a kind of novel plate crimped dual-chip encapsulated ceramic package, is made up of ceramic base, transition electrode 7 and loam cake three parts;
Referring to Fig. 1～2, described ceramic base is mainly by anode flange 1, porcelain ring 2, anode seal ring 3, anode electrode 4, gate lead pipe one 5-1, gate lead pipe two 5-2, cathode leg pipe 6-1, negative electrode inserted sheet 6-2 forms, anode seal ring 3 inner edges are welded on the outer rim of anode electrode 4 with one heart, outer rim is welded on the lower surface of porcelain ring 2 with one heart, anode flange 1 is welded on the upper surface of porcelain ring 2 with one heart, anode flange 1, the superimposed from top to bottom concentric welding of porcelain ring 2 and anode seal ring 3, gate lead pipe one 5-1 and gate lead pipe two 5-2 levels are connected to the shell wall central authorities of porcelain ring 2, and be mutually 180 ° of directions, cathode leg pipe 6-1 level is connected to the shell wall central authorities of porcelain ring 2, and it is perpendicular to close the line of gate lead pipe two 5-2 in two gate lead pipes, one 5-1, and negative electrode inserted sheet 6-2 level is connected in the middle of the cathode leg pipe 6-1.
Referring to Fig. 1, described transition electrode 7 places between ceramic base and the loam cake, and the gap between transition electrode 7 and the anode electrode 4 can encapsulate a chip, and the gap between transition electrode 7 and the cathode electrode 8 can encapsulate another chip.
Referring to Fig. 1, Fig. 3, described loam cake mainly is made up of cathode electrode 8 and cathode flange 9.Cathode flange 9 is welded on the outer rim of cathode electrode 8 with one heart.
The upper surface of described transition electrode 7 is the anode of a chip, and the lower surface is the negative electrode of another chip.
Described gate lead pipe one 5-1 is the trigger end of a chip, and described gate lead pipe two 5-2 are the trigger end of another chip.
Described cathode leg pipe 6-1, negative electrode inserted sheet 6-2 is the cathode end of a chip, is connected with transition electrode during encapsulation.
Described porcelain ring 2 adopts 95% aluminium oxide ceramics, has very high insulating properties.
Described anode electrode 4, transition electrode 7, cathode electrode 8, anode flange 1, anode seal ring 3, cathode flange 9 adopt the oxygenless copper material of high conduction, be fit to high temperature vacuum brazing, all electrodes all have super flat surface, can closely contact with chip, satisfy compression joint type encapsulation requirement, improve the ability of device radiating effect and thermal fatigue resistance.
Described gate lead pipe one 5-1, gate lead pipe two 5-2, cathode leg pipe 6-1 and negative electrode inserted sheet 6-2 adopt the iron-nickel alloy material that is complementary with the ceramic coefficient of expansion, after the welding can and pottery between form very high intensity and sealing, the thick semi-bright nickel of 3-7 μ is finally electroplated in all metal surfaces, make it have high conduction, antioxygenic property, can satisfy the encapsulation requirement of twin-core sheet well.
Claims (8)
1. novel plate crimped dual-chip encapsulated ceramic package, it is characterized in that: described shell is made up of ceramic base, transition electrode (7) and loam cake three parts;
Described ceramic base is mainly by anode flange (1), porcelain ring (2), anode seal ring (3), anode electrode (4), gate lead pipe one (5-1), gate lead pipe two (5-2), cathode leg pipe (6-1), negative electrode inserted sheet (6-2) is formed, described anode seal ring (3) inner edge is welded on the outer rim of anode electrode (4) with one heart, the outer rim of described anode seal ring (3) is welded on the lower surface of porcelain ring (2) with one heart, anode flange (1) is welded on the upper surface of porcelain ring (2) with one heart, gate lead pipe one (5-1) and gate lead pipe two (5-2) level are connected to the shell wall central authorities of porcelain ring (2), described cathode leg pipe (6-1) level is connected to the shell wall central authorities of porcelain ring (2), and described negative electrode inserted sheet (6-2) level is connected in the middle of the cathode leg pipe (6-1);
Described transition electrode (7) places between ceramic base and the loam cake;
Described loam cake mainly is made up of cathode electrode (8) and cathode flange (9), and cathode flange (9) is welded on the outer rim of cathode electrode (8) with one heart.
2. a kind of according to claim 1 novel plate crimped dual-chip encapsulated ceramic package is characterized in that: described gate lead pipe one (5-1) is the trigger end of a chip, and described gate lead pipe two (5-2) is the trigger end of another chip.
3. a kind of according to claim 1 novel plate crimped dual-chip encapsulated ceramic package, it is characterized in that: described cathode leg pipe (6-1) and negative electrode inserted sheet (6-2) are the cathode end of a chip, and described cathode leg pipe (6-1) is connected with transition electrode (7).
4. a kind of according to claim 1 novel plate crimped dual-chip encapsulated ceramic package is characterized in that: described porcelain ring (2) adopts 95% aluminium oxide ceramics.
5. as a kind of novel plate crimped dual-chip encapsulated ceramic package as described in claim 1 or 4, it is characterized in that: described anode electrode (4), transition electrode (7), cathode electrode (8), anode flange (1), anode seal ring (3) and cathode flange (9) adopt the oxygenless copper material of high conduction.
6. a kind of according to claim 1 novel plate crimped dual-chip encapsulated ceramic package, it is characterized in that: all metal surfaces are electroplate with nickel.
7. as a kind of novel plate crimped dual-chip encapsulated ceramic package as described in claim 1 or 4 or 6, it is characterized in that: described gate lead pipe one (5-1), gate lead pipe two (5-2), cathode leg pipe (6-1) and negative electrode inserted sheet (6-2) adopt the iron-nickel alloy material that is complementary with the ceramic coefficient of expansion.
8. as a kind of novel plate crimped dual-chip encapsulated ceramic package as described in the claim 5, it is characterized in that: described gate lead pipe one (5-1), gate lead pipe two (5-2), cathode leg pipe (6-1) and negative electrode inserted sheet (6-2) adopt the iron-nickel alloy material that is complementary with the ceramic coefficient of expansion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202130100U CN201725787U (en) | 2010-05-31 | 2010-05-31 | Novel plate compression joint double chip ceramic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202130100U CN201725787U (en) | 2010-05-31 | 2010-05-31 | Novel plate compression joint double chip ceramic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201725787U true CN201725787U (en) | 2011-01-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010202130100U Expired - Lifetime CN201725787U (en) | 2010-05-31 | 2010-05-31 | Novel plate compression joint double chip ceramic package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201725787U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916745A (en) * | 2010-05-31 | 2010-12-15 | 江阴市赛英电子有限公司 | Novel plate crimped dual-chip encapsulated ceramic package |
| CN102768997A (en) * | 2012-07-28 | 2012-11-07 | 江阴市赛英电子有限公司 | High-power complete wafer IGBT (insulated gate bipolar translator) ceramic package housing |
| CN102768999A (en) * | 2012-07-28 | 2012-11-07 | 江阴市赛英电子有限公司 | High-power integral wafer IGBT (insulated gate bipolar transistor) packaging structure |
| CN103380495A (en) * | 2012-01-11 | 2013-10-30 | 松下电器产业株式会社 | Pressure contact type semiconductor device and method for fabricating same |
-
2010
- 2010-05-31 CN CN2010202130100U patent/CN201725787U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916745A (en) * | 2010-05-31 | 2010-12-15 | 江阴市赛英电子有限公司 | Novel plate crimped dual-chip encapsulated ceramic package |
| CN103380495A (en) * | 2012-01-11 | 2013-10-30 | 松下电器产业株式会社 | Pressure contact type semiconductor device and method for fabricating same |
| CN103380495B (en) * | 2012-01-11 | 2016-05-18 | 松下知识产权经营株式会社 | Crimp type semiconductor device and manufacture method thereof |
| CN102768997A (en) * | 2012-07-28 | 2012-11-07 | 江阴市赛英电子有限公司 | High-power complete wafer IGBT (insulated gate bipolar translator) ceramic package housing |
| CN102768999A (en) * | 2012-07-28 | 2012-11-07 | 江阴市赛英电子有限公司 | High-power integral wafer IGBT (insulated gate bipolar transistor) packaging structure |
| CN102768999B (en) * | 2012-07-28 | 2014-12-03 | 江阴市赛英电子有限公司 | High-power integral wafer IGBT (insulated gate bipolar transistor) packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: 214405 Jiangsu city in Jiangyin Province, South Gate Street: Road No. 60 Patentee after: JIANGYIN SAIYING ELECTRON CO., LTD. Address before: 214432 No. 6, Jing Jing Village, Chengjiang industry concentrated area, Jiangsu, Jiangyin Patentee before: Jiangyin Saiying Electron Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110126 |