CN201681861U - Embedded base island encapsulation structure - Google Patents

Embedded base island encapsulation structure Download PDF

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Publication number
CN201681861U
CN201681861U CN201020177437XU CN201020177437U CN201681861U CN 201681861 U CN201681861 U CN 201681861U CN 201020177437X U CN201020177437X U CN 201020177437XU CN 201020177437 U CN201020177437 U CN 201020177437U CN 201681861 U CN201681861 U CN 201681861U
Authority
CN
China
Prior art keywords
pin
base island
dao
back side
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN201020177437XU
Other languages
Chinese (zh)
Inventor
王新潮
梁志忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201020177437XU priority Critical patent/CN201681861U/en
Application granted granted Critical
Publication of CN201681861U publication Critical patent/CN201681861U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Abstract

The utility model relates to an embedded base island encapsulation structure, which comprises a base island (1), a pin (2), electrically conducting or non-conducting adhesive materials (6), a chip (7), a metal wire (8) and encapsulation materials (9) with fillings. First metal layers (4) are arranged on the front surfaces of the base island (1) and the pin (2), a second metal layer (5) is arranged on the back surface of the pin (2), encapsulation materials (3) without fillings are embedded into areas on the outer periphery of the pin (2), the back surface of the base island (1) and between the base island (1) and the pin (2), the outer periphery on the lower portion of the pin (2), the back surface of the base island (1) and the lower portions of the back surface of the base island (1) and the pin (2) are connected into a whole by the encapsulation materials (3) without fillings, and the size of the back surface of the pin (2) is led to be smaller than the that of the front surface of the pin (2) so as to form a pin structure with a large upper portion and a small lower portion. The embedded base island encapsulation structure has the advantage of large bound capacity of an encapsulation body and a metal pin.

Description

Baried type base island encapsulating structure
(1) technical field
The utility model relates to a kind of baried type base island encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
Traditional encapsulating structure, detailed following explanation:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 3) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of above-mentioned lead frame below in encapsulation process, having existed:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in Figure 4) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and the big baried type base island encapsulating structure of constraint ability of a kind of plastic-sealed body and metal leg is provided.
The purpose of this utility model is achieved in that a kind of baried type base island encapsulating structure, comprise Ji Dao, pin, conduction or non-conductive bonding material, chip, metal wire and the filler plastic packaging material arranged, front at described Ji Dao and pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, be provided with chip in front, basic island by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with the filler plastic packaging material, in described pin periphery, no filler plastic packaging material is set in zone between the Ji Dao back side and Ji Dao and the pin, described no filler plastic packaging material is with periphery, pin bottom, the bottom of the Ji Dao back side and the Ji Dao back side and pin links into an integrated entity, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The beneficial effects of the utility model are:
1) because the zone between described metal leg and metal leg is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
2) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form the slightly little and big slightly structure of positive basic island size of the size of back side Ji Dao, and with the size that varies in size up and down of a Ji Dao by tighter more difficult generation slip that no filler plastic packaging material coated and fall pin.
(4) description of drawings
Fig. 1 is the utility model baried type base island encapsulating structure schematic diagram.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was for formed insulation pin schematic diagram in the past.
Fig. 4 pin figure for what formed in the past.
Reference numeral among the figure:
The base island 1, pin 2, no filler plastic packaging material 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material 9 is arranged.
(5) embodiment
Referring to Fig. 1～2, Fig. 1 is the utility model baried type base island encapsulating structure schematic diagram.Fig. 2 is the vertical view of Fig. 1.By Fig. 1 and Fig. 2 as can be seen, the utility model baried type base island encapsulating structure, comprise basic island 1, pin 2, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material 9 is arranged, front at described basic island 1 and pin 2 is provided with the first metal layer 4, be provided with second metal level 5 at the back side of described pin 2, be provided with chip 7 in 1 front, basic island by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material 9, in described pin 2 peripheries, no filler plastic packaging material 3 is set in zone between base 1 back side, island and basic island 1 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin 2 bottom, the bottom of base 1 back side, island and 1 back side, basic island and pin 2 links into an integrated entity, and make described pin 2 back side sizes less than pin 2 positive sizes, form up big and down small pin configuration.

Claims (1)

1. baried type base island encapsulating structure, comprise Ji Dao (1), pin (2), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, front at described Ji Dao (1) and pin (2) is provided with the first metal layer (4), be provided with second metal level (5) at the back side of described pin (2), be provided with chip (7) in Ji Dao (1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), it is characterized in that: in described pin (2) periphery, no filler plastic packaging material (3) is set in zone between Ji Dao (1) back side and Ji Dao (1) and the pin (2), described no filler plastic packaging material (3) is with pin (2) periphery, bottom, the bottom of Ji Dao (1) back side and Ji Dao (1) back side and pin (2) links into an integrated entity, and make described pin (2) back side size less than the positive size of pin (2), form up big and down small pin configuration.
CN201020177437XU 2010-04-26 2010-04-26 Embedded base island encapsulation structure Expired - Lifetime CN201681861U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201020177437XU CN201681861U (en) 2010-04-26 2010-04-26 Embedded base island encapsulation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201020177437XU CN201681861U (en) 2010-04-26 2010-04-26 Embedded base island encapsulation structure

Publications (1)

Publication Number Publication Date
CN201681861U true CN201681861U (en) 2010-12-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201020177437XU Expired - Lifetime CN201681861U (en) 2010-04-26 2010-04-26 Embedded base island encapsulation structure

Country Status (1)

Country Link
CN (1) CN201681861U (en)

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Granted publication date: 20101222