CN201681867U - Multi-base island embedded type multi-turn pin encapsulation structure - Google Patents
Multi-base island embedded type multi-turn pin encapsulation structure Download PDFInfo
- Publication number
- CN201681867U CN201681867U CN201020177733XU CN201020177733U CN201681867U CN 201681867 U CN201681867 U CN 201681867U CN 201020177733X U CN201020177733X U CN 201020177733XU CN 201020177733 U CN201020177733 U CN 201020177733U CN 201681867 U CN201681867 U CN 201681867U
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- China
- Prior art keywords
- pin
- pins
- dao
- base
- back side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a multi-base island embedded type multi-turn pin encapsulation structure which comprises multiple base islands (1), pins (2), a conductive or nonconductive bonding material (6), a chip (7), a metal wire (8) and a packed plastic encapsulated material (9), wherein a first metal layer (4) is arranged on the front surface of each base island (1) and each pin (2); a second metal layer (5) is arranged on the back surface of each pin (2); the multiple base islands (1) are arranged, and the multiple turns of pins (2) are arranged; a packless plastic encapsulated material (3) is embedded on the peripheries of the pins (2), the back surfaces of the base islands (1), areas among the base islands (1), areas between the base islands (1) and the pins (2), as well as areas among the pins (2); the peripheries at the lower parts of the pins (2), the back surfaces of the base islands (1), the back surfaces of the base islands (1) and the lower parts of the pins (2), as well as the lower parts of the pins (2) and the lower parts of other pins (2) are connected into a whole by the packless plastic encapsulated material (3); and the size of the back surfaces of the pins (2) is smaller than that of the front surfaces of the pins (2), so as to form a pin structure with larger upper part and smaller lower part. The multi-base island embedded type multi-turn pin encapsulation structure has the benefit that a plastic encapsulated body and a metal leg have large binding capacity.
Description
(1) technical field
The utility model relates to a kind of a plurality of base island embedded type multi-turn leaded package.Belong to the semiconductor packaging field.
(2) background technology
Traditional encapsulating structure, detailed following explanation:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 3) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of above-mentioned lead frame below in encapsulation process, having existed:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in Figure 4) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and the big a plurality of base island embedded type multi-turn leaded package of constraint ability of a kind of plastic-sealed body and metal leg is provided.
The purpose of this utility model is achieved in that a kind of a plurality of base island embedded type multi-turn leaded package, comprise Ji Dao, pin, conduction or non-conductive bonding material, chip, metal wire and the filler plastic packaging material arranged, front at described Ji Dao and pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, be provided with chip in front, basic island by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with the filler plastic packaging material, described Ji Dao is provided with a plurality of, pin is provided with multi-turn, in described pin periphery, the Ji Dao back side, zone between Ji Dao and the basic island, zone between zone between Ji Dao and the pin and pin and the pin is equipped with packless plastic packaging material, described packless plastic packaging material is with periphery, pin bottom, the Ji Dao back side, the bottom of the bottom of the Ji Dao back side and pin and pin and pin links into an integrated entity, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The beneficial effects of the utility model are:
1) because the zone between described metal leg and metal leg is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
2) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form the slightly little and big slightly structure of positive basic island size of the size of back side Ji Dao, and slided by the tighter more difficult generation that packless plastic packaging material coated and falling pin with the size that varies in size up and down of a Ji Dao.
(4) description of drawings
Fig. 1 is a plurality of base island embedded type multi-turn leaded package schematic diagrames of the utility model.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was for formed insulation pin schematic diagram in the past.
Fig. 4 pin figure for what formed in the past.
Reference numeral among the figure:
The base island 1, pin 2, no filler plastic packaging material 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material 9 is arranged.
(5) embodiment
Referring to Fig. 1~2, Fig. 1 is a plurality of base island embedded type multi-turn leaded package schematic diagrames of the utility model.Fig. 2 is the vertical view of Fig. 1.By Fig. 1 and Fig. 2 as can be seen, the a plurality of base island embedded type multi-turn leaded packages of the utility model, comprise basic island 1, pin 2, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material 9 is arranged, front at described basic island 1 and pin 2 is provided with the first metal layer 4, be provided with second metal level 5 at the back side of described pin 2, be provided with chip 7 in 1 front, basic island by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material 9, described basic island 1 is provided with a plurality of, pin 2 is provided with multi-turn, in described pin 2 peripheries, 1 back side, base island, zone between base island 1 and the basic island 1, zone between base island 1 and the pin 2 and the zone between pin 2 and the pin 2 are equipped with packless plastic packaging material 3, described packless plastic packaging material 3 is with periphery, pin 2 bottom, 1 back side, base island, the bottom of base 1 back side, island and pin 2 and pin 2 link into an integrated entity with the bottom of pin 2, and make described pin 2 back side sizes less than pin 2 positive sizes, form up big and down small pin configuration.
Claims (1)
1. a plurality of base island embedded type multi-turn leaded package, comprise Ji Dao (1), pin (2), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, front at described Ji Dao (1) and pin (2) is provided with the first metal layer (4), be provided with second metal level (5) at the back side of described pin (2), be provided with chip (7) in Ji Dao (1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), it is characterized in that: described Ji Dao (1) is provided with a plurality of, pin (2) is provided with multi-turn, in described pin (2) periphery, Ji Dao (1) back side, zone between Ji Dao (1) and the Ji Dao (1), zone between zone between Ji Dao (1) and the pin (2) and pin (2) and the pin (2) is equipped with packless plastic packaging material (3), described packless plastic packaging material (3) is with pin (2) periphery, bottom, Ji Dao (1) back side, the bottom of Ji Dao (1) back side and pin (2) and pin (2) link into an integrated entity with the bottom of pin (2), and make described pin (2) back side size less than the positive size of pin (2), form up big and down small pin configuration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201020177733XU CN201681867U (en) | 2010-04-26 | 2010-04-26 | Multi-base island embedded type multi-turn pin encapsulation structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201020177733XU CN201681867U (en) | 2010-04-26 | 2010-04-26 | Multi-base island embedded type multi-turn pin encapsulation structure |
Publications (1)
Publication Number | Publication Date |
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CN201681867U true CN201681867U (en) | 2010-12-22 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201020177733XU Expired - Lifetime CN201681867U (en) | 2010-04-26 | 2010-04-26 | Multi-base island embedded type multi-turn pin encapsulation structure |
Country Status (1)
Country | Link |
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CN (1) | CN201681867U (en) |
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2010
- 2010-04-26 CN CN201020177733XU patent/CN201681867U/en not_active Expired - Lifetime
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20101222 |