CN201247774Y - Packaging structure for high-power multi-chip - Google Patents

Packaging structure for high-power multi-chip Download PDF

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Publication number
CN201247774Y
CN201247774Y CNU2008201636584U CN200820163658U CN201247774Y CN 201247774 Y CN201247774 Y CN 201247774Y CN U2008201636584 U CNU2008201636584 U CN U2008201636584U CN 200820163658 U CN200820163658 U CN 200820163658U CN 201247774 Y CN201247774 Y CN 201247774Y
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CN
China
Prior art keywords
chip
pins
bearing plate
pin
integrated circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNU2008201636584U
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Chinese (zh)
Inventor
张永夫
林刚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZHEJIANG HUAYUE CORE LOADING ELECTRONIC CO Ltd
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ZHEJIANG HUAYUE CORE LOADING ELECTRONIC CO Ltd
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Publication date
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Priority to CNU2008201636584U priority Critical patent/CN201247774Y/en
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Publication of CN201247774Y publication Critical patent/CN201247774Y/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

The utility model discloses a high-power multi-chip package structure which belongs to the technical field of semi-conductor package structures. The high-power multi-chip package structure comprises a lead frame with two sides provided with a plurality of pins, and the two sides at the center of the lead frame are respectively and at least provided with one chip loading board. Each chip loading board is connected with corresponding two pins at the same side, the two pins connected with each chip loading board are connected in pairs to form radiation pins, and the pins and the radiation pins are respectively provided with positioning holes. The utility model packages a plurality of high-power elements in a mixed mode, has high radiation efficiency, simple package processing technology, and is helpful for improving the product reliability and the rate of finished products.

Description

A kind of multi-chip encapsulation construction of large power
Technical field
The utility model discloses a kind of multi-chip encapsulation construction of large power, belong to the semiconductor package technical field.
Background technology
Further lifting along with integrated circuit microminiaturization and integrated level, the encapsulating structure of multicore sheet occurs more and more, but all be the mode of piling up generally or on a fritter PCB, carry out the system integration, these methods have higher requirements with equipment to making, and then bring rate of finished products and cost problem, there is the integrated circuit (IC) products of very strong heat radiation requirement all the more so to high-power especially.Tend to because the heating of powerful device work chip current is excessive, can not in time externally dispel the heat and cause losing efficacy.This also is a difficult point place of high power device miniature multicore sheet hybrid package.
The utility model content
The utility model provides a kind of can satisfy the multi-chip encapsulation construction of large power that different high power device chip hybrid-package electric heating characteristics (big electric current, good heat dissipation effect) require.
To achieve these goals, the technical scheme that the utility model adopted is:
A kind of multi-chip encapsulation construction of large power comprises
Both sides are provided with the lead frame of a plurality of pins, these both sides, lead frame center at least respectively are provided with a chip bearing plate, each chip bearing plate links to each other respectively with corresponding two pins of side position, and two pins that link to each other with each chip bearing plate link to each other in twos, form the heat radiation pin, and be equipped with location hole on pin and the heat radiation pin;
At least two kinds of different integrated circuit (IC) chip are loaded in respectively on the relevant chip loading plate;
A plurality of leads is respectively with each described integrated circuit (IC) chip and each corresponding around it described pin electrical connection;
Packing colloid have an end face and a plurality of side of being extended by described top edge at least downwards, and this packing colloid coats the part of each described chip bearing plate, each described integrated circuit (IC) chip, each described lead-in wire and each described pin.
As the further setting of such scheme, described lead frame is respectively equipped with four pins along both sides, circuit center, and two pins in the middle of every side connect a chip bearing plate, and two pins that link to each other with each chip bearing plate link to each other in twos, forms the heat radiation pin.
Be equipped with circular location hole on four pins on the described lead frame residue side, be equipped with square location aperture and square location macropore on two heat radiation pins, during plastic packaging, circular location hole, the square location packed colloid of aperture coat fully, square location macropore then is that part coats, and part exposes.
It is that raw material is made that described packing colloid is selected epoxy resin for use.
Described integrated circuit (IC) chip is fixed on the chip bearing plate by elargol and insulating cement adhesion.
Have on the described integrated circuit (IC) chip and the corresponding functional definition contact of each described pin.
After adopting such scheme, the utility model chip bearing plate is set as at least two, so that carry out a plurality of integrated circuit (IC) chip hybrid package, and the chip bearing plate is set as and links to each other with the corresponding two pins of side position, and two pins fuses into the heat radiation pin, design helps the heat that high-power chip (integrated circuit (IC) chip) work is produced is in time conducted like this, guarantees normal working temperature.
In a word, the utility model has the advantages that: can carry out hybrid package to a plurality of high power device chips, the radiating efficiency height, encapsulation process technology is simple, helps improving reliability of products and rate of finished products.
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is the three-dimensional appearance schematic diagram of the utility model multi-chip encapsulation construction of large power;
Fig. 2 is the perspective schematic perspective view of the intraware of Fig. 1;
Wherein, description of reference numerals is as follows:
10 lead frames, 11 pins, 12 heat radiation pins
13 chip bearing plates, 14 circular location hole 15 square location apertures
16 square location macropore 17 location holes
20 integrated circuit (IC) chip, 21 contacts
30 packing colloids, 31 end faces, 32 sides
40 lead-in wires
Embodiment
For making the purpose of this utility model, structure, feature and function thereof there are further understanding, now cooperate embodiment to be described in detail as follows.
For under the prerequisite of functional definition that does not influence the standard integrated circuit (IC) chip and geometric shape, make they can hybrid package together, and meet that industry is to the standard of Chip Packaging now, the utility model provides a kind of multi-chip encapsulation construction of large power.It has a plurality of loading plates, and each loading plate all has pin to link to each other to dispel the heat, can improve the radiating efficiency of integrated circuit, product reliability is improved, to reduce manufacturing cost, to improve the product yield.
As shown in Figure 1 and Figure 2, it is the schematic diagram according to a kind of multi-chip encapsulation construction of large power of the utility model one preferred embodiment, comprises integrated circuit (IC) chip 20, a plurality of leads 40, the packing colloid 30 of lead frame 10, two different models.
Lead frame 10 is respectively equipped with four pins 11 along both sides, circuit center, the chip bearing plate 13 of two pins, 11 common connections in the middle of every side, and two pins 11 that link to each other with each chip bearing plate 13 link to each other formation heat radiation pin 12 in twos.The design of heat radiation pin 12 helps the heat that high-power chip work is produced is in time conducted, and guarantees normal working temperature; And two chip bearing plates 13 are established relatively in the circuit centre, help shortening the signal pipeline, improve response speed.
Integrated circuit (IC) chip 20 of carrying on each chip bearing plate 13, integrated circuit (IC) chip 20 is fixed on the chip bearing plate 13 with elargol and insulating cement adhesion, and have a plurality of functional definition contacts 21 on the integrated circuit (IC) chip 20, wherein each contact 21 has different separately functional definition and corresponding with specific pin 11 respectively.Four pins, 11 use lead-in wires, 40 modes with welding on the lead frame 10 residue sides are electrically connected on each contact 21 on the integrated circuit (IC) chip 20, transfer to the external world with the particular electrical circuit signal with integrated circuit (IC) chip 20 by pin 11.
Packing colloid 30 is by hot melt epoxy resin casting; and have an end face 31 and a plurality of side 32 of extending downwards by end face 31 edges; in order to coating chip loading plate 13, integrated circuit (IC) chip 20, respectively go between 40 and the part of each pin 11, heat radiation pin 12, to protect each element of this encapsulating structure inside.
For can be when the plastic packaging with pin 11 and 12 firm being fixed in the packing colloid 30 of heat radiation pin, be equipped with location hole 17 on pin 11 and the heat radiation pin 12, concrete structure is as follows:
Be equipped with circular location hole 14 on four pins 11 on the lead frame 10 residue sides, be equipped with square location aperture 15 and square location macropore 16 on two heat radiation pins 12, during plastic packaging, circular location hole 14, square location aperture 15 packed colloids 30 coat fully, 16 of square location macropores are that part coats, and part exposes.
A kind of multi-chip encapsulation construction of large power of the utility model has a plurality of chip bearing plates 13, not only encapsulating structure itself meets the standard of existing industry for the integrated circuit (IC) chip encapsulation, can carry out hybrid package to a plurality of high power device work chips, reaching the requirement of high integration microminiaturization, and owing to make handling ease relatively, good heat dissipation effect, make the product reliability height of this encapsulating structure, the life-span is long, and manufacturing process is simple, the rate of finished products height can reduce manufacturing cost greatly.
Though the utility model with aforesaid example explanation as above, but be not that in the utility model the foregoing description, chip bearing plate 13 is two in order to qualification the utility model, but in actual applications also can be, and be provided with for relative mode in the middle of the circuit more than two.In not breaking away from spiritual scope of the present utility model, change of being done and retouching all belong to scope of patent protection of the present utility model.Please refer to appended claims about the protection range that the utility model defined.

Claims (6)

1, a kind of multi-chip encapsulation construction of large power is characterized in that:
Comprise that both sides are provided with the lead frame of a plurality of pins (11) (10), this lead frame (10) both sides, center at least respectively are provided with a chip bearing plate (13), each chip bearing plate (13) links to each other respectively with corresponding two pins of side position (11), and two pins (11) that link to each other with each chip bearing plate (13) link to each other in twos, form heat radiation pin (12), and be equipped with location hole (17) on pin (11) and the heat radiation pin (12);
At least two kinds of different integrated circuit (IC) chip (20) are loaded in respectively on the relevant chip loading plate (13);
A plurality of leads (40) is respectively with each described integrated circuit (IC) chip (20) and each corresponding around it described pin (11) electrical connection;
Packing colloid (30), at least have an end face (31) and a plurality of side (32) of extending downwards, and this packing colloid (30) coats the part of each described chip bearing plate (13), each described integrated circuit (IC) chip (20), each described lead-in wire (40) and each described pin (11) by described end face (31) edge.
2, a kind of multi-chip encapsulation construction of large power as claimed in claim 1, it is characterized in that: described lead frame (10) is respectively equipped with four pins (11) along both sides, circuit center, two pins (11) in the middle of every side connect a chip bearing plate (13) jointly, two pins (11) that link to each other with each chip bearing plate (13) link to each other in twos, form heat radiation pin (12).
3, a kind of multi-chip encapsulation construction of large power as claimed in claim 2, it is characterized in that: be equipped with circular location hole (14) on four pins (11) on described lead frame (10) the residue side, be equipped with square location aperture (15) and square location macropore (16) on two heat radiation pins (12), during plastic packaging, circular location hole (14), the packed colloid of square location aperture (15) (30) coat fully, square location macropore (16) then is that part coats, and part exposes.
4, a kind of multi-chip encapsulation construction of large power as claimed in claim 1 is characterized in that: it is that raw material is made that described packing colloid (30) is selected epoxy resin for use.
5, a kind of multi-chip encapsulation construction of large power as claimed in claim 1 is characterized in that: described integrated circuit (IC) chip (20) is fixed on the chip bearing plate (13) by elargol and insulating cement adhesion.
6, a kind of multi-chip encapsulation construction of large power as claimed in claim 1 is characterized in that: have on the described integrated circuit (IC) chip (20) and the corresponding functional definition contact of each described pin (11) (21).
CNU2008201636584U 2008-09-04 2008-09-04 Packaging structure for high-power multi-chip Expired - Lifetime CN201247774Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2008201636584U CN201247774Y (en) 2008-09-04 2008-09-04 Packaging structure for high-power multi-chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2008201636584U CN201247774Y (en) 2008-09-04 2008-09-04 Packaging structure for high-power multi-chip

Publications (1)

Publication Number Publication Date
CN201247774Y true CN201247774Y (en) 2009-05-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2008201636584U Expired - Lifetime CN201247774Y (en) 2008-09-04 2008-09-04 Packaging structure for high-power multi-chip

Country Status (1)

Country Link
CN (1) CN201247774Y (en)

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GR01 Patent grant
AV01 Patent right actively abandoned

Effective date of abandoning: 20080904

AV01 Patent right actively abandoned

Effective date of abandoning: 20080904

C25 Abandonment of patent right or utility model to avoid double patenting