CN201017889Y

CN201017889Y - VDMOS, IGBT power device using PSG doping technique

Info

Publication number: CN201017889Y
Application number: CNU2007200673558U
Authority: CN
Inventors: 邵光平
Original assignee: SHANGHAI FUWA MICRO-ELECTRONICS Co Ltd
Current assignee: Jilin Sino Microelectronics Co Ltd
Priority date: 2007-02-14
Filing date: 2007-02-14
Publication date: 2008-02-06
Anticipated expiration: 2017-02-14

Abstract

The utility model relates to a VDMOS and IGBT power device adopting the PSG doping technology and the manufacturing process, which belongs to the microelectronic technical field. The utility model comprises a metal bottom layer, an N + substrate layer (P + substrate layer in a IGBT power device), a N - epitaxial layer, a P - zone, a P + zone, a N + zone, a thermal oxidation SiO <2> gate oxide layer, a polysilicon gate layer, a source gate isolated layer and a metal surface layer. The source gate isolated layer is acted by a phosphorosilicate glass PSG layer with the single layer form, to replace the combined structure form of the SiO <2> layer and the PSG layer in the existing technology, and the phosphorosilicate glass PSG layer acts as the doping source for generating the N + zone, the N + zone is formed with the phosphonium diffusing to silicium, therefore the processes as lithographic process in the production process is effectively reduced. The utility model does not only make for reducing the production cost, but also for improving the operational reliability of the VDMOS and IGBT power device greatly, and has a strong practicability and economical efficiency.

Description

Adopt VDMOS, the IGBT power device of PSG doping techniques

Technical field

The utility model relates to the semiconductor device in the microelectronics technology, particularly a kind of VDMOS, IGBT power device that adopts the PSG doping techniques.

Background technology

Existing VDMOS, IGBT power device are mainly by metal back layer, N+ substrate layer, N-epitaxial loayer, P-district, P+ district, N+ district, thermal oxidation SiO ₂Grid oxide layer, polycrystalline silicon grid layer, SiO ₂Illuvium, phosphorosilicate glass PSG illuvium and metal surface are formed.Fill the post of by metal surface that source electrode, metal back layer are filled the post of drain electrode, polycrystalline silicon grid layer is filled the post of grid, phosphorosilicate glass PSG layer and LPCVD SiO ₂The source gate spacer is filled the post of in layer combination, the source region by the P-district that is positioned at deep layer, in the middle of being positioned at the P+ district and the annular N+ district that is positioned at periphery, P+ district constitute.

Its manufacturing process flow is mainly as follows:

(1) on the base material that constitutes by N+ substrate layer (being the P+ substrate layer in the IGBT power device) and N-epitaxial loayer, generates one deck grid oxide layer earlier and with method growth one deck polycrystalline silicon grid layer of LPCVD deposit in the mode of thermal oxidation;

(2) remove the SiO that covers on the scope of predetermined origin area with photoetching, dry etching method ₂Grid oxide layer and polycrystalline silicon grid layer, and after injecting boron on the N-layer that is concavity, exposure down thus, do annealing, knot processing, form darker, the wide P-district of coverage in the source region;

(3) the photoetching predetermined set is the annular region scope in N+ district in described P-district, and does annealing, knot processing after injecting phosphorus, forms the annular N+ district in source region;

(4) photoetching is positioned at all the other middle predetermined P+ area scopes of described annular N+ district, and does annealing, knot processing after injecting boron, forms the P+ district in the middle of being positioned at;

(5) at front, SiO by remaining polysilicon grid layer ₂The side of grid oxide layer and polycrystalline silicon grid layer links to each other with the following concavity plane that comprises N+ district, P+ district surface on the integral surface that forms with the method elder generation deposit of LPCVD or PECVD one deck SiO that grows ₂, after whole again deposit growth one deck PSG or BPSG, and then to the SiO on the middle position ₂Do photoetching with PSG or bpsg layer and burn into forms by SiO ₂The source, the gate spacer that constitute with PSG layer or bpsg layer;

(6) at last just, evaporation growing metal layer on the back side, make VDMOS or IGBT power device.

In the flow process of in this way making VDMOS, IGBT power device, adopted repeatedly photoetching and burn into to remove the property processing, operation is more loaded down with trivial details, particularly is being isolated into purpose, growth SiO with what realize grid and source ₂In the process of layer and PSG or bpsg layer, except that need are carried out a photoetching and corrosion process, the version that also has this separator, make the N+ district area of the VDMOS that in this way makes, IGBT power device bigger, make the emitter region area of parasitic NPN pipe also bigger, thereby cause the functional reliability of VDMOS, IGBT power device relatively poor.So, the VDMOS, the IGBT power device ubiquity that utilize prior art to produce cause product cost high because of the complexity of production process, because of structural volume and the functional reliability of owing rationally to cause influencing product, thereby all owing desirable aspect economy and the practicality.

Summary of the invention

The purpose of this utility model is that a kind of area in N+ district in the parasitic components of being convenient to dwindle among VDMOS, the IGBT will be provided, and the novelty that the emitter region area of parasitic NPN pipe is also dwindled thereupon, helps improving functional reliability and reduce cost of goods manufactured adopts VDMOS, the IGBT power device of PSG doping techniques.

The VDMOS of employing PSG doping techniques of the present utility model, IGBT power device are mainly by metal back layer, N+ substrate layer (being the P+ substrate layer in the IGBT power device), N-epitaxial loayer, P-district, P+ district, N+ district, thermal oxidation SiO ₂Grid oxide layer, polycrystalline silicon grid layer, source gate spacer and metal surface are formed.Fill the post of by metal surface that source electrode, metal back layer are filled the post of drain electrode, polycrystalline silicon grid layer is filled the post of grid, the source region by the P-district that is positioned at deep layer, be positioned at the P+ district on the middle part, top layer and be positioned at peripheral annular N+ district, P+ district and constitute.It is characterized in that: phosphorosilicate glass PSG layer is filled the post of the source gate spacer with the version of individual layer; The doped source of phosphorosilicate glass PSG floor when generating N+ district in the source region, by PSG floor height temperature is annealed, the knot processing, make phosphorus wherein in silicon, diffuse to form the N+ district.

The utility model adopts VDMOS, the IGBT power device manufacturing process flow of PSG doping techniques as follows:

(1) elder generation's mode with thermal oxidation on the base material that is made of N+ substrate layer and N-epitaxial loayer generates SiO ₂Grid oxide layer, again with the method growing polycrystalline silicon grid layer of deposit;

(2) remove the SiO that is positioned on the predetermined scope zone, source region with photoetching, dry etching method ₂Grid oxide layer and polycrystalline silicon grid layer, and do annealing, knot are handled behind injection boron on the N-layer that is concavity exposure down thus, darker, wide P-district in the formation source region;

(3) concavity N-laminar surface photoetching under being that is exposed is predefined for the central area in P+ district, and does annealing, knot processing after injecting boron, form P+ district more shallow in the middle of being positioned at, book;

(4) with LPCVD method deposit growth PSG floor on the integral surface that constitutes that links to each other by the front of remaining polysilicon grid floor and side, P-district and P+ district, and to be created on P-district and P+ district surperficial on the PSG floor do the removal processing of photoetching, dry etching;

(5) deposit is grown in the doped source when generating N+ district in the source region of PSG floor on the front of remaining polysilicon grid floor and the side, handles, phosphorus contained among the PSG is spread in silicon, form the N+ district of annular more shallow book through high annealing, knot;

(6) align, back side evaporation generates metal back layer and metal surface, makes the VDMOS power device.

The above is the manufacturing process of the utility model VDMOS power device, and for the manufacturing process flow of IGBT power device with it roughly the same, its difference is that the N+ substrate layer on the base material is replaced by the P+ substrate layer.

In addition, according to the technological requirement of the utility model product, the thickness of described polysilicon gate is generally 4000 dusts to 6000 dusts, and the thickness of the PSG of described LPCVD is generally more than 5000 dusts.

Adopt VDMOS, the IGBT power device of PSG doping techniques based on the utility model of above-mentioned design, owing to utilize the source gate spacer that in VDMOS, IGBT power device manufacture process, is provided with to fill the post of with the single layer structure form, replace in the prior art by SiO by phosphorosilicate glass PSG layer ₂The version of layer and PSG layer combination, and utilize this phosphorosilicate glass PSG floor as the doped source during the N+ district in the generation source region, thus saved SiO ₂The layer generation and to SiO ₂Layer carries out the operation of photoetching treatment, not only helped reducing production costs, simultaneously but also the N+ district area in the device parasitic among VDMOS, the IGBT is reduced, help increasing substantially the functional reliability of VDMOS, IGBT power device, thereby have tangible technical advance, remarkable economical and extremely strong practicality.

Description of drawings

Fig. 1 is the internal structure schematic diagram of utility model embodiment product;

The internal structure schematic diagram of Fig. 2 and the utility model related art product;

Fig. 3 is the process flow diagram of the utility model embodiment;

Fig. 4 is the manufacturing process flow diagram of the utility model embodiment.

Among the figure:

1. metal back layer 2.N+ substrate layer 3.N-epitaxial loayer 4.P-district

5.P+ district 6.N+ district 7.SiO ₂ Grid oxide layer 8. polycrystalline silicon grid layers

9. source gate spacer 10. metal surface 11.PSG layer 12.SiO ₂Layer

13. 14. positive 15. sides, source region scope zone

Embodiment

Below in conjunction with accompanying drawing and exemplary embodiments the utility model is further described.

In Fig. 1 and Fig. 2, the VDMOS of employing PSG doping techniques of the present utility model, IGBT power device are mainly by metal back layer 1, N+ substrate layer (being the P+ substrate layer in the IGBT power device) 2, N-epitaxial loayer 3, P-district 4, P+ district 5, N+ district 6, thermal oxidation SiO ₂ Grid oxide layer 7, polycrystalline silicon grid layer 8, source gate spacer 9 and metal surface 10 are formed.Filled the post of by metal surface 10 that source electrode, metal back layer 1 are filled the post of drain electrode, polycrystalline silicon grid layer 8 is filled the post of, the source region is made of the P-district 4 that is positioned at deep layer, the annular N+ district 6 that is positioned at the P+ district 5 in the middle of the top layer and is positioned at 5 peripheries, P+ district.Wherein: source gate spacer 9 is by phosphorosilicate glass PSG layer 11 and SiO in the prior art ₂Layer 12 combines, and source gate spacer 9 is filled the post of with the version of individual layer by phosphorosilicate glass PSG layer 11 in the utility model; In addition, in the utility model, phosphorosilicate glass PSG floor 11 go back the doped source of double as when generating N+ district in the source region, to phosphorosilicate glass PSG floor 11 do annealing, knot is handled, and makes in the silicon of wherein contained phosphorus in predetermined N+ district 6 annular regions to spread, and forms the N+ district 6 of annular more shallow book.

In Fig. 3 and Fig. 4, the utility model adopts the technological process of PSG doping techniques manufacturing VDMOS power device as follows:

(1) earlier on the base material that constitutes by N+ substrate layer 2 and N-epitaxial loayer 3 with the mode of thermal oxidation generate SiO2 grid oxide layer 7, again with the method growing polycrystalline silicon grid layer 8 of deposit;

(2) remove the SiO that is scheduled on the scope zone, source region 13 with photoetching, dry etching method ₂ Grid oxide layer 7 and polycrystalline silicon grid layer 8, and do annealing, knot are handled behind injection boron on the N-layer that is concavity exposure down thus, darker, thick P-district 4 in the formation source region;

(3) photoetching is done in the central area in predetermined P+ district 5 on the concavity N-floor under being that is exposed, and do annealing, knot are handled behind the injection boron, form the P+ district 5 that is positioned at the middle more shallow book in source region;

(4), and P-district 4 and P+ district 5 lip-deep PSG floor 11 are done the removal processing of photoetching, dry etching with LPCVD method deposit growth PSG floor 11 on the integral surface that constitutes that links to each other by the front 14 of remaining polysilicon grid floor 8 and side 15, P-district 4 and P+ district 5;

(5) deposit is grown in the front 14 of remaining polysilicon grid floor 8 and the PSG floor 11 on the side 15 doped source when generating N+ district in the source region, by phosphorosilicate glass PSG layer 11 being done annealing, knot processing, wherein contained phosphorus is spread in silicon, form the N+ district 6 of the more shallow book of annular;

(6) align, back side evaporation generates metal back layer 1 and metal surface 10, makes the VDMOS power device.

More than be the manufacturing process of VDMOS power device in the utility model, for the manufacturing process flow of IGBT power device with it roughly the same, its difference is that the N+ substrate on the base material is replaced by the P+ substrate.

In addition, described PSG layer 11 effect that is arranged between metal surface 10 and the polycrystalline silicon grid layer 8, fills the post of source gate spacer 9; The thickness of described polycrystalline silicon grid layer 8 generally is controlled at 4000 dusts to 6000 dusts, and the thickness of the PSG layer 11 of LPCVD is generally more than 5000 dusts; The N+ district 6 in described source region be by the PSG floor 11 of LPCVD by to the regional photoetching in predetermined N+ district, dry etching after heating anneal diffuses to form the phosphorus in the PSG floor 11 in P-district 4.

Claims

1. VDMOS, IGBT power device that adopts the PSG doping techniques is by metal back layer (1), N+ substrate layer (2) (being the P+ substrate layer in the IGBT power device), N-epitaxial loayer (3), P-district (4), P+ district (5), N+ district (6), thermal oxidation SiO ₂Grid oxide layer (7), polycrystalline silicon grid layer (8), source gate spacer (9) and thermal oxidation SiO ₂Grid oxide layer (7) metal surface (10) is formed, and it is characterized in that source gate spacer (9) filled the post of with the version of individual layer by phosphorosilicate glass PSG layer (11).