CN101017849A - A compound bar, bar source self-separating VDMOS, 1GBT power unit and its making technology - Google Patents
A compound bar, bar source self-separating VDMOS, 1GBT power unit and its making technology Download PDFInfo
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- CN101017849A CN101017849A CN 200710037558 CN200710037558A CN101017849A CN 101017849 A CN101017849 A CN 101017849A CN 200710037558 CN200710037558 CN 200710037558 CN 200710037558 A CN200710037558 A CN 200710037558A CN 101017849 A CN101017849 A CN 101017849A
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Abstract
The invention relates to VDMOS and IGBT power device with composite grid and self-isolated grid-source. Wherein, it sets a thermal-oxidized SiO2 grid between source and multicrystal Si grid, and adds a Si3N4 layer to form a composite grid together with last grid to increase grid yield. Compared with prior art, this invention increase can fast shield grid window and generate only -very-thin oxidation layer to simplify manufacture technology, and needs low cost.
Description
Technical field
The present invention relates to the production process of semiconductor device technology in the microelectronics technology, particularly a kind of composite grid, grid are derived from isolates VDMOS, IGBT power device and manufacturing process thereof.
Background technology
Existing VDMOS, IGBT power device are mainly by metal back layer, N+ substrate, silicon N-epitaxial loayer, P-district, P+ district, N+ district, thermal oxidation SiO
2Grid oxide layer, polysilicon layer, SiO
2Illuvium, phosphorosilicate glass PSG illuvium and metal surface are formed.Fill the post of by metal surface that source electrode, metal back layer are filled the post of drain electrode, polysilicon layer is filled the post of grid, phosphorosilicate glass PSG layer and LPCVD SiO
2Layer is filled the post of separator, the source region by the P-district that is positioned at deep layer, in the middle of being positioned at the P+ district and the annular N+ district that is positioned at periphery, P+ district constitute.
Its manufacturing process flow is as follows:
(1) on the base material that constitutes by N-layer and N+ substrate layer (being the P+ substrate layer), generates one deck grid oxide layer earlier and with method growth one deck polysilicon of LPCVD deposit in IGBT with the method for thermal oxidation;
(2) remove grid oxide layer and polysilicon layer on the predetermined scope zone, source region with photoetching, dry etching method, and do annealing behind the B Implanted on the N-layer of thus exposure in a concave shape, knot is processed, and forms darker, thick P-district in the source region;
(3) the photoetching predetermined set is the annular region in N+ district in the P-district, and does annealing, knot processing after injecting phosphorus, forms the N+ district of annular;
(4) all the other the predetermined P-districts in the middle of photoetching is positioned at, and do annealing, knot are handled behind the injection boron, form to be positioned at middle P+ district;
The side of the concave shape plane that (5) consists of on the surface by N+ district, P+ district, the upper surface of remaining polysilicon and grid oxide layer, polysilicon layer links to each other on the integral surface that forms with the deposit growth one deck SiO of method elder generation of LPCVD or PECVD
2, after more whole deposit growth one deck PSG or BPSG, and then to the SiO on the middle position
2Do photoetching and corrosion treatment with PSG or bpsg layer, form by SiO
2Layer and PSG or bpsg layer consist of the separation layer of source, grid;
(6) at last just, back side evaporation growing metal layer, make VDMOS or IGBT power device.
In the flow process of in this way making VDMOS, IGBT power device, because at growth SiO
2All need carry out a photoetching and corrosion process when forming separation layer behind layer and PSG or the bpsg layer, could realize the isolation in grid and source.The version of this pair of separator, make the N+ district area of the VDMOS that in this way makes, IGBT power device bigger, make the emitter region area of parasitic NPN pipe also bigger, and the version of this separator, because process relation, grid and source short circuit take place easily, influence the situation of working life, except that the functional reliability that causes VDMOS, IGBT power device is relatively poor, also high because of the many complexity product costs of production process, thereby economy and practicality are all relatively poor.
Summary of the invention
The objective of the invention is to provide a kind of area in N+ district in the parasitic components of being convenient to dwindle in VDMOS, the IGBT power device, the novel composite grid, the grid that the emitter region area of parasitic NPN pipe is also dwindled thereupon, help improving functional reliability and reduce cost of goods manufactured are derived from isolates VDMOS, IGBT power device and manufacturing process thereof.
Composite grid of the present invention, grid are derived from isolates VDMOS, IGBT power device mainly by metal back layer, N+ substrate layer (being the P+ substrate layer), N-epitaxial loayer, P-district, P+ district, N+ district, thermal oxidation SiO in IGBT
2Grid oxide layer, polycrystalline silicon grid layer, source gate spacer and metal surface are formed.Filled the post of by metal surface that source electrode, metal back layer are filled the post of drain electrode, polycrystalline silicon grid layer is filled the post of grid, the source region is made of the P-district that is positioned at deep layer, the annular N+ district that is positioned at the P+ district in the middle of the top layer and is positioned at periphery, P+ district.It is characterized in that between source region and polycrystalline silicon grid layer except being provided with thermal oxide SiO
2Outside the grid oxide layer, also increase is provided with and has the Si that oxidation rate is slow, shield the source region window function
3N
4Layer.
It is as follows that the present invention makes the technological process of VDMOS power device:
(1) at first on the base material that is consisted of by N+ substrate layer (being the P+ substrate layer in IGBT) and N-epitaxial loayer the method with thermal oxide generate one deck SiO
2Grid oxide layer and at SiO
2On the grid oxide layer with the method for deposit growth one deck Si
3N
4, use the method for deposit at Si again
3N
4Generate one deck polycrystalline silicon grid layer on the layer;
(2) remove polycrystalline silicon grid layer on the predetermined scope zone, source region with photoetching, dry etching method, and do annealing behind the B Implanted in the scope zone, predetermined source region thus in a concave shape, knot is processed, and forms darker, thick P-district in the source region;
(3) to do annealing behind the central area photoetching in predetermined P+ district in the source region and the B Implanted, knot is processed, and forms the P+ district that is positioned at middle more shallow book;
(4) the predetermined N+ district annular region of photoetching, and do annealing, knot processing after injecting phosphorus, form the N+ district of annular;
(5) at front and side and the Si after etching by remaining polysilicon grid layer
3N
4Generate the thicker SiO that is positioned on polycrystalline silicon grid layer front and the side with thermal oxidation process on the continuous integral surface that consists of in layer surface
2Separation layer and be positioned in the middle of Si
3N
4The lip-deep thinner SiO of layer
2Separation layer is then to the SiO on the integral surface
2Separation layer is made the large tracts of land dry etching and is processed, and makes to be positioned at middle Si
3N
4The lip-deep thinner SiO of layer
2Separation layer is completely removed, and is positioned at the thicker SiO on polycrystalline silicon grid layer front and the side
2Though the separation layer part is removed, but still keep thicker state;
(6) to Si residual in the active area regions scope
3N
4Layer and SiO
2Layer is done the removal processing of dry etching or is removed, exposes the source region by the method in conjunction with employing dry etching and wet etching;
(7) just, back side evaporation generates metal back layer and metal surface, makes the VDMOS power device.
Be the manufacturing process of VDMOS power device as mentioned above, for the manufacturing process flow of IGBT power device with it roughly the same, its difference is that the N+ substrate layer on the base material is replaced by the P+ substrate layer.
In addition, according to technology of the present invention, described SiO
2The thickness of grid oxide layer is generally 300 dusts to 800 dusts, described Si
3N
4The thickness of layer is generally 500 dusts to 1000 dusts, and the thickness of the described polycrystalline silicon grid layer except thermal oxide layer is generally 4000 dusts to 6000 dusts, the thermal oxide layer on the described polycrystalline silicon grid layer, i.e. SiO
2The thickness of separation layer is generally 3000 dusts to 8000 dusts; SiO between described source, the grid
2Separation layer is that the surface heat oxidation by polycrystalline silicon grid layer realizes; The structure of grid is by Si in the power device
3N
4Layer adds SiO
2The composite grid version that layer consists of; Residual Si on the surface, source region
3N
4Add SiO
2Can add the wet method erosion removal by dry etching or by dry etching.
Composite grid of the present invention, grid based on above-mentioned design are derived from isolation VDMOS, IGBT power device and manufacturing process thereof, owing to adopt the technology that directly thermal oxidation generates on the polycrystalline silicon grid layer surface and utilize Si at the separation layer between source, the grid
3N
4Oxidation rate slower more than 10 times than the oxidation rate of polysilicon, can Rapid shielding grid region window and on self surface, can only generate the characteristics of the as thin as a wafer oxide layer of being convenient to remove, both simplified manufacturing process, realized that again grid are derived from isolation, simultaneously Si
3N
4Layer directly is created on the grid oxide layer, has consisted of composite grid, has both helped to strengthen the yield rate of grid, helps again to guarantee in the situation of effectively simplifying working process the generation of separation layer.Compare with the manufacturing VDMOS of prior art, the technology of IGBT power device, omitted photo-mask process one, obviously have simple in structure and science, easily manufactured and cost is low and the easy plurality of advantages such as assurance of product quality, thereby have tangible technical advance, remarkable economical and extremely strong practicality.
Description of drawings
Fig. 1 is the internal structure schematic diagram of embodiment of the invention product;
The internal structure schematic diagram of Fig. 2 prior art products related to the present invention;
Fig. 3 is the process flow diagram of the embodiment of the invention;
Fig. 4 is the manufacturing process flow diagram of the embodiment of the invention.
Among the figure:
1. metal back layer 2.N+ substrate layer 3.N-epitaxial loayer 4.P-district
5.P+ district 6.N+ district 7.SiO
2 Grid oxide layer 8. polycrystalline silicon grid layers
9. source gate spacer 10. metal surface 11.Si
3N
4Layer 12.SiO
2Separation layer
13. active area regions scope 14. positive 15. sides
Embodiment
Below in conjunction with accompanying drawing and exemplary embodiments the present invention is further described.
In Fig. 1 and Fig. 2, composite grid of the present invention, grid are derived from isolates VDMOS, IGBT power device mainly by metal back layer 1, N+ substrate layer (being the P+ substrate layer) 2, N-epitaxial loayer 3, P-district 4, P+ district 5, N+ district 6, thermal oxidation SiO in IGBT
2 Grid oxide layer 7, polycrystalline silicon grid layer 8, source gate spacer 9 and metal surface 10 are formed.Filled the post of by metal surface 10 that source electrode, metal back layer 1 are filled the post of drain electrode, polycrystalline silicon grid layer 8 is filled the post of grid, the source region is made of with the annular N+ district 6 that is positioned at 5 peripheries, P+ district the P+ district 5 that the P-district 4 that is positioned at deep layer is positioned in the middle of the top layer.It is characterized in that between source region and polycrystalline silicon grid layer 8 except being provided with thermal oxide SiO
2Outside the grid oxide layer 7, also increase is provided with Si
3N
4Layer 11, the SiO that source gate spacer 9 is generated by the oxidation of polycrystalline silicon grid layer surface heat
2Separation layer 12 is filled the post of.
In Fig. 3 and Fig. 4, it is as follows that the present invention makes the technological process of VDMOS IGBT power device:
(1) at first on the base material that is consisted of by N+ substrate layer (being the P+ substrate layer in IGBT) 2 and N-epitaxial loayer 3 method with thermal oxide generate one deck SiO
2 Grid oxide layer 7 and at SiO
2On the grid oxide layer 7 with the method for deposit growth one deck Si
3N
4The layer 11, use the method for deposit at Si again
3N
4Generate one deck polycrystalline silicon grid layer 8 on the layer 11;
(2) remove polycrystalline silicon grid layer 8 on the predetermined origin area scope 13 with photoetching, dry etching method, and do annealing behind scope zone, the predetermined source region 13 interior B Implanteds thus in a concave shape, knot is processed, and forms darker, thick P-district 4 in the source region;
(3) to do annealing behind the central area photoetching in predetermined P+ district 5 in the source region and the B Implanted, knot is processed, and forms the P+ district 5 that is positioned at middle more shallow book;
(4) annular region in the predetermined N+ district 6 of photoetching, and inject do annealing behind the phosphorus, knot is handled, and forms annular N+ district 6;
(5) at front 14 and side 15 and the Si after etching by remaining polysilicon grid layer 8
3N
4Generate the thicker SiO that is positioned on polycrystalline silicon grid layer 8 positive 14 and the side 15 with thermal oxidation process on the continuous integral surface that consists of in layer 11 surface
2Separation layer 12 and be positioned in the middle of Si
3N
4Layer 11 lip-deep thinner SiO
2Separation layer 12 is then to the SiO on the integral surface
2Separation layer 12 is made the large tracts of land dry etching and is processed, and makes to be positioned at middle Si
3N
4Layer 11 lip-deep thinner SiO
2Separation layer 12 is completely removed, and is positioned at the front 14 of polycrystalline silicon grid layer 8 and the thicker SiO on the side 15
2Though separation layer 12 parts are removed, but still keep thicker state;
(6) to active area regions scope 13 interior residual Si
3N
4Layer 11 and SiO
2 Grid oxide layer 7 is done the removal processing of dry etching, or in conjunction with adopting dry etching and wet etching method to remove, exposes the source region;
(7) align, back side evaporation generates metal back layer 1 and metal surface 10, makes VDMOS (IGBT) power device.
In addition, according to technology of the present invention, described SiO
2The thickness of grid oxide layer 7 is generally 300 dusts to 800 dusts, described Si
3N
4Layer 11 thickness is generally 500 dusts to 1000 dusts, and the thickness of described polycrystalline silicon grid layer 8 is generally 4000 dusts to 6000 dusts except thermal oxide layer, the thermal oxide layer on the described polycrystalline silicon grid layer, is SiO
2The thickness of separation layer 12 is generally 3000 dusts to 8000 dusts; Described SiO between source, grid
2Separation layer 12 is that the surface heat oxidation by polycrystalline silicon grid layer 8 realizes; The grid of power device are by Si
3N
4 Layer 11 adds SiO
2The composite grid version that grid oxide layer 7 consists of.
Claims (5)
1. a composite grid, grid are derived from isolation VDMOS, IGBT power device, by metal back layer (1), N+ substrate layer (2), N-epitaxial loayer (3), P-district (4), P+ district (5), N+ district (6), thermal oxide SiO
2Grid oxide layer (7), polycrystalline silicon grid layer (8), source gate spacer (9) and metal surface (10) form, and it is characterized in that: remove between source region and polycrystalline silicon grid layer (8) and be provided with thermal oxide SiO
2Outside the grid oxide layer (7), also increase is provided with Si
3N
4Layer (11); Source gate spacer (9) is by the SiO that is arranged between polycrystalline silicon grid layer (8) and the metal surface (10)
2Separation layer (12) is filled the post of.
2. composite grid according to claim 1, grid are derived from isolates VDMOS, IGBT power device, it is characterized in that described SiO
2Separator (12) is generated by polycrystalline silicon grid layer (8) surface heat oxidation.
3. composite grid according to claim 1, grid are derived from isolation VDMOS, IGBT power device, it is characterized in that described Si
3N
4Layer (11) is arranged on thermal oxide SiO by deposit generation method
2On the grid oxide layer (7).
4. a composite grid, grid are derived from the manufacturing process of isolating VDMOS, IGBT power device, it is characterized in that technological process is as follows:
(1) at first on the base material that is consisted of by N+ substrate layer (being the P+ substrate layer in IGBT) (1) and N-epitaxial loayer (2) method with thermal oxide generate one deck SiO
2Grid oxide layer (7) and at SiO
2The upper method growth one deck Si with deposit of grid oxide layer (7)
3N
4The layer (11), use the method for deposit at Si again
3N
4The upper one deck polycrystalline silicon grid layer (8) that generates of layer (11);
(2) remove polycrystalline silicon grid layer (8) on the predetermined origin area scope (13) with photoetching, dry etching method, and do annealing after in the scope zone, predetermined source region (13) that is concavity down thus, injecting boron, knot is handled, the P-district (4) in the formation source region;
(3) to do annealing behind the central area photoetching in predetermined P+ district (5) in the source region and the B Implanted, knot is processed, form to be positioned at middle P+ district (5);
(4) annular region in the predetermined N+ district (6) of photoetching, and inject do annealing behind the phosphorus, knot is processed, and forms annular N+ district (6);
(5) at front (14) and side (15) and the Si after etching by remaining polysilicon grid layer (8)
3N
4Generate the thicker SiO that is positioned on the polycrystalline silicon grid layer (8) positive (14) and side (15) with thermal oxidation process on the continuous integral surface that consists of in layer (11) surface
2Separation layer (12) and be positioned in the middle of Si
3N
4Layer (11) lip-deep thinner SiO
2Separation layer (12) is then to the SiO on the integral surface
2Separation layer (12) is made the large tracts of land dry etching and is processed, and makes to be positioned at middle Si
3N
4Layer (11) lip-deep thinner SiO
2Separation layer (12) is completely removed, and is positioned at the front (14) of polycrystalline silicon grid layer (8) and the thicker SiO on side (15)
2Separation layer (12) but still keeps thicker state though part is removed;
(6) to residual Si in the active area regions scope (13)
3N
4Layer (11) and SiO
2Grid oxide layer (7) is done the removal processing of dry etching, or in conjunction with adopting dry etching and wet etching method to remove, exposes the source region;
(7) align, back side evaporation generates metal back layer (1) and metal surface (10).
5. composite grid according to claim 4, grid are derived from the manufacturing process of isolating VDMOS, IGBT power device, it is characterized in that described SiO
2Separator (12) generates by polycrystalline silicon grid layer (8) surface heat oxidation.
Priority Applications (1)
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|---|---|---|---|
| CN 200710037558 CN101017849A (en) | 2007-02-14 | 2007-02-14 | A compound bar, bar source self-separating VDMOS, 1GBT power unit and its making technology |
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|---|---|---|---|
| CN 200710037558 CN101017849A (en) | 2007-02-14 | 2007-02-14 | A compound bar, bar source self-separating VDMOS, 1GBT power unit and its making technology |
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| CN100463124C (en) * | 2007-08-31 | 2009-02-18 | 江苏宏微科技有限公司 | Manufacturing method for enhancing primitive cell density of MOS grid control transistor |
| CN101752415A (en) * | 2008-12-03 | 2010-06-23 | 上海芯能电子科技有限公司 | Insulated gate bipolar transistor and method for producing same |
| CN105097540A (en) * | 2014-05-21 | 2015-11-25 | 北大方正集团有限公司 | Method for manufacturing planar VDMOS device |
| CN105990404A (en) * | 2015-01-30 | 2016-10-05 | 张家港意发功率半导体有限公司 | Anti-leakage power device and manufacturing method thereof |
| CN106033776A (en) * | 2015-03-18 | 2016-10-19 | 北大方正集团有限公司 | Manufacturing method of VDMOS device and the VDMOS device |
| CN106298928A (en) * | 2015-06-12 | 2017-01-04 | 北大方正集团有限公司 | VDMOS device and preparation method thereof |
| CN107180857A (en) * | 2016-03-10 | 2017-09-19 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| CN107431091A (en) * | 2015-03-30 | 2017-12-01 | 三菱电机株式会社 | Manufacturing silicon carbide semiconductor device and its manufacture method |
| CN107680933A (en) * | 2016-08-02 | 2018-02-09 | 比亚迪股份有限公司 | MOS type power device and its manufacture method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463124C (en) * | 2007-08-31 | 2009-02-18 | 江苏宏微科技有限公司 | Manufacturing method for enhancing primitive cell density of MOS grid control transistor |
| CN101752415A (en) * | 2008-12-03 | 2010-06-23 | 上海芯能电子科技有限公司 | Insulated gate bipolar transistor and method for producing same |
| CN105097540B (en) * | 2014-05-21 | 2018-07-24 | 北大方正集团有限公司 | The manufacturing method of plane VDMOS device |
| CN105097540A (en) * | 2014-05-21 | 2015-11-25 | 北大方正集团有限公司 | Method for manufacturing planar VDMOS device |
| CN105990404A (en) * | 2015-01-30 | 2016-10-05 | 张家港意发功率半导体有限公司 | Anti-leakage power device and manufacturing method thereof |
| CN106033776A (en) * | 2015-03-18 | 2016-10-19 | 北大方正集团有限公司 | Manufacturing method of VDMOS device and the VDMOS device |
| CN106033776B (en) * | 2015-03-18 | 2019-03-15 | 北大方正集团有限公司 | A kind of production method and VDMOS device of VDMOS device |
| CN107431091A (en) * | 2015-03-30 | 2017-12-01 | 三菱电机株式会社 | Manufacturing silicon carbide semiconductor device and its manufacture method |
| CN106298928A (en) * | 2015-06-12 | 2017-01-04 | 北大方正集团有限公司 | VDMOS device and preparation method thereof |
| CN106298928B (en) * | 2015-06-12 | 2019-10-15 | 北大方正集团有限公司 | VDMOS device and preparation method thereof |
| CN107180857A (en) * | 2016-03-10 | 2017-09-19 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| CN107180857B (en) * | 2016-03-10 | 2020-08-07 | 北大方正集团有限公司 | Manufacturing method of VDMOS device |
| CN107680933A (en) * | 2016-08-02 | 2018-02-09 | 比亚迪股份有限公司 | MOS type power device and its manufacture method |
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