CN1979833A - 半导体装置及其制造方法、电子部件、电路基板及电子机器 - Google Patents

半导体装置及其制造方法、电子部件、电路基板及电子机器 Download PDF

Info

Publication number
CN1979833A
CN1979833A CNA2006101637192A CN200610163719A CN1979833A CN 1979833 A CN1979833 A CN 1979833A CN A2006101637192 A CNA2006101637192 A CN A2006101637192A CN 200610163719 A CN200610163719 A CN 200610163719A CN 1979833 A CN1979833 A CN 1979833A
Authority
CN
China
Prior art keywords
semiconductor device
terminal
electrode
active face
plated film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101637192A
Other languages
English (en)
Other versions
CN1979833B (zh
Inventor
桥元伸晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1979833A publication Critical patent/CN1979833A/zh
Application granted granted Critical
Publication of CN1979833B publication Critical patent/CN1979833B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0236Shape of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02377Fan-in arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05024Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体装置,包含:具有能动面的半导体基板,在所述半导体基板的能动面的一侧设置的第1电极,与所述第1电极电连接、设置在所述能动面一侧的外部连接端子,设置在所述半导体基板的能动面的一侧的连接用端子;在所述外部连接端子和所述连接用端子的至少一方,形成镀金膜、镀银膜、镀钯膜中的某一个。

Description

半导体装置及其制造方法、电子部件、电路基板及电子机器
技术领域
本发明涉及半导体装置、半导体装置的制造方法、电子部件、电路基板及电子机器。
背景技术
为了更加高密度地安装半导体装置,裸芯片安装是理想的安装方式。
可是,裸芯片存在着难以确保质量及操作麻烦的问题。
因此,在现有技术中,开发出应用CSP(Chip Scale/Size Package)的半导体装置。
另外,特别是近几年来,如日本国再表01/071805号公报及特开2004-165415号公报所记载的那样,以晶片级形成CSP的、所谓“晶片级CSP(W-CSP)”引人注目。
在晶片级CSP中,以晶片单位形成进行了再布线的多个半导体元件(集成电路),然后切断晶片,将多个半导体元件单片化,得到半导体装置。
可是,在上述的半导体装置中,往往采取利用接合线及软钎焊球与外部结构体连接的形态。
作为这种接合线及软钎焊球所连接的电极,有的采用多层结构,即在电路图案的铜箔上形成镍层,再采用置换型电镀法、无电解还原型电镀法及电解电镀法等手法,在镍层上形成金层。
在这种半导体装置的制造过程中,在将半导体裸芯片固定到电路基板上的粘接剂的加热硬化的工序中,发现存在着下述问题。
粘接剂的加热硬化时,在被外加的热的作用下,镍从镍层的表层部脱离,扩散到其上层的金层内,成为镍化合物(主要是氢氧化镍)的形态,析出到金层的表面(暴露到大气中的部分)。
另外,如日本国特开2005-223088号公报所记载的那样,取代镀镍,使用镍-磷合金电镀时,往往在金层的表面会形成磷浓化层。
在这种状态的金层的表面,实施接合线及软钎焊时,在接合线与金层之间,以及在软钎焊球与金层之间,介有上述化合物,阻碍了两者的接合,接合强度变弱。
因此,作为确保足够的接合强度的方法,人们想到了薄薄地除去金层的表层部后,除去氢氧化镍成分等的方法。
可是,在上述这种现有技术中,存在着下述问题。
在电镀形成金层后,需要另行实施蚀刻洗涤工序等,导致制造效率下降。
发明内容
本发明就是针对上述情况研制的,目的在于提供不使制造效率下降、具有可以获得足够的接合强度的电极的半导体装置、半导体装置的制造方法、电子部件、电路基板及电子机器。
为了达到上述目的,本发明采用以下的结构。
本发明的半导体装置,包含:具有能动(能動)面的半导体基板,在所述半导体基板的能动面的一侧设置的第1电极,与所述第1电极电连接、设置在所述能动面一侧的外部连接端子,设置在所述半导体基板的能动面的一侧的连接用端子;在所述外部连接端子和所述连接用端子的至少一方,形成镀金膜、镀银膜、镀钯膜中的某一个。
这样,在本发明的半导体装置中,由于能够象使用镍层等时那样,抑制形成外部连接端子及连接用端子的金属的扩散,所以不需要另行实施薄薄地除去表层部的工序,能够防止制造效率下降。
另外,在发明中,因为在外部连接端子之外,另行设置连接用端子,所以使用该连接用端子,例如能够和其它的功能结构体(和与外部连接端子连接的功能结构体不同的功能结构体)进行机械性的连接及电性的连接。
这样,可以使半导体装置和功能结构体一体化后,形成电子部件,能够实现其小型化。
另外,在本发明的半导体装置中,最好采用无电解电镀法,形成所述镀金膜、所述镀银膜、所述镀钯膜中的某一个。
这样,在本发明中,不需要电解电镀用布线,能够实现高密度的布线。
另外,在本发明的半导体装置中,最好包含再配置布线,该再配置布线在所述能动面的一侧设置,将所述第1电极和所述外部连接端子电连接。
这样,能够自由(任意)设计外部连接端子的位置及其排列。
另外,在本发明的半导体装置中,最好包含第2电极,该第2电极在所述半导体基板的能动面的一侧设置,与所述连接用端子电连接。
这样,能够使用连接用端子,进行半导体装置的电性的处理。
另外,使用连接用端子,和其它的功能结构体进行电性的连接后,例如还可以将该半导体装置作为所述功能结构体的驱动用元件发挥作用。
另外,在本发明的半导体装置中,所述连接用端子,最好是为了进行电性的检查及调整的端子。
换言之,所述连接用端子,可以是旨在进行电性的检查及调整等维修保养的端子。
这样,例如可以使用所述连接用端子,进行电性的检查及修理等的半导体装置的功能的保证及调整。
另外,在本发明的半导体装置中,最好包含:连接所述外部连接端子和所述第1电极的布线;在所述半导体基板和所述外部连接端子之间设置的应力缓和层。
这样,通过布线做媒介,使第1电极和外部连接端子电性的连接后,能够在该半导体装置上形成再配置布线。
这样,能够扩大外部连接端子的大小及形状、配置等的自由度。
另外,由于设置了应力缓和层,所以能够提高介有外部连接端子的半导体装置和外部机器等的连接的可靠性。
另外,在本发明的半导体装置中,最好包含密封所述连接用端子的密封树脂。
如果将连接用端子用于电性的检查及调整后,利用密封树脂密封连接用端子,以后就不能使用该连接用端子进行调整等,从而能够提高检查及调整后的半导体装置的可靠性。
另外,如果将连接用端子用于和其它的部件之间的电性的连接后,利用密封树脂密封连接用端子,就能够防止该连接用端子的意外的短路,进而提高该连接用端子的连接强度。
另外,在本发明的半导体装置中,所述连接用端子最好柱状形成。
这样,柱状的连接用端子,例如作为使下层的导电部和上层的导电部导通的上下导通部件发挥作用后,能够提高半导体装置的再配置布线的自由度。
本发明的电子部件,包含:半导体装置,该半导体装置具有能动面的半导体基板,在所述半导体基板的能动面的一侧设置的第1电极,与所述第1电极电连接、设置在所述能动面一侧的外部连接端子,设置在所述半导体基板的能动面的一侧的连接用端子;功能结构体,该功能结构体在和所述半导体基板的能动面相反的一侧设置;导电连接部,该导电连接部将所述功能结构体和所述连接用端子电连接。
采用该电子部件后,由于利用连接用端子,用导电连接部连接半导体装置和功能结构体,所以半导体装置和功能结构体一体化后成为电子部件,能够实现小型化。
另外,在本发明的电子部件中,所述导电连接部,最好是接合线或软钎焊球。
这样,能够很简便地获得半导体装置和功能结构体的立体连接结构。
在本发明的电路基板中,安装着上文所述的电子部件。
在本发明的电子机器中,安装着上文所述的电子部件。
这样,采用本发明后,因为安装了实现小型化的电子机器,所以能够相应地实现高密度安装,能够获得实现了高功能化的电路基板及电子机器。
本发明的半导体装置的制造方法,包含:在所述半导体基板的能动面的一侧,形成第1电极的工序;在所述半导体基板的能动面的一侧,形成与所述第1电极电连接的外部连接端子的工序;在所述半导体基板的能动面的一侧,形成连接用端子的工序;在所述外部连接端子和所述连接用端子的至少一方,形成镀金膜、镀银膜、镀钯膜中的某一个的工序。
采用本发明后,就象使用了镍层等时那样,能够抑制形成外部连接端子及连接用端子的金属扩散。
这样,不需要另外设置薄薄地除去表层部的工序,能够防止制造效率的下降。
另外,在本发明的半导体装置的制造方法中,最好采用无电解电镀法,形成所述镀金膜、所述镀银膜、所述镀钯膜中的某一个。
这样,在本发明中,不需要电解电镀用布线,能够实现高密度的布线。
附图说明
图1是表示本发明的半导体装置的一种实施方式的侧剖面图。
图2是表示图1的半导体装置的示意图。
图3A~图3D是为了讲述图1的半导体装置的制造方法而绘制的图形。
图4是为了讲述图1的半导体装置的制造方法而绘制的立体图。
图5是表示本发明的电子部件的一种实施方式的立体图。
图6是表示本发明的半导体装置的其它实施方式的侧剖面图。
图7是表示搭载了本发明的电子部件的电子机器的一个示例的图形。
具体实施方式
下面,参照图1~图7,讲述本发明的半导体装置、半导体装置的制造方法、电子部件、电路基板及电子机器的实施方式。
[半导体装置]
图1、图2是表示本发明的半导体装置的一种实施方式的图形。在这些图中,符号1是晶片级CSP(W-CSP)结构的半导体装置。
此外,图1的侧剖面图,是图2的示意图中的A-A向视线剖面图。
如图1所示,半导体装置1,具备硅基板(半导体基板)10、第1电极11、外部连接端子12、连接用端子13。
在这里,在硅基板(半导体基板)10上,形成由晶体管及存储器元件等半导体元件构成的集成电路(未图示)。
第1电极11,设置在硅基板10的能动面10a的一侧、即形成集成电路的一侧。
外部连接端子12,与第1电极11电连接,设置在能动面10a的一侧。
连接用端子13,设置在能动面10a的一侧。
形成的第1电极11,与硅基板10的所述集成电路直接导通。
第1电极11,例如如图2所示,在矩形的硅基板10的周边部,排列多个地设置。
另外,在所述能动面10a上,如图1所示,形成成为钝化膜的第1绝缘层14。
在第1绝缘层14上,在所述第1电极11上形成开口部14a。
采用这种结构后,第1电极11在所述开口部14a内向外侧露出。
在本实施方式中,第1绝缘层14还在避开所述第1电极11及后文讲述的第2电极的位置,在硅基板10的中央部,形成由绝缘树脂构成的应力缓和层15。
另外,所述第1电极11在所述绝缘层14的开口部14a内,连接布线16。
布线16是为了进行所述集成电路的电极的再配置的元件。
如图2所示,布线16从配置在硅基板10的周边部的第1电极11起,向中央部一侧延伸,进而如图1所示,迂回到应力缓和层15上。
由于布线16是在硅基板10的第1电极11及后文讲述的外部连接端子12之间的布线,所以通常被称作“再配置布线”。
再配置布线,旨在使常有细微设计的硅基板10的电极11的位置与用户的插板安装使用的粗间距的外部连接端子12之间的物理位置错开配置,所以非常重要。
另外,在硅基板10的能动面10a的一侧,形成覆盖布线16、应力缓和层15及第1绝缘层14的第2绝缘层17。
第2绝缘层17,由焊剂-抗蚀剂构成,具有耐热性。
第2绝缘层17在所述应力缓和层15上形成的所述布线16上,形成开口部17a。
采用这种结构后,布线16在所述开口部17a内向外侧露出。
而且,在开口部17a内露出的布线16上,设置和外部连接端子12连接的连接部(连接端子)16a。
在连接部16a中,在铜膜的布线16上形成镀银膜21。
作为电镀膜21的种类,从镀银膜或镀钯膜中选择。
外部连接端子12,例如利用软钎焊球形成突台(バンプ)形状。
外部连接端子12,与用图1中的双点划线所示的作为外部机器的印刷布线板(电路基板)P电连接。
在这种结构下,在硅基板10上形成的集成电路(半导体元件),通过第1电极11、作为再配置布线的布线16、外部连接端子12媒介,与印刷布线板P电连接。
另外,如图2所示,在硅基板10上形成的所述集成电路中,在所述第1电极11以外,还形成第2电极18。
该第2电极18,例如作为输出旨在驱动和所述印刷布线板P不同的其它的功能结构体的输出信号的电极而使用,或者为了电性地进行所述集成电路的各种功能检查及功能调整等的维修而使用。
此外,在本实施方式中,和所述第1电极11的情况一样,第2电极18与再配置布线19连接。
再配置布线19,与向外部露出的所述连接用端子13连接。
连接用端子13,是为了形成电性或机械性连接的焊盘状的端子。
连接用端子13,特别作为第2电极18输出旨在驱动功能结构体的输出信号的端子而使用。
这时,本实施方式的半导体装置1,在和所述印刷布线板P不同的其它的功能结构体连接的结构中,可以适当利用连接用端子13。
另外,如前所述,所述第2电极18为了电性地进行所述集成电路的各种功能检查及功能调整而使用连接用端子13。
这时,连接用端子13与检查及调整用的探头等电连接(接触)。
这时,检查及调整用的探头同时与外部连接端子12连接,从而和连接用端子13协调,电性地进行各种功能检查及功能调整。
另外,连接用端子13例如在进行了所述集成电路的各种功能检查及功能调整后,如图1中的双点划线所示,被环氧树脂等密封树脂20密封。
这样,在功能检查及功能调整中被暂时性地使用的连接用端子,在除此以外的时候,就和外部环境隔断。
这样,能够利用连接用端子,杜绝半导体元件出现可靠性下降那样的状况。
另外,所述第1电极11、第2电极18及连接用端子13,能够由钛(Ti)、氮化钛(TiN)、铝(Al)、铜(Cu)或包含它们的合成等形成。
在本实施方式中,电极11、18用Al形成。
另外,在本实施方式中,连接用端子13作为上述电镀膜21,通过在Cu膜上形成镀银膜后形成。
进而,布线16、再配置布线19,可以由金(Au)、铜(Cu)、银(Ag)、钛(Ti)、钨(W)、钛钨(TiW)、氮化钛(TiN)、镍(Ni)、镍钒(NiV)、铬(Cr)、铝(Al)、钯(Pd)等形成。
在本实施方式中,布线16、再配置布线19在Cu膜上形成。
此外,作为这些布线16、再配置布线19的结构,既可以采用所述材料构成的单层结构,也可以采用组合多种的叠层结构。
另外,对于这些布线16、再配置布线19,通常用同一道工序形成,所以成为互相相同的材料。
另外,作为旨在形成第1绝缘层14及第2绝缘层17的树脂,例如使用聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、丙烯树脂、苯酚树脂、BCB(benzocyclobutene)及PBO(polybenzoxazole)等。
此外,还可以利用氧化硅(SiO2)、氮化硅(Si3N4)等无机绝缘材料,形成第2绝缘层17。
[半导体装置的制造方法]
接着,参照图3A~图3D,讲述上述结构的半导体装置1的制造方法。
此外,在本实施方式中,如图4所示,在同一个硅晶片(基板)100上统一形成多个半导体装置1,然后切割(切断)硅晶片100,从而将多个半导体装置1单片化,获得单片的半导体装置1。
在图3A~图3D中,为了使说明简洁,只表示出一个半导体装置1的形成方法。
另外,在以下的讲述中,硅基板10与硅晶片100对应。
首先,如图3A所示,在硅基板10的能动面10a上的成为所述集成电路的导电部的位置,形成第1电极11、第2电极18(图3A未示出,参照图2)。
接着,在硅基板10上,形成覆盖第1电极11及第2电极18的第1绝缘层14。进而,覆盖该第1绝缘层14,形成树脂层(未图示)。
再接着,采用众所周知的光刻法及蚀刻法,在所述树脂层上布图,形成规定的形状、即在除了所述第1电极11及第2电极1的正上方位置以外的硅基板10的中央部,形成应力缓和层15。
进而,采用众所周知的光刻法及蚀刻法,除去覆盖第1电极11及第2电极18的位置的绝缘材料,形成开口部14a。
这样,使第1电极11及第2电极18在这些开口部14a内露出。
接着,如图3B所示,在形成与第1电极11连接的布线16同时,还形成与第2电极18连接的再配置布线19。
下面,讲述布线16、再配置布线19的形成方法。
首先,在开口部14a内,为了与第1电极11、第2电极18导通,例如采用溅射法,按照该顺序,用Cu等导电材料成膜。
然后,按照布线16及再配置布线19的形状布图,采用电镀法,在获得的图案上层叠Cu。
另外,特别在再配置布线19的前端部、即如图2所示在和第2电极18相反的一侧,焊盘形状地布图,从而在再配置布线19的前端,形成连接用端子部。
接着,形成覆盖布线16、再配置布线19及连接用端子13的第2绝缘层17。
进而,采用众所周知的光刻法及蚀刻法,除去布线16的一部分、即覆盖和第1电极11相反一侧的绝缘材料,形成开口部17a。
这样,使布线16在该开口部17a内露出后,形成连接部16a。
利用,与此同时,还除去覆盖连接用端子13的绝缘材料,形成开口部17b,从而使连接用端子13在该开口部17b内露出。
再接着,将硅基板10浸渍到加热到规定温度的无电解Ag电镀浴中。
于是,如图3C所示,第2绝缘层17作为掩模发挥作用,在从开口部17a、17b露出的连接部16a及连接用端子13的铜膜上,电镀形成镀银膜21。
这样,在铜膜的表面形成镀银膜21后,能够提高电气接触性,或者能够提高线接合之际的接合性。
然后,如图3D所示,在开口部17a内露出的布线16(镀银膜21)上的连接部16a上,设置例如由铅游离软钎焊构成的软钎焊球,形成外部连接端子12。
此外,对于该外部连接端子12,也可以取代配置软钎焊球后形成,而在布线16上印刷钎焊膏后形成。
然后,如图4所示,利用切割装置110,按照各半导体装置1进行切割(切断)硅晶片(基板)100,从而单片化后,获得半导体装置1。
在这里,对于这样获得的半导体装置1,特别是所述连接用端子13成为检查及调整用(保养维修用)时,即所述第2电极18成为电性地进行所述集成电路的各种功能检查及功能调整的元件时,利用该连接用端子13进行所述集成电路的各种功能检查及功能调整等保养维修。
具体地说,进行IC探头检查及与该IC探头检查同时进行的修理等(断路器断开),从而保证集成电路的功能,或者调整其功能。
此外,为了只在集成电路的功能检查及功能调整时使用所述连接用端子13,结束这些功能检查及功能调整后,就如前所述,用密封树脂20密封这些连接用端子13。
另外,在本实施方式中,如果将连接用端子13作为集成电路的功能检查及功能调整用的结构,就能够确保半导体装置1的质量稳定性,提高可靠性。
换言之,由于外部连接端子12被作为用户安装用使用,所以通常需要加大其端子间距,这时受到电路设计的制约,往往不能将所有的端子作为外部连接端子,从集成电路(IC)的电极抽出。
与此不同,在本实施方式中,在外部连接端子12之外,另行设计不被作为用户安装用的连接用端子13,利用它进行集成电路的功能检查及功能调整,所以能够减少有关外部连接端子12的电路设计中的制约,提高设计自由度。
就是说,在本发明中,所述连接用端子13,如果与外部连接端子12的位置不干涉,所以是不影响设计自由度的位置,就如前所述,可以利用再配置布线19,从第2电极18迂回到任意的位置后配置。
进而,还可以在该再配置布线19上的任意的位置配置。毫无疑问,也可以不使用再配置布线19,直接设置第2电极18。
另外,关于连接用端子13的形态,如前所述,既可以直接在连接用端子13上形成再配置布线19的一部分,也可以在再配置布线19及第2电极18之外,利用焊盘等形成连接用端子13。
另外,调整用的端子及数据写入用的端子等,有时按照功能必须向用户开放,但本实施方式的连接用端子13,特别是在结束功能检查及功能调整后,就用密封树脂20密封,所以能够在以后不能进行使用连接用端子13的调整。
因此,能够一致保持结束检查及调整时的状态,这样,能够如前所述,确保半导体装置1的质量稳定性,提高可靠性。
[电子部件]
采用上述方法获得的连接用端子13,可以全部用于集成电路的功能检查及功能调整,但是也可以只使其一部分用于集成电路的功能检查及功能调整,剩下的部分则在和所述印刷布线板P不同的其它的功能结构体连接之际使用。
进而,还可以使所有的连接用端子13,在和其它的功能结构体连接之际使用。
就是说,将所述半导体装置1和功能结构体一体化后,能够构成本发明的电子部件。
下面,讲述使用所述半导体装置1构成的本发明的电子部件。
图5是表示本发明的电子部件的一种实施方式的图形,图5中的符号30是电子部件。
该电子部件,是具备所述半导体装置1和功能结构体31后构成的部件。
作为功能结构体31,没有特别的限定,可以使用各种元件。
具体的说,可以使用水晶振荡器及压电振动子、压电音叉、弹性表面波元件(SAW(Surface Acoustic Wave)元件)、NEMS结构体、和半导体装置1不同的半导体装置、其它各种电子部件结构体等。
而且,半导体装置1被作为旨在特别驱动这种功能结构体31的驱动装置而使用。
就是说,所述半导体装置1中的第2电极18,在本实施方式中,具有输出旨在驱动功能结构体31的输出信号的功能。这样,与其连接的连接用端子13,就和功能结构体31一侧的连接端子(未图示)电性连接。
在本发明的电子部件30中,半导体装置1搭载在功能结构体31的上面,并且被粘接剂等固定。
半导体装置1,其能动面10a被朝着外侧地搭载。这样,功能结构体31就和半导体装置1中的能动面10a相反的一侧的面结合。
采用这种结构后,在功能结构体31和半导体装置1中,在各自的上面侧,连接用端子13和功能结构体31一侧的连接端子,就被导电连接部连接。
作为导电连接部,采用金线32的线接合,非常简便,是理想的方式。
但是,并不局限于此,例如还可以采用线的软钎焊、梁式引线、TAB(Tape Automated Bonding)等其它众所周知的安装技术。
采用这种金线32的线接合,因为在半导体装置1中的能动面10a一侧实施,所以如图5所示,在和半导体装置1中的外部连接端子12相同的面,形成金线32。
将电子部件30安装到印刷布线板P上时,因为使用外部连接端子12安装,所以金线32就朝着印刷布线板P的一侧。
因此,在本实施方式中,使该金线32的高度(线接合的高度),具体的说是使金线32的顶点高度(从能动面10a到金线32的顶点的距离)远远小于外部连接端子12的高度(从能动面10a到外部连接端子12的顶点的距离),以便特别是在安装时,使金线32不与印刷布线板P接触。
这样,通过外部连接端子12做媒介,将电子部件30与印刷布线板P(外部机器)连接之际,金线32就不会干涉印刷布线板P。
这样,不会引起外部连接端子12和金线32之间的短路等,能够进行良好的连接。
此外,将半导体装置1的连接用端子13和功能结构体31的连接端子线接合后,如图5中的双点划线所示,最好用密封树脂33密封连接用端子13。
这样,能够提高金线32和连接用端子13的连接强度。
进而,因为用树脂覆盖连接用端子13、金线32,所以能够减少特别是以后的工序对连接部结构的损伤,还能够大大提高连接可靠性。
在本实施方式的电子部件30的制造方法中,在利用切割机将半导体装置1单片化之前,在连接端子16a上形成外部连接端子12。但是电子部件30的制造方法,并不局限于此。可以在未形成外部连接端子12时将半导体装置1单片化,在功能结构体31和半导体装置1之间进行线接合后,再形成外部连接端子12。
在连接端子16a及连接用端子13中,在铜膜上实施无电解镍-磷、金的电镀处理时,在金层的表面形成磷浓化层,或者析出镍化合物(主要是氢氧化镍)。我们知道:这样,在电镀上涂敷钎焊料时,在镍-钎焊料的界面上就会出现层间剥离。
与此不同,在本实施方式中,在铜膜上形成镀银膜21,从而能够抑制这种不良现象,能够提高介有线接合及钎焊料的功能结构体的安装后的可靠性。
另外,在本实施方式中,由于在使用镍及磷时,不需要另外实施除去金层的表层部的工序,所以还有利于提高制造效率。
进而,在本实施方式中,因为用无电解电镀形成镀银膜21,所以不需要在采用电解电镀时使用的电解电镀用的布线,能够实现高密度的布线。
进而,在本实施方式中,因为在外部连接端子12之外,另行设置连接用端子13,所以使用该连接用端子13,和功能结构体31进行机械性的连接及电性的连接后,能够将半导体装置1和功能结构体31一体化后,形成电子部件30,能够实现小型化。
另外,由于在硅基板10和外部连接端子12之间设置应力缓和层15,所以例如介有外部连接端子12,连接半导体装置1和印刷布线板P等外部机器之际,即使连接时外部连接端子12出现起因于压力及热量的应力,也因为应力缓和层15缓和、吸收该应力,所以能够防止出现断线等不良现象。
这样,能够提高外部连接端子12和外部机器的连接可靠性。
而且,在本实施方式的电子部件30中,由于利用连接用端子13,用线接合连接半导体装置1和功能结构体31,所以只要使用现有的技术,就能够很容易地使半导体装置1和功能结构体31一体化,构成三维结构,这样作为集合体,能够实现袖珍化,而且能够实现低价格化。
在本实施方式中,作为和连接端子的电性连接的结构,以使用线接合为例,进行了讲述,但并不局限于此,也可以采用伴随着TAB及COF(ChipOn Flexible)等引出线的安装方式进行连接。
以下,在哪种实施方式中也一样。
以上,参照附图,讲述了本发明涉及的适当的实施方式。但毫无疑问,本发明并不局限于涉及的这些例子。
在上述的例子中,示出的各构成部件的各种形状及组合等,只是一个例子,可以在不违背本发明的宗旨的范围内,根据设计要求,进行各种变更。
例如:在上述实施方式中,作为在铜膜上形成的电镀膜21,以银为例进行了讲述。但是采用金或钯等不容易氧化的、可以进行金属接合的金属,或者和其它金属的复合膜时,也能够获得同样的作用·效果。
另外,在图5所示的实施方式中,在作为电性连接的线接合中,利用了连接用端子13。但除此以外,还可以在单纯的机械性的连接中使用连接用端子13。
具体的说,可以与硅基板10形成的集成电路无关,作为电性地独立的岛,使用金属等,形成连接用端子13,将它作为只是为了使半导体装置1和硅基板10机械性地连接的线接合结构而使用。
具体地说,在实现对于功能结构体31而言,半导体装置1悬浮的悬浮结构时、难以使用粘接剂时以及单靠粘接剂不能获得足够的接合强度等时,可以采用利用连接用端子13的线接合结构的机械性连接。
另外,作为连接用端子13的结构,可以取代图1所示的那种焊盘状,采用图6所示的那种柱状(接线柱状)结构。
在图6所示的半导体装置40中,例如用铜柱状(接线柱状)地形成连接用端子41,在其成为连接面的上面,为了防止表面氧化,提高现接合性,而实施银或钯的电镀膜21。
此外,在该半导体装置40中,在外部连接端子12和布线16之间,也形成用和所述连接用端子41同一道工序形成的接线柱(连接部)42。
这样,外部连接端子12就在第2绝缘层17的上面侧,通过电镀膜21及接线柱42做媒介,和布线16电连接。
在这种结构中,柱状的连接用端子41,作为例如使成为下层的导电部的第2电极18及再配置布线19,和按照需要在上层(第2绝缘层17之上)形成的导电部(未图示)导通的上下导通部件发挥作用,这样,能够进一步提高半导体装置40的整体的再配置布线的自由度。
[电路基板及电子机器]
本发明的电路基板,例如将所述电子部件30安装到图1中用双点划线表示的印刷布线板P上后形成。
就是说,电子部件30中的半导体装置1(40)的外部连接端子12,与印刷布线板P的导电部电连接,从而形成本发明的一种实施方式的电路基板。
采用该电路基板后,由于安装了实现小型化的电子部件30,所以可以相应地实现高密度安装,实现高功能化。
另外,本发明的电子机器,也可以安装所述电子部件30后形成。
具体地说,作为搭载了所述电子部件30的电子机器,能够列举图7所示的手机300。
这种电子部件,也由于安装了实现小型化的电子部件30,所以可以相应地实现高密度安装,实现高功能化,同时还伴随着制造效率的提高而有利于的低价格化。
另外,作为应用本发明的电子机器,除了手机以外,例如还可以列举IC卡、摄像机、个人用计算机、头安装显示器、投影仪、办公装置、数码相机、便携型TV、DSP装置、PDA、电子笔记本等。

Claims (15)

1、一种半导体装置,包含:
具有能动面的半导体基板,
在所述半导体基板的能动面一侧设置的第1电极,
设置在所述能动面一侧且与所述第1电极电连接的外部连接端子,以及
设置在所述半导体基板的能动面一侧的连接用端子;
在所述外部连接端子和所述连接用端子的至少一方,形成镀金膜、镀银膜、镀钯膜中的某一个。
2、如权利要求1所述的半导体装置,其特征在于:采用无电解电镀法,形成所述镀金膜、所述镀银膜、所述镀钯膜中的某一个。
3、如权利要求1或2所述的半导体装置,其特征在于:包含再配置布线,该再配置布线设置在所述能动面一侧,将所述第1电极与所述外部连接端子电连接。
4、如权利要求1~3任一项所述的半导体装置,其特征在于:包含第2电极,该第2电极设置在所述半导体基板的能动面一侧,与所述连接用端子电连接。
5、如权利要求1~4任一项所述的半导体装置,其特征在于:所述连接用端子,是为了进行电性的检查及调整的端子。
6、如权利要求1~5任一项所述的半导体装置,其特征在于:包含:连接所述外部连接端子与所述第1电极的布线;和
在所述半导体基板与所述外部连接端子之间设置的应力缓和层。
7、如权利要求1~6任一项所述的半导体装置,其特征在于:包含密封所述连接用端子的密封树脂。
8、如权利要求1~7任一项所述的半导体装置,其特征在于:所述连接用端子形成为柱状。
9、一种电子部件,包含:
半导体装置,该半导体装置具有:具备能动面的半导体基板、在所述半导体基板的能动面一侧设置的第1电极、设置在所述能动面一侧且与所述第1电极电连接的外部连接端子、以及设置在所述半导体基板的能动面一侧的连接用端子;
功能结构体,该功能结构体设置在与所述半导体基板的能动面相反的一侧;以及
导电连接部,该导电连接部将所述功能结构体与所述连接用端子电连接。
10、如权利要求9所述的电子部件,其特征在于:所述导电连接部,是接合线。
11、如权利要求9所述的电子部件,其特征在于:所述导电连接部,具有软钎焊球。
12、一种电路基板,安装着权利要求9~11任一项所述的电子部件。
13、一种电子机器,安装着权利要求9~11任一项所述的电子部件。
14、一种半导体装置的制造方法,包含:
在半导体基板的能动面一侧形成第1电极的工序;
在所述半导体基板的能动面一侧,形成与所述第1电极电连接的外部连接端子的工序;
在所述半导体基板的能动面一侧,形成连接用端子的工序;以及
在所述外部连接端子和所述连接用端子的至少一方,形成镀金膜、镀银膜、镀钯膜中某一个的工序。
15、如权利要求14所述的半导体装置的制造方法,其特征在于:采用无电解电镀法,形成所述镀金膜、所述镀银膜、所述镀钯膜中的某一个。
CN2006101637192A 2005-12-06 2006-12-04 半导体装置及其制造方法、电子部件、电路基板及电子机器 Expired - Fee Related CN1979833B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005351631A JP4379413B2 (ja) 2005-12-06 2005-12-06 電子部品、電子部品の製造方法、回路基板及び電子機器
JP2005-351631 2005-12-06
JP2005351631 2005-12-06

Publications (2)

Publication Number Publication Date
CN1979833A true CN1979833A (zh) 2007-06-13
CN1979833B CN1979833B (zh) 2011-06-29

Family

ID=38117881

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006101637192A Expired - Fee Related CN1979833B (zh) 2005-12-06 2006-12-04 半导体装置及其制造方法、电子部件、电路基板及电子机器

Country Status (5)

Country Link
US (1) US20070126109A1 (zh)
JP (1) JP4379413B2 (zh)
KR (1) KR100786741B1 (zh)
CN (1) CN1979833B (zh)
TW (1) TWI328847B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101978451A (zh) * 2008-03-17 2011-02-16 星电株式会社 滑动操作式开关
CN102054811A (zh) * 2009-10-29 2011-05-11 台湾积体电路制造股份有限公司 集成电路结构
CN111344860A (zh) * 2017-10-05 2020-06-26 德州仪器公司 用于微电子器件的具有保护层的管芯贴合表面铜层

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306635B (zh) 2004-11-16 2015-09-09 罗姆股份有限公司 半导体装置及半导体装置的制造方法
JP5324121B2 (ja) * 2008-04-07 2013-10-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101627574B1 (ko) * 2008-09-22 2016-06-21 쿄세라 코포레이션 배선 기판 및 그 제조 방법
US8637983B2 (en) 2008-12-19 2014-01-28 Ati Technologies Ulc Face-to-face (F2F) hybrid structure for an integrated circuit
TW201233280A (en) * 2011-01-25 2012-08-01 Taiwan Uyemura Co Ltd Chemical palladium-gold plating film method
JP6355541B2 (ja) 2014-12-04 2018-07-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2020145316A (ja) * 2019-03-06 2020-09-10 豊田合成株式会社 半導体装置
CN111755400B (zh) * 2019-03-29 2023-08-08 比亚迪股份有限公司 散热元件及其制备方法和igbt模组

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0734059B1 (en) * 1995-03-24 2005-11-09 Shinko Electric Industries Co., Ltd. Chip sized semiconductor device and a process for making it
CN1311547C (zh) * 2000-03-23 2007-04-18 精工爱普生株式会社 半导体器件及其制造方法、电路基板和电子装置
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
JP2002050647A (ja) * 2000-08-01 2002-02-15 Sharp Corp 半導体装置及びその製造方法
TW577152B (en) * 2000-12-18 2004-02-21 Hitachi Ltd Semiconductor integrated circuit device
TW488052B (en) * 2001-05-16 2002-05-21 Ind Tech Res Inst Manufacture process of bumps of double layers or more
JP4007798B2 (ja) * 2001-11-15 2007-11-14 三洋電機株式会社 板状体の製造方法およびそれを用いた回路装置の製造方法
US6781239B1 (en) * 2001-12-05 2004-08-24 National Semiconductor Corporation Integrated circuit and method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip
US6681640B2 (en) * 2002-02-28 2004-01-27 Nokia Corporation Test fixture and method
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2004247530A (ja) * 2003-02-14 2004-09-02 Renesas Technology Corp 半導体装置及びその製造方法
JP3693056B2 (ja) * 2003-04-21 2005-09-07 セイコーエプソン株式会社 半導体装置及びその製造方法、電子装置及びその製造方法並びに電子機器
US7910471B2 (en) * 2004-02-02 2011-03-22 Texas Instruments Incorporated Bumpless wafer scale device and board assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101978451A (zh) * 2008-03-17 2011-02-16 星电株式会社 滑动操作式开关
CN102054811A (zh) * 2009-10-29 2011-05-11 台湾积体电路制造股份有限公司 集成电路结构
CN102054811B (zh) * 2009-10-29 2013-08-14 台湾积体电路制造股份有限公司 集成电路结构
CN111344860A (zh) * 2017-10-05 2020-06-26 德州仪器公司 用于微电子器件的具有保护层的管芯贴合表面铜层

Also Published As

Publication number Publication date
US20070126109A1 (en) 2007-06-07
CN1979833B (zh) 2011-06-29
KR100786741B1 (ko) 2007-12-18
KR20070059970A (ko) 2007-06-12
JP2007158043A (ja) 2007-06-21
JP4379413B2 (ja) 2009-12-09
TWI328847B (en) 2010-08-11
TW200802647A (en) 2008-01-01

Similar Documents

Publication Publication Date Title
CN1979833B (zh) 半导体装置及其制造方法、电子部件、电路基板及电子机器
JP4476381B2 (ja) 半導体チップパッケージ及びその製造方法
JP2540652B2 (ja) 半導体装置
JP4400802B2 (ja) リードフレーム及びその製造方法並びに半導体装置
US6472745B1 (en) Semiconductor device
US7629687B2 (en) Semiconductor device and method for manufacturing the same
US6420787B1 (en) Semiconductor device and process of producing same
JP2004343030A (ja) 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2009524922A (ja) 半導体部品のための応力緩衝パッケージ
CN100477189C (zh) 半导体装置及制造方法、电子部件、电路基板及电子设备
US20080023820A1 (en) Bond finger on via substrate, process of making same, package made thereby, and method of assembling same
KR100699892B1 (ko) 솔더접합신뢰도 개선을 위한 락킹 구조를 갖는 반도체 소자및 인쇄회로기판
JP4232301B2 (ja) リードフレームの製造方法、及び、半導体装置の製造方法
JP2005026301A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2007103539A (ja) 半導体チップおよび半導体装置
JP3869220B2 (ja) 半導体装置
JP2005116915A (ja) 半導体装置
JP5061010B2 (ja) 半導体モジュール
JP4352263B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2019062062A (ja) 配線基板、電子装置、及び、配線基板の製造方法
JP2005116916A (ja) 半導体装置及びその製造方法
US20030057569A1 (en) Semiconductor device
KR100893558B1 (ko) 반도체 장치, 반도체 장치의 제조 방법 및 전자 부품
JP2008028109A (ja) 半導体装置及び半導体装置の製造方法
KR100715969B1 (ko) 금속리드를 갖는 반도체 칩과 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110629

Termination date: 20171204