CN1979804A - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
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- CN1979804A CN1979804A CNA2006101642858A CN200610164285A CN1979804A CN 1979804 A CN1979804 A CN 1979804A CN A2006101642858 A CNA2006101642858 A CN A2006101642858A CN 200610164285 A CN200610164285 A CN 200610164285A CN 1979804 A CN1979804 A CN 1979804A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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Abstract
本发明提供一种能够防止器件缺陷的半导体器件的制造方法。该方法包括如下步骤:在半导体衬底上形成具有接触孔的绝缘层;通过无电镀在该绝缘层上的接触孔中形成籽晶层;以及在该接触孔中的该籽晶层上形成金属互连。根据本发明,通过无电镀工艺形成具有连续阶梯分布的籽晶层,从而防止在籽晶层上形成的金属互连中出现诸如空隙之类的缺陷。此外,可以使用无电镀工艺和向铜中添加添加剂来形成籽晶层,从而通过添加剂抑制了铜的扩散,从而可减少或防止出现由于热应力而导致的诸如空隙的缺陷。因此,能够提高半导体产品的可靠性。此外,使用无电镀工艺和向铜中添加添加剂来形成籽晶层,从而能够将电迁移(EM)增加约5倍。
Description
技术领域
本发明涉及一种半导体器件,更具体地,涉及一种能够防止器件缺陷的半导体器件的制造方法。
背景技术
为了满足对半导体器件的高集成度和高性能的需求,广泛使用具有多层结构的金属互连,并且将铝用于金属互连。近来,具有良好导电性的铜(Cu)被广泛用于金属互连。
由于铜互连层不容易被图案化,因此主要通过镶嵌工艺和化学机械抛光(CMP)工艺形成铜互连层。
图1至图4示出在现有技术的半导体器件中出现的各种缺陷。
如图1所示,在半导体衬底100上形成绝缘层110,并在绝缘层110上形成金属间绝缘层120。金属间绝缘层120具有与通孔121连通的沟槽122。为了在通孔121和沟槽122中容易地填充铜,形成籽晶层130。籽晶层130通过溅射工艺而形成。在通过如上所述的溅射工艺形成籽晶层130时,如A所示,在通孔121中可能不均匀地形成铜。即,在通孔121的侧面没有形成厚度均匀的籽晶层130,籽晶层130具有不连续的阶梯分布。由于籽晶层130的宽度较窄,所以有时候难于形成籽晶层130。
如图2所示,通过用铜填充其中具有籽晶层130的沟槽和通孔形成铜互连140。
然而,如图1所示,在籽晶层130具有不连续的阶梯分布的情况下,当形成铜互连140时,在铜互连140中可能出现诸如空隙141和/或缝142之类(如图3所示)的缺陷。
另外,当进行包括热处理的后续工艺时,由于图4中用箭头表示的热应力的存在而导致在铜互连140的底部与绝缘层110之间出现诸如空隙143的缺陷。众所周知,出现空隙143的原因是铜会由于热应力而扩散。
发明内容
本发明涉及基本能消除由于现有技术的限制和缺点而导致的上述一个或多个问题的半导体器件(例如,集成电路或液晶显示器)。
本发明的目的是提供一种半导体器件的制造方法,其通过形成具有连续阶梯分布的籽晶层,能够防止诸如空隙和/或缝之类的缺陷或由于热应力而导致的空隙缺陷。
本发明的其它优点、目的和特点,部分将在下面的说明书中提出,部分对所属领域的普通技术人员来说通过研究下文而变得显而易见或可以从本发明的实施中而获知。本发明的目的和其它优点可以通过在书面说明书及其权利要求书以及附图中特别指出的结构而实现和获得。
根据本发明的第一实施例,提供一种半导体器件的制造方法,该方法包括如下步骤:在半导体衬底上形成具有接触孔的绝缘层;通过无电镀在该绝缘层上的该接触孔中形成籽晶层;以及在接触孔中的该籽晶层上形成第一金属互连。
根据本发明的第二实施例,提供一种半导体器件的制造方法,该方法包括:在半导体衬底上形成具有接触孔的绝缘层;使用预定的金属材料和添加剂通过无电镀在该绝缘层上的该接触孔中形成籽晶层;以及在该接触孔中的该籽晶层上形成第一金属互连。
应当理解,本发明前述的概况描述和下面的详细说明均是示范性和说明性的,其目的是提供对要求保护的本发明的进一步解释。
附图说明
附图包括在申请文件中并构成申请文件的一部分,所包含的附图提供对本发明的进一步理解。附图示出本发明的实施例并与说明书一起用于解释本发明的原理。
图1至图4分别示出在现有技术的半导体器件中出现的缺陷;以及
图5和图6分别示出根据本发明的半导体器件的制造工艺。
具体实施方式
以下,参照附图对本发明的优选实施例进行详细描述。请注意,可对本发明的实施例进行各种修改,并且不应将本发明的保护范围解释为局限于下面的实施例。
图5和图6分别示出根据本发明的半导体器件的制造工艺。
如图5所示,在半导体衬底200上形成绝缘层210。在形成绝缘层210之前,在半导体衬底200上可以形成晶体管或电容器。此外,在绝缘层210上或在绝缘层210中可以形成下金属互连。
在绝缘层210上形成具有通孔221和沟槽222的金属间绝缘层220。首先,通常通过化学气相沉积和/或等离子体沉积在绝缘层210上形成金属间绝缘层220。金属间绝缘层220可以包括单一材料,但是更普遍地,其包括多层结构,所述多层结构可以包括:一个或多个蚀刻停止层;一个或多个低介电常数层;以及一个或多个未掺杂层(例如,诸如氮化硅之类的蚀刻停止层;位于所述蚀刻停止层上的可选的未掺杂硅酸盐玻璃[USG]层或富硅氧化物[SRO]层;位于所述未掺杂硅酸盐玻璃[USG]层或富硅氧化物[SRO]层上的诸如氟硅酸盐玻璃[FSG]或碳氧化硅[SiOC,其可以氢化为SiOCH]之类的低介电常数层;可选的第二个如上所述的蚀刻停止层;位于所述第二蚀刻停止层上的可选的第二个如上所述的低介电常数层;以及上盖层,例如USG、等离子体硅烷[氧化物]层、TEOS或O3-TEOS层和/或氮化硅层)。在沉积之后,金属间绝缘层220通常通过CMP被平坦化。通常通过光刻和选择性蚀刻去除金属间绝缘层220的预定区,形成通孔221。然后,形成沟槽222,沟槽222与通孔221连通,并且其宽度大于通孔221。通孔221和沟槽222可通过镶嵌或双镶嵌工艺形成。
在金属间绝缘层220上的通孔221和/或沟槽222中形成籽晶层230。籽晶层230是一种使得后面待形成的金属互连易于形成的介质。
籽晶层230可通过无电镀工艺形成。
在该无电镀工艺中,不需要外部电能,通过使用去氧剂或还原剂,金属盐的水溶液中的金属离子被自催化地去氧或还原,并且将金属提取或沉积在被处理的材料的表面(例如,绝缘层220中的通孔221和沟槽222的侧表面)上。优选地,上述金属盐包括铜盐,例如CuCl2、CuI2、CuSO4等。上述去氧剂或还原剂可以包括能够将铜盐还原为铜金属的任何现有去氧剂或还原剂,例如甲醛、乙醛、羟基乙酸、乙醛酸、抗坏血酸、氢硼化物盐(例如NaBH4或LiBH4)、氨基硼烷络合物(aminoborane complex)和/或连二磷酸钠。上述铜盐溶液可以包括用以形成金属络合物以及防止氢氧化铜的析出的络合剂或螯合剂,例如酒石酸、酒石酸盐、EDTA、(聚)氨(例如乙二胺(EDA))、(聚)甘氨酸、内赤藓醇(meso-erithritol)、羟基乙酸和柠檬酸。并且,上述铜盐溶液的PH值可以利用以下基调整:例如氢氧化钠、氢氧化钾、氢氧化四甲铵(TMAH)和/或氢氧化铵。与平均厚度或目标厚度相同的溅射膜相比,这种无电镀工艺的优点在于其能够形成厚度较均匀的金属层。
根据本发明,取代现有技术的溅射工艺,使用无电镀工艺形成籽晶层230。因此,基本上均匀地形成了具有连续阶梯分布的籽晶层230。具体地,由于通孔221和沟槽222的侧面具有连续的阶梯分布,因此在随后形成的金属互连中,诸如空隙和缝之类的缺陷出现的几率降低,或者根本不会出现。
根据如上所述制造半导体器件的方法,通过无电镀工艺形成籽晶层,所以能够防止出现诸如空隙和缝之类的缺陷。
本发明也可使用上述方法的变化例。
首先,通过如上所述的无电镀工艺形成籽晶层230。然而,在无电镀工艺中,取代使用只包含铜盐作为金属籽晶层的前体的溶液来形成籽晶层230,可以通过向铜盐溶液中添加添加剂来形成籽晶层230。该添加剂可以包括锰(Mn)、镁(Mg)和锌(Zn)中的一种或多种盐。例如,可以将镁(或者镁盐,例如MgF2、MgCl2、MgI2、MgBr2、MgSO4、磷酸镁等)作为添加剂添加到铜盐溶液中,然后可以通过无电镀工艺形成籽晶层230。此外,可以将锰(或者锰盐,例如MnFx、MnClx、MnBrx、MnIx[其中xis2或3,优选为2]、硫酸锰、磷酸锰等)作为添加剂添加到铜盐溶液中,然后可以通过无电镀工艺形成籽晶层230。同样地,可以将锌(或者锌盐,例如ZnF2、ZnCl2、ZnBr2、ZnI2、ZnSO4、磷酸锌等)作为添加剂添加到铜盐溶液中,然后可以通过无电镀工艺形成籽晶层230。另外,还可将锰和镁盐作为添加剂添加到铜盐溶液中,然后可以通过无电镀工艺形成籽晶层230。如上所述,可以将单一添加剂或混合添加剂作为添加剂添加到铜盐溶液中,然后可以通过无电镀工艺形成籽晶层230。
更具体地,通孔221和沟槽222先被催化或处理以在通孔221和沟槽222中形成金属催化剂或金属化合物催化剂(例如钯或PdO)。然后,使用去氧剂或还原剂以在含催化剂的表面上形成Cu-Mn合金镀层,而无需外部供电。在上述过程中,去氧剂或还原剂被氧化而释放电子。释放的电子与金属离子(例如,Cu2+、Mn2+、Mg2+和Zn2+)结合,从而在催化剂的表面上形成籽晶层230(即铜和添加剂的合金)。
这种机制可用反应式(1)表示。
R+H2O→ROx+2H++2e (1)
M2++2e→M0
在反应式(1)中,R表示去氧剂或还原剂,Ox表示该去氧剂或还原剂的氧化反应产物,M2+表示金属离子,M0表示被还原金属。在此,M2+可以包括Cu2+和Mn2+、Mg2+和/或Zn2+,M0可以包括Cu和Mn、Mg和/或Zn。
如上所述,当添加剂被添加到铜中以形成籽晶层230时,通过热处理(后续工艺),添加剂可以在籽晶层230的表面上扩散,从而用作铜扩散阻挡层。因此,在形成金属互连时,铜的扩散被阻止,所以能够减少或防止出现由于热应力而导致的诸如空隙的缺陷。此外,根据本发明当将添加剂添加到铜中以形成籽晶层230时,与通过现有技术溅射工艺形成籽晶层的情况相比,电迁移(EM)可增加或减少大约5倍。在本发明中,EM可以表示由于电子流动而导致的原子可移动的能力之类。
通过后续工艺(例如CMP),可以去除在金属间绝缘层220的上表面上的籽晶层230,而保留在通孔221和沟槽222中形成的籽晶层230。
如图6所示,通过电化学电镀(ECP)工艺用沉积在籽晶层230上的铜层填充通孔221和沟槽222,从而形成金属互连240。即,在EPC工艺期间用籽晶层230上的铜层填充通孔221和沟槽222,从而可形成金属互连240。
因此,由于籽晶层230具有连续的阶梯分布,所以能够减少或防止在金属互连240中出现诸如空隙和缝之类的缺陷。此外,即使在进行后续的热处理时,由于在籽晶层230中含有添加剂,所以也可以阻止铜的扩散,从而可以减少或防止出现由于热应力而导致的诸如空隙的缺陷。
在上面的说明中,描述了具有通孔和沟槽的双镶嵌结构。然而,本发明也可应用单镶嵌结构。
根据如上所述的本发明,通过无电镀工艺形成具有连续阶梯分布的籽晶层,从而防止在籽晶层上形成的金属互连中出现诸如空隙和/或缝之类的缺陷。因此,能够提高诸如集成电路的半导体产品的可靠性。
此外,根据本发明,使用无电镀工艺,并可以向铜中添加添加剂来形成籽晶层,从而通过添加剂抑制了铜的扩散,可减少或防止出现由于热应力而导致的诸如空隙或缝的缺陷。因此,能够提高诸如集成电路的半导体产品的可靠性。
此外,根据本发明,使用无电镀工艺,并可以向铜中添加添加剂来形成籽晶层,从而电迁移(EM)与通过溅射形成的相应籽晶层的EM相比能够增加(或减少)约5倍。
显而易见,对所属领域的技术人员来说可对本发明进行各种修改和变换。因此,应该认为本发明涵盖了落入所附权利要求和其等效范围内的本发明的所有修改和变化。
Claims (15)
1.一种半导体器件的制造方法,该方法包括如下步骤:
a、在半导体衬底上形成具有接触孔的绝缘层;
b、通过无电镀在该绝缘层上的该接触孔中形成籽晶层;以及
c、在该接触孔中的该籽晶层上形成第一金属互连。
2.如权利要求1所述的方法,其中该接触孔包括通孔。
3.如权利要求1所述的方法,其中该接触孔包括通孔和沟槽。
4.如权利要求1所述的方法,其中该籽晶层包含铜。
5.如权利要求4所述的方法,其中该籽晶层还包含锰、锌和镁中的至少之一。
6.如权利要求4所述的方法,其中所述第一金属互连包含铜。
7.如权利要求6所述的方法,还包括如下步骤:
通过重复步骤a至步骤c形成第二金属互连。
8.一种半导体器件的制造方法,该方法包括如下步骤:
a、在半导体衬底上形成具有接触孔的绝缘层;
b、使用预定的金属材料和添加剂通过无电镀在该绝缘层上的该接触孔中形成籽晶层;以及
c、在该接触孔中的该籽晶层上形成第一金属互连。
9.如权利要求8所述的方法,其中该接触孔包括通孔。
10.如权利要求8所述的方法,其中该接触孔包括通孔和沟槽。
11.如权利要求8所述的方法,其中该金属材料包含铜。
12.如权利要求8所述的方法,其中该添加剂包含由锰、锌和镁构成的集合中的成分。
13.如权利要求8所述的方法,其中该添加剂包含锰、锌和镁的混合物。
14.如权利要求8所述的方法,其中所述第一金属互连包含铜。
15.如权利要求8所述的方法,还包括如下步骤:
通过重复步骤a至步骤c形成第二金属互连。
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US6197688B1 (en) * | 1998-02-12 | 2001-03-06 | Motorola Inc. | Interconnect structure in a semiconductor device and method of formation |
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US6727176B2 (en) * | 2001-11-08 | 2004-04-27 | Advanced Micro Devices, Inc. | Method of forming reliable Cu interconnects |
US6774037B2 (en) * | 2002-05-17 | 2004-08-10 | Intel Corporation | Method integrating polymeric interlayer dielectric in integrated circuits |
US20040108217A1 (en) * | 2002-12-05 | 2004-06-10 | Dubin Valery M. | Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby |
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