CN1949505A - Stacked integrated circuit chip and packaging - Google Patents
Stacked integrated circuit chip and packaging Download PDFInfo
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- CN1949505A CN1949505A CNA2006101408738A CN200610140873A CN1949505A CN 1949505 A CN1949505 A CN 1949505A CN A2006101408738 A CNA2006101408738 A CN A2006101408738A CN 200610140873 A CN200610140873 A CN 200610140873A CN 1949505 A CN1949505 A CN 1949505A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
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- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
A stacked integrated circuit chip and a package whereby the area of the package is reduced. The package is characterised by including a substrate, a first integrated circuit chip electrically connected to the substrate by mechanical contact according to a surface mount technology (SMT), and a second integrated circuit chip which is stacked on the first integrated circuit chip and is electrically connected to the substrate by wire bonding.
Description
Technical field
The invention relates to stacked integrated circuit chip and relevant encapsulation.
Background technology
The manufacture process of semiconductor chip is to carry out the etching of unit element and plated film etc. earlier, finally encapsulates through overtesting then.Common encapsulation is to carry out semiconductor chip to mount on the substrate that forms lead, carries out plastotype then in being similar to the moulding synthetic of plastics.
The relevant encapsulation technology of 2 integrated circuit (IC) chip is in the past carried out following explanation.
(1) 2 integrated circuit (IC) chip is encapsulated respectively and be connected.
(2) represented among Fig. 1 a is exactly that 2 integrated circuit (IC) chip have been carried out 101,102 of encapsulation respectively.
In Fig. 1 a, 2 integrated circuit (IC) chip are to interconnect by substrate or conveyer line (diagram) in the outside of chip.
The represented structure of Fig. 1 a be 2 integrated circuit (IC) chip by the encapsulation of carrying out respectively, like this when mounting 2 integrated circuit (IC) chip on 1 machine, the entire area that machine will occur becomes big such problem.
(2) by the structure of MCM (Multi-Chip-Module multi-chip module) 2 integrated circuit (IC) chip are carried out configured separate on 1 plane, be packaged into 1 form of having carried out being electrically connected after handling then.
What Fig. 1 b was represented is respectively 2 integrated circuit (IC) chip 112,113 to be carried out wire-bonded 116 on 1 substrate 111, then the form that is electrically connected with the table top 114 of substrate 111 of the table top 115 of integrated circuit (IC) chip 112,113.
But this kind structure and be positioned at same level with different integrated circuit (IC) chip 112,113 has then caused the whole area occupied of integrated circuit (IC) chip such problem that remains unchanged.
Therefore, from the method for above-mentioned (1) Yu (2), the area occupied that reduces integrated circuit (IC) chip by the machine of stipulating has certain limit, and existence can't be with the such problem of the volume miniaturization of whole machine.
(3) be 2 integrated circuit (IC) chip carried out that lamination is handled and be electrically connected after, encapsulate again.At this moment, 2 integrated circuit (IC) chip are electrically connected with substrate by wire-bonded.
Represented 2 integrated circuit (IC) chip 122,123 of Fig. 1 c are carried out wire-bonded 127,128 with substrate 121 respectively according to lamination-type, and the table top 125,126 to integrated circuit (IC) chip 122,123 is electrically connected with the table top 124 of substrate 121 then.
But, (3) though method can be in the inner area occupied that reduces integrated circuit (IC) chip of encapsulation, because upper and lower 2 integrated circuit (IC) chip of carrying out lamination are connected with wire-bonded by substrate respectively, thereby the electrical interference problem between the processing signals can take place integrated circuit (IC) chip each other.Particularly 2 integrated circuit (IC) chip are when handling different mutually signals, and the problem of interference can be more serious.
(4) in addition, other technology in the past also has at the open communique (publication number: disclosed semiconductor module 10-2005-0062442) of Korean Patent.Herein, semiconductor module is made of 2 semiconductor laminated types, and the semiconductor on top is that flip chip links to each other with the top interface member, and the top interface member is connected with substrate by wire-bonded.
But the structure shown in Fig. 1 d is the module with the different laminated semiconductor structure of technical field of the present invention, makes semiconductor carry out having used interface member in the modular structure of lamination.Thereby the height of all semiconductor structures has just exceeded the height of interface member, needs a plurality of operations, can produce the problem that producing cost increases.
And upper semiconductor (2) must possess the form of flip-chip in order to be connected with top interface member (4).Therefore, upper semiconductor (2) must be carried out wire-bonded (9) from top interface member (4), like this in order to be connected with module substrate, connect the structure complexity that becomes for 2 times of the connection that must engage by flip-chip and being connected of wire-bonded etc. for 1 semiconductor of lamination.Especially the roughly the same noise that tie point sent of the tie point that produces and increase can compare fragile problem.
In addition,, allow the top and the semiconductor of bottom possess the type of attachment of identical flip-chip, can produce on-insulated problem owing to mutual electrical interference in order to allow upper semiconductor carry out lamination.
Summary of the invention
The present invention is in order to solve above-mentioned previous technical problem, and its purpose just provides stacked integrated circuit chip and the encapsulation that reduces package area.
In addition, other purpose of the present invention provides the mutual electrical interference that has the integrated circuit (IC) chip of relevance more than 2 mutually reduced to and minimizes, and the stacked integrated circuit chip of mutually insulated and encapsulation.
[solving the means of problem]
In order to solve above-mentioned problem, form of implementation of the present invention is the stacked integrated circuit chip that contains with the lower part, specifically comprises substrate, passes through this substrate and surface mounting technology (SMT; Surface Mount Technology) the 1st integrated circuit (IC) chip that Mechanical Contact was electrically connected, on the 1st integrated circuit (IC) chip, carries out lamination, then the 2nd integrated circuit (IC) chip that is electrically connected with wire-bonded (Wire-Bonding) by aforesaid base plate.
At this, aforementioned the 2nd integrated circuit (IC) chip preferably is electrically connected with direct wire-bonded by aforesaid base plate.
At this, aforesaid base plate preferably also possesses junction point and tie point, aforementioned the 1st integrated circuit (IC) chip also possess aforementioned junction point and surface mounting technology by aforesaid base plate machinery contact the junction point that is electrically connected, aforementioned the 2nd integrated circuit (IC) chip preferably also possesses the tie point that the aforementioned tie point by aforesaid base plate is electrically connected with wire-bonded.
At this, one of them preferably receives the RF receiving chip of RF (Radio Frequency) signal aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip, and one of aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip are wherein other preferably handles the base band (Base band) as the output signal of aforementioned RF receiving chip or the demodulation chip of IF (IntermediateFrequency intermediate frequency) signal.
At this, aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip preferably receive S-DMB, T-DMB, ISDB-T, Wibro or DVB-H and carry out demodulation.
At this, the stacked integrated circuit chip of being put down in writing in the claim 1 preferably has following feature, and promptly aforesaid base plate is BGA (Ball Grid Array ball bar display pin), LGA (Land Grid Array), multilayer printed board (PCB) or LTCC (LowTemp.Co-fired Ceramics).
Other execution modes of the present invention are the stacked integrated circuit encapsulation that comprise above-mentioned stacked integrated circuit chip more than 2.
At this, preferably has a stacked integrated circuit chip more than 1 among the aforementioned stacked integrated circuit chip at least, one of them preferably receives the RF receiving chip of RF signal aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip, and one of aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip are wherein other preferably handles the base band (Base band) as the output signal of aforementioned RF receiving chip or the demodulation chip of IF (IntermediateFrequency intermediate frequency) signal.
The present invention also has different forms of implementation, promptly comprises above-mentioned stacked integrated circuit chip and the encapsulation of the stacked integrated circuit of the regulation unit element that is electrically connected with aforesaid base plate.
At this, aforementioned unit element is passive component or active element preferably.
At this, preferably one of them is the RF receiving chip that receives the RF signal for aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip, and one of aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip are wherein other preferably handles the base band (Base band) as the output signal of aforementioned RF receiving chip or the demodulation chip of IF (Intermediate Frequency intermediate frequency) signal.
At this, aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip preferably receive S-DMB, T-DMB, ISDB-T, Wibro or DVB-H and carry out demodulation process.
Other forms of implementation that the present invention is correlated with are the stacked integrated circuit chips with following characteristics, it comprises substrate, in the 1st integrated circuit (IC) chip of carrying out lamination on this substrate, on the 1st integrated circuit (IC) chip, carry out the 2nd integrated circuit (IC) chip of lamination, just the 2nd integrated circuit (IC) chip is electrically connected with aforesaid base plate by wire-bonded.
At this, aforementioned the 2nd integrated circuit (IC) chip preferably is electrically connected with aforesaid base plate by direct wire-bonded.
At this, preferably one of them is that receiving RF receiving chip, this aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip of RF signal one of preferably other is that processing is as the base band (Base band) of the output signal of aforementioned RF receiving chip or the demodulation chip of IF (Intermediate Frequency intermediate frequency) signal for aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip.
At this, aforementioned the 1st integrated circuit (IC) chip and aforementioned the 2nd integrated circuit (IC) chip preferably receive S-DMB, T-DMB, ISDB-T, Wibro or DVB-H and carry out demodulation.
[effect of invention]
The present invention can reduce the shared area of integrated circuit (IC) chip, and contribution has been made in the miniaturization of machine, can be reduced expenses and improve the effect of production.
In addition, the present invention reduces to the electrical interference between the integrated circuit (IC) chip of handling 2 multi-form signals and minimizes, and is preventing to have effect aspect the performance degradation.
Brief Description Of Drawings
What Fig. 1 a represented is the form that in the past 2 integrated circuit (IC) chip is encapsulated respectively.
What Fig. 1 b represented is respectively 2 integrated circuit (IC) chip to be carried out wire-bonded on 1 substrate in the past, then the form that the table top of integrated circuit (IC) chip is electrically connected with the table top of substrate.
Fig. 1 c represents is by lamination-type 2 integrated circuit (IC) chip to be engaged at the enterprising line lead of substrate respectively in the past, then the form that the table top of integrated circuit (IC) chip is electrically connected with the table top of substrate.
Fig. 1 d represents is in the past semiconductor module.
What Fig. 2 represented is a form of implementation of the present invention--the sectional view of-stacked integrated circuit chip.
What Fig. 3 represented is other form of implementation of the present invention--the sectional view of-stacked integrated circuit encapsulation.
Embodiment
Below, describe with reference to the accompanying drawing of the form of implementation of the best of the present invention.
Fig. 2 is a form of implementation of the present invention, and represented is the cross section of stacked integrated circuit chip.
The 1st integrated circuit (IC) chip 202 possesses junction point 204.The junction point 204 of the 1st integrated circuit (IC) chip 202 is electrically connected with the Mechanical Contact of the junction point 205 of substrate 201 by surface mounting technology.
The scolding tin (solder ball) that the metallurgy juncture with heat fusing can be used in the junction point 204 of the 1st integrated circuit (IC) chip 202 and boss (bump) etc.
The 2nd integrated circuit (IC) chip 203 is carried out lamination according to lamination-type on the 1st integrated circuit (IC) chip 202.The 2nd integrated circuit (IC) chip 203 possesses tie point 207.The tie point 207 of the 2nd integrated circuit (IC) chip 203 is electrically connected with wire-bonded 208 by company's point 206 of substrate 201.
According to this kind structure, the 1st integrated circuit (IC) chip 202 is carried out surface mount by the junction point 204,205 of substrate 201, be electrically connected then, the 2nd integrated circuit (IC) chip 203 carries out lamination on the 1st integrated circuit (IC) chip 202, be electrically connected with wire-bonded 208 by substrate 201.
Usually, the electrical connection of substrate and integrated circuit (IC) chip engages with flip-chip according to the different wire-bonded that are divided into of its shape.
Wire-bonded is to place semiconductor chip on the substrate that forms lead, uses fine circuit that substrate is electrically connected with semiconductor chip.
It is that the junction point of protuberances such as boss by semiconductor chip and substrate or scolding tin is electrically connected substrate with semiconductor chip that flip-chip engages.When flip-chip is bonded on semiconductor chip is electrically connected with substrate, can save the space with the wire-bonded same degree, the manufacturing of compact package is achieved.
This kind flip-chip engages and belongs to surface mounting technology.When the surface mounting technology meaning is connected to electronic component on the substrate exactly, obstructed zero passage member apertures, but the technology that in the connection line on surface, connects by scolding tin (soldering).This kind technology can be tackled phenomenons such as not digestion [ use], the conductor wire end of parts be narrow, has realized highdensity mounting.
Therefore, the 1st integrated circuit (IC) chip 202 and the 2nd integrated circuit (IC) chip 203 are different mutually with electric connection mode between the substrate 201.
Shown in Fig. 1 c, when 2 chips of lamination-type use the such identical connected mode of wire-bonded, taken place as the signal of telecommunication interference problem between the integrated circuit (IC) chip.
Particularly 2 integrated circuit (IC) chip exist when interrelated, and this kind electrical interference increases, the performance degradation of machine.
In order to solve this type of problem, the connected mode of the integrated circuit (IC) chip of institute's lamination has been carried out different settings in the present invention, made the signal of telecommunication minimum interference between the integrated circuit (IC) chip.
In the form of implementation of the best of the present invention, the 1st integrated circuit (IC) chip 202 is the RF receiving chips that receive the RF signal, and the 2nd integrated circuit (IC) chip 203 is baseband chip or IF chips of the output signal of demodulation RF receiving chip.Perhaps, the 2nd integrated circuit (IC) chip 203 is the RF receiving chips that receive the RF signal, and the 1st integrated circuit (IC) chip 202 is that processing is as the base band of the output signal of RF receiving chip or the demodulation chip of IF signal.
The former is described as benchmark, and its details is as follows.
The 1st integrated circuit (IC) chip 202 is the RF receiving chips that receive the RF signal, the 2nd integrated circuit (IC) chip 203 is for handling as the base band of the output signal of RF receiving chip or the demodulation chip of IF signal, constitutes digital tuner jointly by the RF receiving chip and as the base band of the output signal of RF receiving chip or the demodulation chip of IF signal.
The RF receiving chip receives and processing RF signals, and processing is as the base band of the output signal of RF receiving chip or the demodulation chip processing digital signal of IF signal.
The 1st integrated circuit (IC) chip 122 shown in Fig. 1 c and the 2nd integrated circuit (IC) chip 123, if shown in the structure of Fig. 1 b, all be connected with substrate 121, then can cause the performance degradation of digital tuner because of the electrical interference of RF signal and digital signal by wire-bonded 127,128.
2 integrated circuit (IC) chip 122,123 shown in Fig. 1 c also all are to connect by wire-bonded 127,128, so also identical problem can take place.
Therefore, among the present invention, the 1st integrated circuit (IC) chip 202 is not used wire-bonded, uses surface mounting technology to be electrically connected with substrate 201, the 2nd integrated circuit (IC) chip 203 uses wire-bonded 208 to be electrically connected with substrate 201, minimizes so the electrical interference of RF signal and digital signal has reached.
During for latter instance, the 1st integrated circuit (IC) chip 202 is to handle as the base band of the output signal of RF receiving chip or the demodulation chip of IF signal, and the 2nd integrated circuit (IC) chip 203 is RF receiving chips, and is all identical in addition, so omit explanation.
This kind contains the RF receiving chip and the digital tuner handled as the demodulation chip of the base band of the output signal of RF receiving chip or IF signal can receive and demodulation S-DMB, T-DMB, ISDB-T, Wibro or DVB-H.
Shown in Figure 3 is other form of implementation of the present invention--the cross section of stacked integrated circuit encapsulation.
The stacked integrated circuit chip aspect of Fig. 2 has also comprised regulation unit element 309 in the substrate 301, be electrically connected with substrate 301.Regulation unit element 309 may be to carry out microstrip line and the shape band line that impedance matching is used, and may be again passive component or filters such as resistance, inductance, electric capacity, also may be active elements such as transistor.
As shown in Figure 3, include the 1st and the 2nd integrated circuit (IC) chip 302,303 and unit element 309 on the substrate 301, by encapsulating material (Encapsulation Material; 310) carry out overall package.
Encapsulating material is in order to realize protecting the electrical connection section of integrated circuit (IC) chip and substrate, can to use injection moulding material (Molding Components) or pore (Air Cavity) etc.
In addition, stacked integrated circuit encapsulation shown in Figure 3, when encapsulation, only the 1st integrated circuit (IC) chip 302 and the 2nd integrated circuit (IC) chip 303 parts are carried out epoxy mold (Epoxymolding), can the substrate 301 that comprise the 1st integrated circuit (IC) chip 302 and the 2nd integrated circuit (IC) chip 303 and regulation unit element 309 is whole with can (Matal can) covering encapsulation.
Because the annexation of the 1st integrated circuit (IC) chip and the position of the 2nd integrated circuit (IC) chip is identical with the declaratives of Fig. 2, so the omission explanation.
In addition, the present invention is not limited in above form of implementation, can carry out various changes from technological thought of the present invention in its scope, and these changes also belong to technical scope of the present invention.
Claims (16)
1. stacked integrated circuit chip is characterized in that comprising following a few part: substrate, by this substrate and surface mounting technology (SMT; Surface Mount Technology) the 1st integrated circuit (IC) chip that Mechanical Contact is electrically connected, on the 1st integrated circuit (IC) chip, carry out lamination, then the 2nd integrated circuit (IC) chip that is electrically connected with aforesaid base plate by wire-bonded (Wire-Bonding).
2. stacked integrated circuit chip as claimed in claim 1 is characterized in that: described the 2nd integrated circuit (IC) chip is electrically connected with direct wire-bonded by described substrate.
3. stacked integrated circuit chip as claimed in claim 1, it is characterized in that: described substrate also possesses junction point and tie point, described the 1st integrated circuit (IC) chip also possesses the junction point that the described junction point by described substrate is electrically connected with the Mechanical Contact of surface mounting technology, and described the 2nd integrated circuit (IC) chip also possesses the tie point that the described tie point by described substrate is electrically connected with wire-bonded.
4. stacked integrated circuit chip as claimed in claim 1, it is characterized in that: one of them is the RF receiving chip that receives RF (RadioFrequency) signal for described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip, and the wherein another one of described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip is that processing is as the base band (Base band) of the output signal of described RF receiving chip or the demodulation chip of IF (Intermediate Frequency) signal.
5. stacked integrated circuit chip as claimed in claim 4 is characterized in that: described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip receive S-DMB, T-DMB, ISDB-T, Wibro or DVB-H and carry out demodulation process.
6. stacked integrated circuit chip as claimed in claim 1 is characterized in that: described substrate is BGA (Ball Grid Array), LGA (Land Grid Array), multilayer printed board (PCB) or LTCC (Low Temp.Co-fired Ceramics).
7. a stacked integrated circuit encapsulation is characterized in that comprising 2 described stacked integrated circuit chips of above claim 1.
8. stacked integrated circuit encapsulation as claimed in claim 7, it is characterized in that: among the described stacked integrated circuit chip in the stacked integrated circuit chip that has at least more than 1, one of them is the RF receiving chip that receives the RF signal for described the 1st ic core and described the 2nd integrated circuit (IC) chip, and one of described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip are wherein other is that processing is as the base band of the output signal of described RF receiving chip or the demodulation chip of IF signal.
9. stacked integrated circuit encapsulation is characterized in that comprising described stacked integrated circuit chip of claim 1 and and the unit element that is electrically connected of described substrate.
10. stacked integrated circuit encapsulation as claimed in claim 9, it is characterized in that: described unit element is passive component or active element.
11. stacked integrated circuit encapsulation as claimed in claim 9, it is characterized in that: one of them is the RF receiving chip that receives the RF signal for described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip, and the one of wherein other of described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip is that processing is as the base band of the output signal of described RF receiving chip or the demodulation chip of IF signal.
12. stacked integrated circuit encapsulation as claimed in claim 9, it is characterized in that: described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip receive S-DMB, T-DMB, ISDB-T, Wibro or DVB-H and carry out demodulation process.
13. stacked integrated circuit chip, it is characterized in that: comprise the 2nd integrated circuit (IC) chip of carrying out lamination on the 1st integrated circuit (IC) chip of carrying out lamination on substrate, this substrate and the 1st integrated circuit (IC) chip, having only the 2nd integrated circuit (IC) chip is to be electrically connected with wire-bonded by described substrate.
14. stacked integrated circuit chip as claimed in claim 13 is characterized in that: described the 2nd integrated circuit (IC) chip is electrically connected with described substrate by direct wire-bonded.
15. stacked integrated circuit chip as claimed in claim 13, it is characterized in that: one of them is the RF receiving chip that receives the RF signal for described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip, and the one of wherein other of described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip is that processing is as the base band of the output signal of aforementioned RF receiving chip or the demodulation chip of IF signal.
16. stacked integrated circuit chip as claimed in claim 13 is characterized in that: described the 1st integrated circuit (IC) chip and described the 2nd integrated circuit (IC) chip receive S-DMB, T-DMB, ISDB-T, Wibro or DVB-H and carry out demodulation process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050097137 | 2005-10-14 | ||
| KR1020050097137A KR20070095504A (en) | 2005-10-14 | 2005-10-14 | Stacking type ic chip and package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1949505A true CN1949505A (en) | 2007-04-18 |
| CN100552943C CN100552943C (en) | 2009-10-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101408738A Expired - Fee Related CN100552943C (en) | 2005-10-14 | 2006-10-13 | Stacked integrated circuit chip and encapsulation |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2007110108A (en) |
| KR (1) | KR20070095504A (en) |
| CN (1) | CN100552943C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021989A (en) * | 2012-12-11 | 2013-04-03 | 矽力杰半导体技术(杭州)有限公司 | Multiple-component chip packaging structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101051576B1 (en) * | 2009-09-15 | 2011-07-22 | 삼성전기주식회사 | Optimized battlefield power package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6384128A (en) * | 1986-09-29 | 1988-04-14 | Oki Electric Ind Co Ltd | Hybrid integrated circuit device |
| JPH0983398A (en) * | 1995-09-20 | 1997-03-28 | Mitsubishi Electric Corp | Radio communication equipment |
| JPH11219984A (en) * | 1997-11-06 | 1999-08-10 | Sharp Corp | Semiconductor device package, its manufacture and circuit board therefor |
| JP3891678B2 (en) * | 1998-03-11 | 2007-03-14 | 松下電器産業株式会社 | Semiconductor device |
| US6914950B1 (en) * | 2000-07-31 | 2005-07-05 | Lyrtech Inc. | Multi-protocol receiver |
| JP2002141757A (en) * | 2000-08-08 | 2002-05-17 | Tdk Corp | Power amplifier module, dielectric board for power amplifier module and communication terminal |
| JP2002124538A (en) * | 2000-10-12 | 2002-04-26 | Eastern Co Ltd | Circuit board |
| JP4126891B2 (en) * | 2001-08-03 | 2008-07-30 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| JP2004296719A (en) * | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | Semiconductor device |
| JP2004296613A (en) * | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | Semiconductor device |
| JP2005079385A (en) * | 2003-09-01 | 2005-03-24 | Toshiba Corp | Optical semiconductor device and optical signal input/output device |
| JP4159960B2 (en) * | 2003-09-30 | 2008-10-01 | シャープ株式会社 | Tuner IC package and digital broadcast receiver subassembly |
| JP4260617B2 (en) * | 2003-12-24 | 2009-04-30 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| JP2005303056A (en) * | 2004-04-13 | 2005-10-27 | Toshiba Corp | Semiconductor integrated circuit device |
-
2005
- 2005-10-14 KR KR1020050097137A patent/KR20070095504A/en active Search and Examination
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2006
- 2006-09-26 JP JP2006260910A patent/JP2007110108A/en active Pending
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021989A (en) * | 2012-12-11 | 2013-04-03 | 矽力杰半导体技术(杭州)有限公司 | Multiple-component chip packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100552943C (en) | 2009-10-21 |
| JP2007110108A (en) | 2007-04-26 |
| KR20070095504A (en) | 2007-10-01 |
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