JP2007110108A - Stacked integrated circuit chip and package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked integrated circuit chip and a package whereby the area of the package is reduced. <P>SOLUTION: The package includes a substrate 201, a first integrated circuit chip 202 electrically connected to the substrate by mechanical contact according to a surface mounting technique (SMT), and a second integrated circuit chip 203 which is stacked on the first integrated circuit chip and is electrically connected to the substrate by wire bonding. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a stacked integrated circuit chip and a package.

  In the process of manufacturing a semiconductor chip, processes such as etching and vapor deposition for each wafer are completed, and after packaging, the final packaging is performed. In general packaging, a semiconductor chip is mounted on a substrate on which leads are formed and molded into a molding compound such as plastic.

  A conventional technique for packaging two integrated circuit chips will be described as follows.

  (1) Two integrated circuit chips are packaged and connected.

  (2) FIG. 1a shows a package 101 and 102 of two integrated circuit chips, respectively.

  In FIG. 1a, two integrated circuit chips are connected to each other by a substrate or transmission line (not shown) outside the chip.

  The structure shown in FIG. 1a is one in which two integrated circuit chips are packaged. When two integrated circuit chips are mounted on one device, there is a problem that the entire area of the device increases.

  (2) Two integrated circuit chips having a structure of MCM (Multi-Chip-Module) are separately arranged on one plane, electrically connected, and then packaged into one.

  In FIG. 1b, two integrated circuit chips 112 and 113 are bonded to each other by bonding wires 116 on one substrate 111. The pads 115 of the integrated circuit chips 112 and 113 and the pads 114 of the substrate 111 are connected to each other. It shows what is electrically connected.

  However, such a structure is also located on the same plane as the integrated circuit chips 112 and 113, and the area occupied by the entire integrated circuit chip is maintained as it is.

  Therefore, the methods (1) and (2) described above have a problem in that the volume of the entire device cannot be reduced because there is a limit in reducing the area occupied by the integrated circuit chip with a predetermined device.

  (3) Two integrated circuit chips are stacked in a stacked form, electrically connected, and then packaged. At this time, the two integrated circuit chips are electrically connected to the substrate by wire bonding.

  In FIG. 1C, two integrated circuit chips 122 and 123 are stacked and connected to the substrate 121 by bonding wires 127 and 128, respectively. The pads 125 and 126 of the integrated circuit chips 122 and 123 and the pads 124 of the substrate 121 are electrically connected. It shows that it was connected to.

  However, the method (3) can reduce the area occupied by the integrated circuit chip inside the package, but the two integrated circuit chips stacked on the upper and lower sides are connected to the substrate and wire bonding, respectively. This causes the problem of electrical interference between signals processed by the integrated circuit chips. In particular, when two integrated circuit chips process different kinds of signals from each other, the problem of interference increases.

  (4) In another conventional technique, there is a semiconductor module disclosed in a Korean publication (publication number: 10-2005-0062442) (see FIG. 1d). Here, the semiconductor module is formed by stacking two semiconductors, but the upper semiconductor is flip-chip connected to the upper interposed unit, and the upper interposed unit is connected to the substrate by wire bonding.

  However, the structure shown in FIG. 1d is for a module for a stacked semiconductor structure different from the technical field of the present invention, and an intervening unit is used for a module structure in which semiconductors are stacked. Therefore, there is a problem that the height of the entire semiconductor structure becomes as high as the height of the intervening unit, which requires a plurality of steps and increases the production cost.

  Also, the upper semiconductor (2) must have the form of a flip chip to be connected to the upper intervening unit (4). Thus, in order for the upper semiconductor (2) to connect to the module substrate, wire bonding (9) must be performed from the upper intervening unit (4), which is flip-chip bonding to stack one semiconductor. The structure becomes complicated because the connection must be made twice, such as connection by wire bonding and wire bonding. Furthermore, there is a problem that as the number of connection points increases, the connection point becomes more vulnerable to noise.

  In addition, since the upper and lower semiconductors have the same flip chip connection form for stacking the upper semiconductor, there is a problem that they are not isolated by mutual electrical interference.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a stacked integrated circuit chip and a package that reduce the area of the package.

  It is another object of the present invention to provide a stacked integrated circuit chip and a package which are isolated from each other by minimizing mutual electrical interference between two or more related integrated circuit chips. .

  An embodiment according to the present invention for solving the above-described problems includes a substrate, and a first integrated circuit chip that is electrically connected to the substrate by mechanical contact using surface mount technology (SMT). And a second integrated circuit chip that is stacked on the first integrated circuit chip and is electrically connected to the substrate by wire-bonding.

  Here, it is preferable that the second integrated circuit chip is electrically connected to the substrate directly by wire bonding.

  Here, the substrate further includes a bonding point and a bonding point, and further includes a bonding point where the first integrated circuit chip is electrically connected to the bonding point of the substrate by mechanical contact by surface mounting technology, Preferably, the second integrated circuit chip further includes a bonding point that is electrically connected to the bonding point of the substrate by wire bonding.

  Here, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF (Radio Frequency) signal, and the first integrated circuit chip and the second integrated circuit chip The other one is preferably a demodulation chip that processes a baseband or IF (Intermediate Frequency) signal that is an output signal of the RF receiving chip.

  Here, it is preferable that the first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H.

  Here, the substrate is a BGA (Ball Grid Array), an LGA (Land Grid Array), a multilayer printed circuit board (PCB), or LTCC (Low Temp. Co-fired Ceramics). The stacked integrated circuit chip described is preferred.

  Another embodiment of the present invention is a stacked integrated circuit package including two or more of the above-described stacked integrated circuit chips.

  Here, in at least one of the stacked integrated circuit chips, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF signal. The other one of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband or IF (Intermediate Frequency) signal that is an output signal of the RF receiving chip. It is preferable.

  Another embodiment of the present invention is a stacked integrated circuit package including the above-described stacked integrated circuit chip and a predetermined unit element electrically connected to the substrate.

  Here, the unit element is preferably a passive element or an active element.

  Here, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF signal, and the other one of the first integrated circuit chip and the second integrated circuit chip. One is preferably a demodulation chip that processes a baseband or IF (Intermediate Frequency) signal that is an output signal of the RF receiving chip.

  Here, it is preferable that the first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H.

  Another embodiment according to the present invention includes a substrate, a first integrated circuit chip stacked on the substrate, and a second integrated circuit chip stacked on the first integrated circuit chip, Only the second integrated circuit chip is electrically connected to the substrate by wire bonding, which is a stacked integrated circuit chip.

  Here, it is preferable that the second integrated circuit chip is electrically connected to the substrate directly by wire bonding.

  Here, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF signal, and one of the first integrated circuit chip and the second integrated circuit chip is A demodulation chip that processes a baseband or IF (Intermediate Frequency) signal that is an output signal of the RF receiving chip is preferable.

  Here, it is preferable that the first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H.

  The present invention can reduce the area occupied by the integrated circuit chip, contribute to the downsizing of the equipment, and can reduce the cost and increase the productivity.

  In addition, the present invention has the effect of minimizing electrical interference between integrated circuit chips that process two different types of signals and preventing performance degradation.

  Hereinafter, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 2 is a cross-sectional view of a stacked integrated circuit chip according to an embodiment of the present invention.

  The substrate 201 includes one or more bonding points 206 and one or more bonding points 205. In a preferred embodiment, the substrate is a BGA (Ball Grid Array), an LGA (Land Grid Array), a multilayer printed circuit board (PCB), or an LTCC (Low Temp. Co-fired Ceramics).

  The first integrated circuit chip 202 includes one or more junction points 204 on the lower surface. The junction point 204 of the first integrated circuit chip 202 is electrically connected to the junction point 205 of the substrate 201 by mechanical contact using surface mounting technology.

  The bonding points 204 of the first integrated circuit chip 202 may be solder balls or bumps that are melted by heat to realize metallurgical bonding.

  The second integrated circuit chip 203 is stacked on the upper surface of the first integrated circuit chip 202 in a stacked manner. The second integrated circuit chip 203 includes one or a plurality of bonding points 207 on the upper surface. The bonding point 207 of the second integrated circuit chip 203 is electrically connected to the bonding point 206 of the substrate 201 by wire bonding connection using a bonding wire 208.

  With this configuration, the first integrated circuit chip 202 is surface-mounted and electrically connected by the junction points 204 and 205 of the substrate 201, and the second integrated circuit chip 203 is placed on the first integrated circuit chip 202. They are stacked and electrically connected to the substrate 201 by bonding wires 208.

  Generally, the electrical connection between the substrate and the integrated circuit chip is divided into wire bonding and flip chip bonding depending on the shape.

  In wire bonding, a semiconductor chip is raised and placed on a substrate on which leads are formed, and the substrate and the semiconductor chip are electrically connected using a fine wire.

  In the flip chip bonding, the substrate and the semiconductor chip are electrically connected by a junction between the semiconductor chip and a protruding portion such as a bump or a solder ball of the substrate. Flip chip bonding can save as much space as wire bonding when electrically connecting a semiconductor chip and a substrate, and enables the manufacture of small packages.

  Such flip chip bonding belongs to surface mounting technology. The surface mounting technique means a technique of connecting an electronic component to a substrate through soldering to a surface connection pattern regardless of the component hole. This technology makes it possible to cope with undigested parts and narrowing of the lead pins, realizing high-density mounting.

  Therefore, the first integrated circuit chip 202 and the second integrated circuit chip 203 are different from each other in electrical connection method with the substrate 201.

  As shown in FIG. 1c, when two stacked chips use an equal connection method called wire bonding, a problem of electrical signal interference between integrated circuit chips occurs.

  In particular, when two integrated circuit chips are related to each other, such electrical interference increases and degrades the performance of the instrument.

  In order to solve such a problem, the present invention aims to minimize the electrical signal interference between the integrated circuit chips by changing the connection method of the integrated circuit chips to be stacked.

  In a preferred embodiment of the present invention, the first integrated circuit chip 202 is an RF receiving chip that receives an RF signal, and the second integrated circuit chip 203 is a baseband chip or an IF chip that demodulates the output signal of the RF receiving chip. . Alternatively, the second integrated circuit chip 203 is an RF receiving chip that receives an RF signal, and the first integrated circuit chip 202 is a demodulation chip that processes a baseband or IF signal that is an output signal of the RF receiving chip.

  The former case will be described as follows.

  The first integrated circuit chip 202 is an RF receiving chip that receives an RF signal, and the second integrated circuit chip 203 is a demodulation chip that processes a baseband or IF signal that is an output signal of the RF receiving chip. Together with the baseband or the demodulation chip that processes the IF signal that is the output signal of the RF receiving chip, it constitutes a digital tuner.

  The RF receiving chip receives and processes the RF signal, and the demodulation chip that processes the baseband or IF signal that is the output signal of the RF receiving chip processes the digital signal.

  When the first integrated circuit chip 112 and the second integrated circuit chip 113 shown in FIG. 1b are all connected to the substrate 111 with bonding wires 116 as in the structure of FIG. The performance of the digital tuner deteriorates due to mechanical interference.

  Since the two integrated circuit chips 122 and 123 shown in FIG. 1c are all connected by bonding wires 127 and 128, the same problem occurs.

  Accordingly, in the present invention, the first integrated circuit chip 202 is electrically connected to the substrate 201 using surface mounting technology without using wire bonding, and the second integrated circuit chip 203 is connected to the substrate 201 using wire bonding 208. Since it is electrically connected, electrical interference between the RF signal and the digital signal is minimized.

  In the latter case, all are the same except that the first integrated circuit chip 202 is a demodulation chip for processing a baseband or IF signal that is an output signal of the RF receiving chip, and the second integrated circuit chip 203 is an RF receiving chip. Therefore, the description is omitted.

  Such a digital tuner including an RF receiving chip and a demodulating chip that processes a baseband or IF signal that is an output signal of the RF receiving chip is S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H. Can be received and demodulated.

  FIG. 3 shows another embodiment of the present invention and shows a cross section of a stacked integrated circuit package.

  In the stacked integrated circuit chip of FIG. 2, the substrate 301 further includes a predetermined unit element 309 and is electrically connected to the substrate 301. The predetermined unit element 309 may be a microstrip line or a strip line for impedance matching, may be a passive element such as a resistor, an inductor, or a capacitor, or a filter, and may be an active element such as a transistor.

  As shown in FIG. 3, the first and second integrated circuit chips 302 and 303 and the unit element 309 are included on the substrate 301, and the whole is packaged by an encapsulating material (310). The

  The filler serves to protect the electrical connection between the integrated circuit chip and the substrate, and a molding material (Molding Componens) or air (Air Cavity) can be used.

  In the stacked integrated circuit package shown in FIG. 3, only the first integrated circuit chip 302 and the second integrated circuit chip 303 are subjected to epoxy molding at the time of packaging. The entire substrate 301 including the second integrated circuit chip 303 and the predetermined unit element 309 can be covered with a metal can and packaged.

  The connection relationship between the positions of the first integrated circuit chip and the second integrated circuit chip is the same as that described in FIG.

  In addition, this invention is not limited to said embodiment, A various change is possible within the range which does not deviate from the technical idea which concerns on this invention, and they also belong to the technical scope of this invention.

It shows that two conventional integrated circuit chips have been packaged. FIG. 2 shows a conventional structure in which two integrated circuit chips are wire-bonded on one substrate, and the pads of the integrated circuit chip and the pads of the substrate are electrically connected. Conventionally, two integrated circuit chips are laminated and wire-bonded to a substrate, respectively, and the integrated circuit chip pad and the substrate pad are electrically connected. 1 shows a conventional semiconductor module. 1 is a cross-sectional view of a stacked integrated circuit chip according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of a stacked integrated circuit package according to another embodiment of the present invention.

Claims (16)

A substrate,
A first integrated circuit chip electrically connected to the substrate by mechanical contact with a surface mount technology (SMT);
A laminated integrated circuit chip, comprising: a second integrated circuit chip laminated on the first integrated circuit chip and electrically connected to the substrate by wire bonding.   The stacked integrated circuit chip according to claim 1, wherein the second integrated circuit chip is electrically connected to the substrate directly by wire bonding. The substrate further comprises a bonding point and a bonding point;
The first integrated circuit chip further comprises a junction point that is electrically connected to the junction point of the substrate by mechanical contact using surface mounting technology;
The second integrated circuit chip further comprises a bonding point electrically connected by the bonding point and wire bonding of the substrate.
The multilayer integrated circuit chip according to claim 1, wherein: One of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF (Radio Frequency) signal,
The other one of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband or IF (Intermediate Frequency) signal that is an output signal of the RF receiving chip. The stacked integrated circuit chip according to claim 1, wherein:   The first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H, respectively. Multilayer integrated circuit chip.   The laminated substrate according to claim 1, wherein the substrate is a BGA (Ball Grid Array), an LGA (Land Grid Array), a multilayer printed circuit substrate (PCB), or LTCC (Low Temp. Co-fired Ceramics). Type integrated circuit chip.   A stacked integrated circuit package comprising two or more stacked integrated circuit chips according to claim 1. In at least one stacked integrated circuit chip among the stacked integrated circuit chips,
One of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF signal,
8. The other one of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband or IF signal that is an output signal of the RF receiving chip. The stacked integrated circuit package described.   A stacked integrated circuit package comprising: the stacked integrated circuit chip according to claim 1; and a unit element electrically connected to the substrate.   10. The stacked integrated circuit package according to claim 9, wherein the unit element is a passive element or an active element. One of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF signal,
The other one of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband or IF signal that is an output signal of the RF receiving chip.
The stacked integrated circuit package according to claim 9.   The first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H, respectively. Stacked integrated circuit package. A substrate,
A first integrated circuit chip stacked on the substrate;
A second integrated circuit chip stacked on the first integrated circuit chip,
Only the second integrated circuit chip is electrically connected to the substrate by wire bonding.   14. The stacked integrated circuit chip according to claim 13, wherein the second integrated circuit chip is electrically connected to the substrate directly by wire bonding. One of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip that receives an RF signal,
14. The other one of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband or IF signal that is an output signal of the RF receiving chip. The laminated integrated circuit chip as described.   The first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H, respectively. Multilayer integrated circuit chip.

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