KR20070095504A - Stacking type ic chip and package - Google Patents

Stacking type ic chip and package Download PDF

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KR20070095504A
KR20070095504A KR1020050097137A KR20050097137A KR20070095504A KR 20070095504 A KR20070095504 A KR 20070095504A KR 1020050097137 A KR1020050097137 A KR 1020050097137A KR 20050097137 A KR20050097137 A KR 20050097137A KR 20070095504 A KR20070095504 A KR 20070095504A
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integrated circuit
circuit chip
chip
substrate
signal
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KR1020050097137A
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Korean (ko)
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김경오
김본기
김보은
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인티그런트 테크놀로지즈(주)
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Priority to KR1020050097137A priority Critical patent/KR20070095504A/en
Priority to JP2006260910A priority patent/JP2007110108A/en
Priority to CNB2006101408738A priority patent/CN100552943C/en
Publication of KR20070095504A publication Critical patent/KR20070095504A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
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    • H01L2924/3011—Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A stacked IC chip and its package are provided to reduce the area of the package by electrically connecting a second integrated circuit chip with a substrate by wire bonding. A first integrated circuit chip(202) is electrically connected to a substrate(201) by mechanical contact according to a surface mounting technique. A second integrated circuit chip(203) is stacked on the first IC chip and is electrically connected to the substrate by a wire bonding(208). The substrate has a joining point(205) and a bonding point(206). The first IC chip has a joining point(204) electrically connected to the joining point of the substrate. The second IC chip has a bonding point(207) electrically connected to the bonding point of the substrate.

Description

적층형 집적회로 칩 및 패키지.{Stacking Type IC Chip and Package}Stacked integrated circuit chips and packages. {Stacking Type IC Chip and Package}

도 1a는 종래에 2개의 집적회로 칩을 각각 패키징한 것을 도시한 것이다.1A shows a conventional packaging of two integrated circuit chips, respectively.

도 1b는 종래에 하나의 기판 위에 2개의 집적회로 칩을 각각 와이어-본딩한 것으로, 집적회로 칩의 패드와 기판의 패드를 전기적으로 접속한 것을 도시한 것이다.FIG. 1B shows a conventional wire-bonding of two integrated circuit chips on one substrate, and electrically connecting pads of the integrated circuit chip and pads of the substrate.

도 1c는 종래에 2개의 집적회로 칩이 스택의 형태로 기판에 각각 와이어-본딩한 것으로, 집적회로 칩의 패드와 기판의 패드가 전기적으로 접속된 것을 도시한 것이다.FIG. 1C is a diagram in which two integrated circuit chips are wire-bonded to a substrate in the form of a stack, and the pads of the integrated circuit chip and the pads of the substrate are electrically connected to each other.

도 1d는 종래의 반도체 모듈을 도시한 것이다.1D illustrates a conventional semiconductor module.

도 2는 본 발명의 일 실시예에 의한 적층형 집적회로 칩의 단면도를 도시한 것이다.2 is a cross-sectional view of a stacked integrated circuit chip according to an exemplary embodiment of the present invention.

도 3는 본 발명의 다른 실시예에 의한 적층형 집적회로 패키지의 단면도를 도시한 것이다.3 is a cross-sectional view of a stacked integrated circuit package according to another exemplary embodiment of the present invention.

본 발명은 집적회로 칩 및 패키지에 관한 것이다.The present invention relates to integrated circuit chips and packages.

반도체 칩을 제조하는 과정에서 웨이퍼 단위의 식각 및 증착 등의 공정을 마치면 테스트를 거쳐 최종적으로 패키징을 하게 된다. 일반적인 패키징은 리드가 형성된 기판에 반도체 칩을 실장하고 플라스틱과 같은 몰딩 합성물로 몰딩하는 것을 말한다.In the process of manufacturing a semiconductor chip, the wafer-based etching and deposition processes are finished, and then finally packaged. Typical packaging refers to mounting a semiconductor chip on a substrate on which a lead is formed and molding into a molding compound such as plastic.

2개 이상의 상호 연관성이 있는 집적회로 칩의 패키징에 대한 종래기술을 살펴보면 다음과 같다.The prior art for packaging two or more interconnected integrated circuit chips is as follows.

(1) 상호 연관성이 있는 2개 이상의 집적회로 칩을 각각 패키징하여 연결한다. (1) Package and connect two or more interconnected integrated circuit chips, respectively.

도 1a는 2개의 집적회로 칩을 각각 패키징한 것(101,102)을 도시한 것이다.FIG. 1A illustrates packaging 101 and 102 of two integrated circuit chips, respectively.

도 1a에서 2개의 집적회로 칩은 상호 연관성이 있는 것으로 칩의 외부에서 기판 또는 전송선(도시되어 있지 않음)에 의해 상호 연결된다In FIG. 1A the two integrated circuit chips are interconnected and interconnected by a substrate or transmission line (not shown) outside the chip.

도 1a에 도시된 구조는 상호 연관성이 있는 2개 이상의 집적회로 칩이 각각 패키징됨으로써 상호 연관성있는 2개의 집적회로 칩을 하나의 기기에 실장할 경우 기기의 전체 면적이 커지는 문제점이 있다.The structure shown in FIG. 1A has a problem in that the total area of the device is increased when two interconnected integrated circuit chips are packaged in a single device by packaging two or more interconnected integrated circuit chips.

(2) MCM(Multi-Chip-Module)의 형태로 2개 이상의 집적회로 칩을 하나의 평면상에 분리 배치하여 전기적으로 연결한 후 하나로 패키징한다. (2) In the form of MCM (Multi-Chip-Module), two or more integrated circuit chips are separately arranged on one plane, electrically connected, and packaged as one.

도 1b는 하나의 기판(111) 위에 2개의 집적회로 칩(112,113)을 각각 와이어-본딩(116)한 것으로, 집적회로 칩(112,113)의 패드(115)와 기판(111)의 패드(114)를 전기적으로 접속한 것을 도시한 것이다.FIG. 1B is a wire-bonding 116 of two integrated circuit chips 112 and 113 on one substrate 111, respectively. The pad 115 of the integrated circuit chips 112 and 113 and the pad 114 of the substrate 111 are shown in FIG. Shows the electrically connected.

그러나, 이러한 구조 역시 각각의 집적회로 칩(112,113)이 같은 평면에 위치 하여 집적회로 칩 전체가 차지하는 면적은 그대로 유지되는 문제점이 있다.However, such a structure also has a problem that the respective integrated circuit chips 112 and 113 are located on the same plane so that the area occupied by the entire integrated circuit chip is maintained as it is.

따라서, 전술한 (1)과 (2)의 방법은 소정의 기기에서 집적회로 칩이 차지하는 면적을 줄이는 데에 한계가 있어 전체 기기의 부피를 소형화하지 못하는 문제점이 있다.Therefore, the above-described methods (1) and (2) have limitations in reducing the area occupied by the integrated circuit chip in a given device, and thus, there is a problem in that the volume of the entire device cannot be reduced.

(3) 2개의 집적회로 칩을 스택의 형태로 쌓아 올려 전기적으로 연결한 후 패키징을 하는 것이다. 이때에 2개의 집적회로 칩은 와이어-본딩에 의해 기판과 전기적으로 연결된다.(3) Two integrated circuit chips are stacked and electrically connected to each other in a stack. At this time the two integrated circuit chips are electrically connected to the substrate by wire-bonding.

도 1c는 2개의 집적회로 칩(122,123)이 스택의 형태로 기판(121)에 각각 와이어-본딩(127,128)한 것으로, 집적회로 칩(122,123)의 패드(125,126)와 기판(121)의 패드(124)가 전기적으로 접속된 것을 도시한 것이다.In FIG. 1C, two integrated circuit chips 122 and 123 are wire-bonded 127 and 128 to the substrate 121 in the form of a stack, respectively. The pads 125 and 126 of the integrated circuit chips 122 and 123 and the pads of the substrate 121 are illustrated in FIG. 124 is electrically connected.

그러나, (3)의 방법은 패키지 내부에서 집적회로 칩이 차지하는 면적은 줄일 수 있으나, 상.하로 스택된 2개의 집적회로 칩이 각각 기판과 와이어-본딩으로 연결됨으로써 상호 집적회로 칩들이 처리하는 신호간의 전기적 간섭의 문제가 발생하게 된다. 특히, 2개의 집적회로 칩이 서로 다른 이종의 신호를 처리하는 경우에 간섭의 문제는 커지게 된다.However, the method of (3) can reduce the area occupied by the integrated circuit chip inside the package, but the signals integrated by the integrated circuit chips are processed by connecting two integrated circuit chips stacked up and down, respectively, by wire-bonding with the substrate. The problem of electrical interference will arise. In particular, when two integrated circuit chips process different heterogeneous signals, the problem of interference becomes large.

(4) 또 다른 종래기술로는 대한민국 공개공보(공개번호: 10-2005-0062442)에 개시되어 있는 반도체 모듈이 있다. 여기서, 반도체 모듈은 2개의 반도체가 적층형으로 구성되어 있으나, 상부의 반도체는 플립 칩의 형태로 상부개재유닛에 접속되고, 상부개제유닛이 기판과 와이어-본딩이 되는 형태이다.(4) Another conventional technique is a semiconductor module disclosed in Korean Laid-Open Publication No. 10-2005-0062442. Here, in the semiconductor module, two semiconductors are stacked, but the upper semiconductor is connected to the upper interposition unit in the form of a flip chip, and the upper interposition unit is wire-bonded with the substrate.

그러나, 도 1d에 도시된 구조는 본 발명의 기술 분야와는 상이한 적층형 반 도체 구조를 위한 모듈에 대한 것으로, 반도체를 적층시키는 모듈구조를 위해 개재유닛을 사용한다. 따라서, 개재유닛의 높이 만큼 전체 반도체 구조의 높이가 증가하게 되고, 다수의 공정이 필요하여 생산비용을 증가시키게 되는 문제점이 있다.However, the structure shown in FIG. 1D is for a module for a stacked semiconductor structure different from the technical field of the present invention, and uses an interposition unit for a module structure for stacking semiconductors. Therefore, the height of the entire semiconductor structure is increased by the height of the intervening unit, and a number of processes are required to increase the production cost.

또한, 상부 반도체(2)는 상부개제유닛(4)에 접속되기 위해 플립 칩의 형태를 가져야만 한다. 이에 따라, 상부 반도체(2)가 모듈 기판과 접속하기 위해서는 상부개제유닛(4)에서 와이어-본딩(9)을 해야 하며, 이것은 하나의 반도체를 적층하기 위해 플립칩 본딩에 의한 접속과 와이어-본딩에 의한 접속 등의 2번 개별적인 접속을 해야 하므로 구조가 복잡해진다. 더욱이, 증가되는 접속점만큼 접속점에 의한 잡음에 취약한 문제점이 있다.In addition, the upper semiconductor 2 must have the form of a flip chip in order to be connected to the upper opening unit 4. Accordingly, in order for the upper semiconductor 2 to be connected with the module substrate, wire-bonding 9 must be performed in the upper opening unit 4, which is connected and wire-bonded by flip chip bonding to stack one semiconductor. The structure is complicated because it requires two separate connections such as connection by the Moreover, there is a problem that the vulnerability by the connection point is as vulnerable as the increasing connection point.

또한, 상부 반도체를 적층시키기 위해 상부와 하부의 반도체가 동일한 플립 칩의 접속형태를 가지게 되므로 상호 전기적 간섭에 의해 아이솔레이션이 되지 못하는 문제점이 있다.In addition, since the upper and lower semiconductors have the same flip chip connection form in order to stack the upper semiconductors, there is a problem in that isolation is not possible due to mutual electrical interference.

본 발명에서는 패키지의 면적을 줄이는 적층형 집적회로 칩 및 패키지를 제공하는 데 그 목적이 있다.An object of the present invention is to provide a stacked integrated circuit chip and package to reduce the area of the package.

본 발명의 다른 목적은 2개 이상의 상호 연관성 있는 집적회로 칩들의 상호 전기적 간섭을 최소화시켜 서로 아이솔레이션되는 적층형 집적회로 칩 및 패키지를 제공하는 데 있다.It is another object of the present invention to provide stacked integrated circuit chips and packages that are isolated from each other by minimizing mutual electrical interference of two or more interconnected integrated circuit chips.

전술한 과제를 해결하기 위한 본 발명에 의한 일 실시예는 기판; 상기 기판 과 표면실장기술(SMT; Surface Mount Technology)에 의한 기계적인 접촉에 의해 전기적으로 연결되는 제1 집적회로 칩; 및 상기 제1 집적회로 칩 위에 적층되며, 상기 기판과 와이어-본딩(Wire-Bonding)에 의해 전기적으로 연결되는 제2 집적회로 칩을 포함하는, 적층형 집적회로 칩이다.One embodiment according to the present invention for solving the above problems is a substrate; A first integrated circuit chip electrically connected to the substrate by mechanical contact by Surface Mount Technology (SMT); And a second integrated circuit chip stacked on the first integrated circuit chip and electrically connected to the substrate by wire-bonding.

여기서, 상기 제2 집적회로 칩은 상기 기판과 직접 와이어-본딩에 의해 전기적으로 연결되는 것이 바람직하다.Here, the second integrated circuit chip is preferably electrically connected to the substrate by direct wire-bonding.

여기서, 상기 기판은 접합점과 본딩점을 더 구비하고, 상기 제1 집적회로 칩은 상기 기판의 상기 접합점과 표면실장기술에 의한 기계적 접촉에 의해 전기적으로 연결되는 접합점을 더 구비하고, 상기 제2 집적회로 칩은 상기 기판의 상기 본딩점과 와이어-본딩에 의해 전기적으로 연결되는 본딩점을 더 구비하는 것이 바람직하다.The substrate may further include a junction point and a bonding point, and the first integrated circuit chip may further include a junction point electrically connected to the junction point of the substrate by mechanical contact by a surface mount technology, and the second integration point may be used. The circuit chip preferably further comprises a bonding point electrically connected to the bonding point of the substrate by wire-bonding.

여기서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩이 바람직하다.Here, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, and the other of the first integrated circuit chip and the second integrated circuit chip is the RF receiving chip. A demodulation chip for processing a baseband or IF (intermediate frequency) signal, which is an output signal of the signal, is preferable.

여기서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩은 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조하는 것이 바람직하다.The first integrated circuit chip and the second integrated circuit chip preferably receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H.

여기서, 상기 기판은 BGA(Ball Grid Array), LGA(Land Grid Array), 다층 인쇄회로기판(PCB) 또는 LTCC(Low Temp. Co-fired Ceramics) 인 것이 바람직하다.The substrate may be a ball grid array (BGA), a land grid array (LGA), a multilayer printed circuit board (PCB), or a low temp.co-fired ceramics (LTCC).

본 발명의 다른 실시예는 제1 항에 의한 적층형 집적회로 칩을 2개 이상 포 함하는, 적층형 집적회로 패키지이다.Another embodiment of the present invention is a stacked integrated circuit package including two or more stacked integrated circuit chips according to claim 1.

여기서, 상기 적층형 집적회로 칩 중 적어도 하나 이상의 적층형 집적회로 칩에서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩인 것이 바람직하다.Here, in at least one stacked integrated circuit chip of the stacked integrated circuit chip, any one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, the first integrated circuit chip And another one of the second integrated circuit chip is a demodulation chip for processing a baseband (IF) signal or an intermediate frequency (IF) signal, which is an output signal of the RF receiver chip.

본 발명의 또 다른 실시예는 제1 항에 의한 적층형 집적회로 칩; 및 상기 기판과 전기적으로 연결되는 소정의 단위 소자를 포함하는, 적층형 집적회로 패키지이다.Another embodiment of the present invention is a stacked integrated circuit chip according to claim 1; And a predetermined unit device electrically connected to the substrate.

여기서, 상기 단위 소자는 수동 소자 또는 능동 소자인 것이 바랍직하다.Here, the unit device is preferably a passive device or an active device.

여기서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩이 바람직하다. Here, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, and the other of the first integrated circuit chip and the second integrated circuit chip is the RF receiving chip. A demodulation chip for processing a baseband or IF (intermediate frequency) signal, which is an output signal of the signal, is preferable.

여기서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩은 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조하는 것이 바람직하다. The first integrated circuit chip and the second integrated circuit chip preferably receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H.

본 발명에 의한 또 다른 실시예는 기판; 상기 기판 상에 적층되는 제1 집적회로 칩; 및 상기 제1 집적회로 칩 위에 적층되는 제2 집적회로 칩을 포함하고, 상기 제2 집적회로 칩만이 상기 기판과 와이어-본딩(Wire-Bonding)에 의해 전기적으로 연결되는, 적층형 집적회로 칩이다.Another embodiment according to the present invention is a substrate; A first integrated circuit chip stacked on the substrate; And a second integrated circuit chip stacked on the first integrated circuit chip, wherein only the second integrated circuit chip is electrically connected to the substrate by wire-bonding.

여기서, 상기 제2 집적회로 칩은 상기 기판과 직접 와이어-본딩에 의해 전기적으로연결되는 것이 바람직하다.Here, the second integrated circuit chip is preferably electrically connected to the substrate by direct wire-bonding.

여기서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩인 것이 바람직하다.Here, one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, and the other of the first integrated circuit chip and the second integrated circuit chip is the RF receiving chip. Preferably, the demodulation chip processes a baseband (IF) signal or an IF signal.

여기서, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩은 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조하는 것이 바람직하다. The first integrated circuit chip and the second integrated circuit chip preferably receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro, or DVB-H.

이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 2는 본 발명에 의한 일 실시예로 적층형 집적회로 칩의 단면을 도시한 것이다.2 is a cross-sectional view of a stacked integrated circuit chip according to an exemplary embodiment of the present invention.

기판(201)은 본딩점(206)과 접합점(205)을 구비한다. 바람직한 실시예로 기판은 전기적 연결을 위한 금속배선 또는 단위수동소자를 내부에 가지는 BGA(Ball Grid Array), LGA(Land Grid Array), 다층 인쇄회로기판(PCB) 또는 LTCC(Low Temp. Co-fired Ceramics) 등 이다.The substrate 201 has a bonding point 206 and a junction point 205. In a preferred embodiment, the substrate has a metal grid or a unit passive device for electrical connection therein, a ball grid array (BGA), a land grid array (LGA), a multilayer printed circuit board (PCB), or a low temp.co-fired Ceramics) and so on.

제1 집적회로 칩(202)은 접합점(204)을 구비한다. 제1 집적회로의 접합점(204)은 기판(201)의 접합점(205)과 표면실장기술(SMT; Surface Mount Technology)에 의한 기계적인 접촉에 의해 전기적으로 연결된다.The first integrated circuit chip 202 has a junction point 204. The junction 204 of the first integrated circuit is electrically connected to the junction 205 of the substrate 201 by mechanical contact by surface mount technology (SMT).

제1 집적회로 칩(202)의 접합점(204)은 열에 의해 용융되어 야금학적 접함점을 구현하는 방식의 솔더 볼이나 범프 등을 이용할 수 있다.The junction point 204 of the first integrated circuit chip 202 may use solder balls, bumps, or the like, which melt by heat to implement metallurgical contact points.

제2 집적회로 칩(203)은 제1 집적회로 칩(202)의 위에 스택 형태로 적층된다. 제2 집적회로 칩(203)은 본딩점(207)을 구비한다. 제2 집적회로 칩(203)의 본딩점(207)은 기판(201)의 본딩점(206)과 와이어-본딩(208)에 의해 전기적으로 연결된다.The second integrated circuit chip 203 is stacked on top of the first integrated circuit chip 202 in a stack form. The second integrated circuit chip 203 has a bonding point 207. The bonding point 207 of the second integrated circuit chip 203 is electrically connected to the bonding point 206 of the substrate 201 by wire-bonding 208.

이렇게 구성함으로써, 제1 집적회로 칩(202)은 기판(201)에 접촉점(204,205)에 의해 표면실장되어 전기적으로 연결된고, 제2 집적회로 칩(203)은 제1 집적회로 칩(202)의 위에 적층되어 기판(201)과 와이어-본딩(208)에 의해 전기적으로 연결된다. In this configuration, the first integrated circuit chip 202 is surface-mounted and electrically connected to the substrate 201 by the contact points 204 and 205, and the second integrated circuit chip 203 is connected to the first integrated circuit chip 202. Stacked above and electrically connected by substrate 201 and wire-bonding 208.

일반적으로 기판과 집적회로 칩의 전기적 연결은 그 형태에 따라 와이어-본딩과 플립칩 본딩으로 나뉜다. In general, the electrical connection between the substrate and the integrated circuit chip is divided into wire-bonding and flip-chip bonding according to its shape.

와이어-본딩은 리드가 형성된 기판에 반도체 칩을 올려두고 미세 와이어를 이용해 기판과 반도체 칩을 전기적으로 연결한다. Wire-bonding places a semiconductor chip on a substrate on which a lead is formed and electrically connects the substrate and the semiconductor chip using fine wires.

플립칩 본딩은 반도체 칩과 기판의 범프 또는 솔더 볼과 같은 돌출부의 접합점에 의해 기판과 반도체 칩을 전기적으로 연결한다.Flip chip bonding electrically connects the substrate and the semiconductor chip by a junction point of a protrusion such as a bump or solder ball of the semiconductor chip and the substrate.

플립칩 본딩은 반도체 칩과 기판을 전기적으로 연결할 때에 와이어-본딩 만큼의 공간을 절약할 수 있어 작은 패키지의 제조가 가능하다.Flip chip bonding can save space as much as wire-bonding when electrically connecting a semiconductor chip and a substrate, thus enabling the manufacture of small packages.

이러한 플립칩 본딩은 표면실장기술에 속한다. 표면실장기술은 전자부품을 기판에 접속할 때 부품구멍에 의하지 않고 표면의 접속패턴에 솔더린을 통해 접속 하는 기술을 의미한다. 이 기술에 의해 부품의 미소화, 리드핀의 협칩화에 대응이 가능해져 고밀도 실장이 실현된다.Such flip chip bonding belongs to the surface mount technology. Surface mounting technology refers to a technique for connecting an electronic component to a substrate by soldering to a surface connection pattern instead of a component hole. This technology makes it possible to cope with miniaturization of parts and narrow chip of lead pins, and high density mounting is realized.

따라서, 제1 집적회로 칩(202)과 제2 집적회로 칩(203)은 기판(201)과의 전기적인 연결방식이 서로 상이하게 된다. Accordingly, the first integrated circuit chip 202 and the second integrated circuit chip 203 have different electrical connection schemes with the substrate 201.

도 1c에 도시된 바와 같이 적층형의 2개의 칩이 와이어-본딩이라는 동일한 연결방식을 사용하는 경우에는 집적회로 칩들 간의 전기적 신호간섭의 문제가 발생하게 된다.As shown in FIG. 1C, when two stacked chips use the same connection method as wire-bonding, a problem of electrical signal interference between integrated circuit chips occurs.

특히, 2개의 집적회로 칩이 상호 연관성이 있는 경우에는 이러한 상호 간의 전기적 간섭이 증대되어 기기의 성능을 열화시킨다.In particular, when two integrated circuit chips are correlated with each other, such electrical interference is increased to degrade the performance of the device.

본 발명에서는 이러한 문제점을 해결하기 위하여 적층되는 집적회로 칩의 연결방식을 상이하게 하여 집적회로 칩들 간의 전기적 신호 간섭을 최소화 하고자 하는 것이다. In order to solve this problem, the present invention aims to minimize the electrical signal interference between the integrated circuit chips by differently connecting the stacked integrated circuit chips.

본 발명의 바람직한 실시예로 제1 집적회로 칩(202)은 RF 신호를 수신하는 RF 수신 칩이고, 제2 집적회로 칩(203)은 RF 수신 칩의 출력신호를 복조하는 베이스밴드(Baseband) 칩 또는 IF(Intermediate Frequency) 칩이다. 또는, 제2 집적회로 칩(203)은 RF 신호를 수신하는 RF 수신 칩이고, 제1 집적회로 칩(202)은 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩이다.In a preferred embodiment of the present invention, the first integrated circuit chip 202 is an RF receiving chip for receiving an RF signal, and the second integrated circuit chip 203 is a baseband chip for demodulating an output signal of the RF receiving chip. Or IF (Intermediate Frequency) chip. Alternatively, the second integrated circuit chip 203 may be an RF receiving chip that receives an RF signal, and the first integrated circuit chip 202 may receive a baseband or intermediate frequency (IF) signal that is an output signal of the RF receiving chip. Demodulation chip to process.

전자의 경우를 기준으로 설명하면 다음과 같다.The following description will be made based on the former case.

제1 집적회로 칩(202)은 RF 신호를 수신하는 RF 수신 칩이고, 제2 집적회로 칩(203)은 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩으로 RF 수신 칩과 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩은 함께 디지털 튜너를 구성한다.The first integrated circuit chip 202 is an RF receiving chip that receives an RF signal, and the second integrated circuit chip 203 processes a baseband or intermediate frequency (IF) signal that is an output signal of the RF receiving chip. As a demodulation chip, a demodulation chip which processes a baseband or IF (intermediate frequency) signal, which is an output signal of the RF reception chip and the RF reception chip, constitutes a digital tuner.

RF 수신 칩은 RF 신호를 수신하여 처리하고, RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩은 디지털 신호를 처리한다.The RF receiving chip receives and processes an RF signal, and a demodulation chip processing a baseband or IF (intermediate frequency) signal, which is an output signal of the RF receiving chip, processes a digital signal.

만약, 도 1b에 도시된 제1 집적회로 칩(122)과 제2 집적회로 칩(123)이 도 1b의 구조와 같이 모두 와이어-본딩(127,128)으로 기판(121)과 연결되면, RF 신호와 디지털 신호의 전기적 간섭에 의해 디지털 튜너의 성능이 열화된다.If the first integrated circuit chip 122 and the second integrated circuit chip 123 illustrated in FIG. 1B are all connected to the substrate 121 by wire-bonding 127 and 128 as in the structure of FIG. 1B, the RF signal and the Electrical interference of the digital signal degrades the performance of the digital tuner.

도 1c에 도시된 2개의 집적회로 칩(122,123)도 모두 와이어-본딩(127,128)으로 연결되었으므로 동일한 문제점이 발생하게 된다.Since the two integrated circuit chips 122 and 123 illustrated in FIG. 1C are also connected by wire-bonding 127 and 128, the same problem occurs.

따라서, 본 발명에서는 제1 집적회로 칩(202)은 와이어-본딩을 이용하지 아니하고 표면실장기술을 이용하여 기판(201)과 전기적으로 연결하고, 제2 집적회로 칩(203)은 와이어-본딩(208)을 이용하여 기판(201)과 전기적으로 연결함으로써, RF 신호와 디지털 신호의 전기적 간섭을 최소화한 것이다. Accordingly, in the present invention, the first integrated circuit chip 202 is electrically connected to the substrate 201 using surface mount technology without using wire-bonding, and the second integrated circuit chip 203 is wire-bonded ( By electrically connecting to the substrate 201 using the 208, the electrical interference of the RF signal and the digital signal is minimized.

후자의 경우는 제1 집적회로 칩(202)이 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩이고, 제2 집적회로 칩(203)이 RF 수신 칩인 것을 제외하고는 모두 동일하므로 설명을 생략하 기로 한다.In the latter case, the first integrated circuit chip 202 is a demodulation chip that processes a baseband or IF (intermediate frequency) signal, which is an output signal of the RF receiving chip, and the second integrated circuit chip 203 receives the RF. Except for the chip, all are the same, so description is omitted.

이러한, RF 수신 칩과 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩을 포함하는 디지털 튜너는 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조할 수 있다.The digital tuner including a demodulation chip for processing a baseband (IF) or IF (intermediate frequency) signal that is an output signal of the RF reception chip and the RF reception chip is S-DMB, T-DMB, ISDB-T, Wibro or DVB-H can be received and demodulated.

도 3은 본 발명에 의한 다른 실시예로 적층형 집적회로 패키지의 단면을 도시한 것이다.3 is a cross-sectional view of a stacked integrated circuit package according to another exemplary embodiment of the present invention.

도 2의 적층형 집적회로 칩에서 기판(301)에는 소정의 단위 소자(309)들이 더 포함되어 기판(301)과 전기적으로 연결된다. 소정의 단위 소자(309)는 임피던스 매칭을 하기 위한 마이크로 스트립라인이나 스트립 라인일 수 있고, 저항, 인덕터, 커패시터와 같은 수동소자 또는 필터일 수 있으며, 트랜지스터와 같은 능동소자도 가능하다.In the stacked integrated circuit chip of FIG. 2, the substrate 301 further includes predetermined unit elements 309 to be electrically connected to the substrate 301. The predetermined unit element 309 may be a micro strip line or a strip line for impedance matching, a passive element such as a resistor, an inductor, a capacitor, or a filter, and an active element such as a transistor may be used.

도 3에 도시된 바와 같이 기판(301) 위에는 제1 및 제2 집적회로 칩(302,303)과 단위 소자(309)들이 포함되고, 충전재(Encapsulation Material; 310)에 의해 전체가 패키징된다.As illustrated in FIG. 3, the first and second integrated circuit chips 302 and 303 and the unit elements 309 are included on the substrate 301, and are entirely packaged by an encapsulation material 310.

충전제는 집적회로 칩과 기판의 전기적 연결부를 보호하는 역할을 하는 것으로, 몰딩제(Molding Componens) 또는 공기(Air Cavity) 등이 사용될 수 있다. The filler serves to protect the electrical connection between the integrated circuit chip and the substrate, and a molding agent or an air cavity may be used.

또한, 도 3에 도시된 적층형 집적회로 패키지는 패키징시에 적층형태의 제1 집적회로 칩(302)과 제2 집적회로 칩(303) 부분만을 에폭시 몰딩(Epoxy molding)하고, 적층형태의 제1 집적회로 칩(302)과 제2 집적회로 칩(303) 및 소정의 단위 소 자(309)들이 포함된 기판(301) 전체를 금속캔(Matal can)으로 덮어 패키징할 수 있다.In addition, in the multilayer integrated circuit package illustrated in FIG. 3, only epoxy portions of the first integrated circuit chip 302 and the second integrated circuit chip 303 in a stacked form are epoxy molded at the time of packaging, and the stacked first integrated circuit package is shown in FIG. The entire substrate 301 including the integrated circuit chip 302, the second integrated circuit chip 303, and the predetermined unit elements 309 may be covered with a metal can to be packaged.

제1 집적회로 칩과 제2 집적회로 칩의 위치와 연결관계는 도 2의 설명부분과 동일하므로 여기서는 생략하기로 한다.Positions and connection relations of the first integrated circuit chip and the second integrated circuit chip are the same as the description of FIG. 2 and will not be described herein.

본 발명에 의하면, 집적회로 칩이 차지하는 면적을 줄일 수 있어 기기의 소형화에 기여하고, 비용을 절감하여 생산성을 향상시킬 수 있다.According to the present invention, the area occupied by the integrated circuit chip can be reduced, contributing to the miniaturization of the device, and reducing the cost, thereby improving productivity.

본 발명에 의하면 2개의 서로 다른 형태의 신호를 처리하는 집적회로 칩들 간의 전기적 간섭을 최소화하여 성능 열화를 방지할 수 있다.According to the present invention, performance degradation can be prevented by minimizing electrical interference between integrated circuit chips processing two different types of signals.

Claims (16)

기판;Board; 상기 기판과 표면실장기술(SMT; Surface Mount Technology)에 의한 기계적인 접촉에 의해 전기적으로 연결되는 제1 집적회로 칩; 및A first integrated circuit chip electrically connected to the substrate by mechanical contact by surface mount technology (SMT); And 상기 제1 집적회로 칩 위에 적층되며, 상기 기판과 와이어-본딩(Wire-Bonding)에 의해 전기적으로 연결되는 제2 집적회로 칩을 포함하는, 적층형 집적회로 칩.And a second integrated circuit chip stacked on the first integrated circuit chip, the second integrated circuit chip being electrically connected to the substrate by wire-bonding. 제1 항에 있어서,According to claim 1, 상기 제2 집적회로 칩은 상기 기판과 직접 와이어-본딩에 의해 전기적으로 연결되는, 적층형 집적회로 칩.And the second integrated circuit chip is electrically connected to the substrate by direct wire-bonding. 제1 항에 있어서,According to claim 1, 상기 기판은 접합점과 본딩점을 더 구비하고,The substrate further includes a bonding point and a bonding point, 상기 제1 집적회로 칩은 상기 기판의 상기 접합점과 표면실장기술에 의한 기계적 접촉에 의해 전기적으로 연결되는 접합점을 더 구비하고,The first integrated circuit chip further includes a junction point electrically connected to the junction point of the substrate by mechanical contact by surface mount technology, 상기 제2 집적회로 칩은 상기 기판의 상기 본딩점과 와이어-본딩에 의해 전기적으로 연결되는 본딩점을 더 구비하는, 적층형 집적회로 칩.And the second integrated circuit chip further comprises a bonding point electrically connected to the bonding point of the substrate by wire-bonding. 제1 항에 있어서,According to claim 1, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF(Radio Frequency) 신호를 수신하는 RF 수신 칩이고,Any one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving a radio frequency (RF) signal, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩인, 적층형 집적회로 칩.And the other of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip for processing a baseband (IF) or intermediate frequency (IF) signal, which is an output signal of the RF receiving chip. 제4 항에 있어서,The method of claim 4, wherein 상기 제1 집적회로 칩과 상기 제2 집적회로 칩은 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조하는, 적층형 집적회로 칩.And the first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro or DVB-H. 제1 항에 있어서,According to claim 1, 상기 기판은 BGA(Ball Grid Array), LGA(Land Grid Array), 다층 인쇄회로기판(PCB) 또는 LTCC(Low Temp. Co-fired Ceramics) 인, 적층형 집적회로 칩.The substrate is a ball grid array (BGA), a land grid array (LGA), a multi-layer printed circuit board (PCB), or Low Temp. Co-fired Ceramics (LTCC). 제1 항에 의한 적층형 집적회로 칩을 2개 이상 포함하는, 적층형 집적회로 패키지.A multilayer integrated circuit package comprising two or more stacked integrated circuit chips according to claim 1. 제7 항에 있어서,The method of claim 7, wherein 상기 적층형 집적회로 칩 중 적어도 하나 이상의 적층형 집적회로 칩에서,In at least one stacked integrated circuit chip of the stacked integrated circuit chip, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고,Any one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩인, 적층형 집적회로 패키지.And the other of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband (IF) signal or an intermediate frequency (IF) signal, which is an output signal of the RF receiver chip. 제1 항에 의한 적층형 집적회로 칩; 및A stacked integrated circuit chip according to claim 1; And 상기 기판과 전기적으로 연결되는 소정의 단위 소자를 포함하는, 적층형 집적회로 패키지.And a predetermined unit device electrically connected to the substrate. 제9 항에 있어서,The method of claim 9, 상기 단위 소자는 수동 소자 또는 능동 소자인, 적층형 집적회로 패키지.The unit device may be a passive device or an active device, stacked integrated circuit package. 제9 항에 있어서,The method of claim 9, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고,Any one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩인, 적층형 집적회로 패키지.And the other of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip that processes a baseband (IF) signal or an intermediate frequency (IF) signal, which is an output signal of the RF receiver chip. 제9 항에 있어서,The method of claim 9, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩은 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조하는, 적층형 집적회로 패키지.And the first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro or DVB-H. 기판;Board; 상기 기판 상에 적층되는 제1 집적회로 칩; 및A first integrated circuit chip stacked on the substrate; And 상기 제1 집적회로 칩 위에 적층되는 제2 집적회로 칩을 포함하고,A second integrated circuit chip stacked on the first integrated circuit chip, 상기 제2 집적회로 칩만이 상기 기판과 와이어-본딩(Wire-Bonding)에 의해 전기적으로 연결되는, 적층형 집적회로 칩.And only the second integrated circuit chip is electrically connected to the substrate by wire-bonding. 제13 항에 있어서,The method of claim 13, 상기 제2 집적회로 칩은 상기 기판과 직접 와이어-본딩에 의해 전기적으로 연결되는, 적층형 집적회로 칩.And the second integrated circuit chip is electrically connected to the substrate by direct wire-bonding. 제13 항에 있어서,The method of claim 13, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 어느 하나는 RF 신호를 수신하는 RF 수신 칩이고,Any one of the first integrated circuit chip and the second integrated circuit chip is an RF receiving chip for receiving an RF signal, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩 중 다른 하나는 상기 RF 수신 칩의 출력신호인 베이스밴드(Baseband) 또는 IF(Intermediate Frequency) 신호를 처리하는 복조 칩인, 적층형 집적회로 칩.And the other of the first integrated circuit chip and the second integrated circuit chip is a demodulation chip for processing a baseband (IF) or intermediate frequency (IF) signal, which is an output signal of the RF receiving chip. 제13 항에 있어서,The method of claim 13, 상기 제1 집적회로 칩과 상기 제2 집적회로 칩은 S-DMB, T-DMB, ISDB-T, Wibro 또는 DVB-H 를 수신하여 복조하는, 적층형 집적회로 칩.And the first integrated circuit chip and the second integrated circuit chip receive and demodulate S-DMB, T-DMB, ISDB-T, Wibro or DVB-H.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101051576B1 (en) * 2009-09-15 2011-07-22 삼성전기주식회사 Optimized battlefield power package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021989B (en) * 2012-12-11 2014-07-30 矽力杰半导体技术(杭州)有限公司 Multiple-component chip packaging structure

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6384128A (en) * 1986-09-29 1988-04-14 Oki Electric Ind Co Ltd Hybrid integrated circuit device
JPH0983398A (en) * 1995-09-20 1997-03-28 Mitsubishi Electric Corp Radio communication equipment
JPH11219984A (en) * 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor
JP3891678B2 (en) * 1998-03-11 2007-03-14 松下電器産業株式会社 Semiconductor device
US6914950B1 (en) * 2000-07-31 2005-07-05 Lyrtech Inc. Multi-protocol receiver
JP2002141757A (en) * 2000-08-08 2002-05-17 Tdk Corp Power amplifier module, dielectric board for power amplifier module and communication terminal
JP2002124538A (en) * 2000-10-12 2002-04-26 Eastern Co Ltd Circuit board
JP4126891B2 (en) * 2001-08-03 2008-07-30 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP2004296613A (en) * 2003-03-26 2004-10-21 Renesas Technology Corp Semiconductor device
JP2004296719A (en) * 2003-03-26 2004-10-21 Renesas Technology Corp Semiconductor device
JP2005079385A (en) * 2003-09-01 2005-03-24 Toshiba Corp Optical semiconductor device and optical signal input/output device
JP4159960B2 (en) * 2003-09-30 2008-10-01 シャープ株式会社 Tuner IC package and digital broadcast receiver subassembly
JP4260617B2 (en) * 2003-12-24 2009-04-30 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP2005303056A (en) * 2004-04-13 2005-10-27 Toshiba Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101051576B1 (en) * 2009-09-15 2011-07-22 삼성전기주식회사 Optimized battlefield power package

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