CN101047160A - Semiconductor connection line packaging structure and its method of connection with IC - Google Patents

Semiconductor connection line packaging structure and its method of connection with IC Download PDF

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Publication number
CN101047160A
CN101047160A CNA2006101276758A CN200610127675A CN101047160A CN 101047160 A CN101047160 A CN 101047160A CN A2006101276758 A CNA2006101276758 A CN A2006101276758A CN 200610127675 A CN200610127675 A CN 200610127675A CN 101047160 A CN101047160 A CN 101047160A
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CN
China
Prior art keywords
package substrates
integrated circuit
semiconductor line
encapsulating structure
connection pad
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Pending
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CNA2006101276758A
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Chinese (zh)
Inventor
张仕承
胡琦伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101047160A publication Critical patent/CN101047160A/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a wire bond semiconductor package structure and a method for connecting the package structure and an integrated circuit. The hybrid package includes a package substrate, a plurality of flip chip pads, and a plurality of wire-bond pads. The package substrate has at least one void or opening with a top side and a bottom side. The flip chip pads mounted on the top side of the package substrate, while the wire-bond pads mounted on the bottom side of the package substrate. The wire bond semiconductor package structure and the method for connecting the package structure and an integrated circuit of the invention allows more power/earth pads and signal output/input pads in a single package structure.

Description

Semiconductor line encapsulating structure and with the method for attachment of integrated circuit
Technical field
The invention relates to a kind of semiconductor packages, and be particularly to a kind of integrated circuit encapsulation that utilizes wire bonds and flip-chip bonded and can save the space.
Background technology
In the field of integrated circuit encapsulation, except pursuing littler package dimension, encapsulated integrated circuit not only needs power supply and ground connection, and also needs output and input signal.Therefore, the target of integrated circuit encapsulation institute desire pursuit often can not obtain simultaneously.
General traditional flip-chip bonded (flip-chip) encapsulating structure 1000, as shown in Figure 1, integrated circuit substrate 1002 is connected to package substrates 1006 by contact point (contacts) 1004, wherein contact point 1004 is the grafting material of conductivity, and this package substrates 1006 connects as external signal with ball grid array 1008.
General traditional wire bonds (wire-bond) encapsulating structure 2000, as shown in Figure 2, in bonding wire encapsulating structure 2000, integrated circuit substrate 2002 has contact mat 2010, and contact mat 2010 is connected with contact mat 2014 on the package substrates 2006 by lead 2012, and package substrates 2006 connects as external signal with ball grid array 2008.
Summary of the invention
A purpose of the present invention is to provide a kind of integrated circuit package structure of saving the space.According to above-mentioned purpose, the invention provides a kind of semiconductor line encapsulating structure of integrated circuit, comprising: a package substrates, this package substrates has a hole at least, and this package substrates has a top and a bottom; A plurality of upside-down mounting connection pads be fixed in the bottom of this package substrates, and those upside-down mounting connection pads are in order to accept an integrated circuit; And a plurality of bonding wire connection pads, be fixed in the top of this package substrates.
Semiconductor line encapsulating structure of the present invention comprises that more a ball grid array is fixed in the top of this package substrates, and this package substrates and described upside-down mounting connection pad and bonding wire connection pad transmit the signal of telecommunication mutually to this ball grid array.
Semiconductor line encapsulating structure of the present invention, wherein said upside-down mounting connection pad is by a contact point, and in order to accept this integrated circuit, this contact point is the grafting material of tool conductivity.
Semiconductor line encapsulating structure of the present invention, wherein said bonding wire connection pad is electrically connected to this integrated circuit by a lead, and this lead is connected to this integrated circuit via the hole of this package substrates.
Semiconductor line encapsulating structure of the present invention more comprises an encapsulating material, the hole of dielectric this package substrates of encapsulation of this encapsulating material.
Semiconductor line encapsulating structure of the present invention, wherein this package substrates has more than one hole.
Semiconductor line encapsulating structure of the present invention, wherein this package substrates is in order to accept more than one integrated circuit.
Semiconductor line encapsulating structure of the present invention, wherein this encapsulating material comprises epoxy resin, epoxy resin envelope membranization compound or polyimides sticker.
The present invention provides the method for attachment of a kind of semiconductor line encapsulation with integrated circuit again, comprise: fix the bottom of an integrated circuit in a package substrates, this package substrates has the bottom that a plurality of upside-down mounting connection pads are fixed in this package substrates, and those upside-down mounting connection pads are in order to accept this integrated circuit; Connect a plurality of joint sheets of a plurality of bonding wire connection pads to this integrated circuit by a plurality of leads, wherein those bonding wire connection pads are fixed in the top of this package substrates, and those leads pass a hole of this package substrates; And encapsulate those leads and this hole with a non-conductive material.
The method of attachment of semiconductor line encapsulation of the present invention and integrated circuit, wherein this non-conductive material comprises epoxy resin, epoxy resin envelope membranization compound or polyimides sticker.
The method of attachment of semiconductor line encapsulation of the present invention and integrated circuit, wherein said upside-down mounting connection pad comprises gold, copper, aluminium or nickel.
The method of attachment of semiconductor line encapsulation of the present invention and integrated circuit, wherein this package substrates comprises polyimide tape, epoxy resin copper-clad plate, organic multilayer plate, ceramic bases.
Semiconductor line encapsulating structure provided by the present invention and with the method for attachment of integrated circuit, can make to have more power supply/ground mat and signal output/input pad in the single encapsulating structure.
Description of drawings
Fig. 1 is the profile of flip-chip bonded (flip-chip) encapsulating structure that illustrates known technology;
Fig. 2 is the profile of wire bonds (wire-bond) encapsulating structure that illustrates known technology;
Fig. 3 is the profile that illustrates according to the hybrid package structure 3000 of the flip-chip bonded of the embodiment of the invention and wire bonds;
Fig. 4 is the vertical view that illustrates according to the hybrid package structure of the flip-chip bonded of Fig. 3 and wire bonds;
It is the vertical view that illustrates according to the hybrid package structure of the upside-down mounting of the embodiment of the invention and wire bonds for Fig. 5;
It is to illustrate according to the embodiment of the invention for Fig. 6, the hybrid package structure of the upside-down mounting of single IC for both and wire bonds;
It is to illustrate according to the embodiment of the invention for Fig. 7, the hybrid package structure of the upside-down mounting of a plurality of integrated circuits and wire bonds;
It is the processing flow that illustrates the hybrid package structure of the upside-down mounting of the example according to the present invention and wire bonds for Fig. 8.
Embodiment
General traditional bonding wire (wire-bond) encapsulation can't have the power supply/ground mat of equal number with upside-down mounting (flip-chip) encapsulation; Yet flip-chip packaged can't be with the substrate acquisition of minimum layer and the connection gasket or the signal output/input pad of bonding wire encapsulation equal number.The embodiment of the invention provides a kind of hybrid package structure with bonding wire and flip-chip bonded, so, can have more power supply/ground mat and signal output/input pad in single encapsulating structure.
Following preferred embodiment provides a kind of structure and processing procedure of the hybrid package integrated circuit with bonding wire and flip-chip bonded.The method of operation of the embodiment of the invention is only as example, but not in order to limit the present invention.
See also Fig. 3, it is the profile that illustrates according to the hybrid package structure 3000 of the flip-chip bonded of the embodiment of the invention and wire bonds.According to embodiments of the invention, this mixing connected structure can provide more power supply/ground mat and signal output/input pad in single encapsulating structure.In one embodiment, integrated circuit (IC) externally connects by wire bonds, as the encapsulating structure of wire bonds, has a hole or opening to make bonding wire reach purpose of connecting in the package substrates.And integrated circuit has Metal Contact, as the flip-chip bonded encapsulating structure.
The surface of integrated circuit 3002 has bonding wire connection pad 3010 and upside-down mounting connection pad.Contact point (contacts) 3004 is arranged on the upside-down mounting connection pad 3003, and is connected to package substrates material 3006, and as the flip-chip bonded encapsulation, wherein, contact point 3004 is grafting materials of conductivity.Making contact point 3004 can utilize any known method to finish, as shown in Figure 3, C4 (Controlled-Collapse Chip Connection, also being called control punctures wafer and engages) solder ball (solder ball) can be used as contact point 3004, is connected on the relative joint sheet of integrated circuit 3002 and package substrates 3006.Solder ball not only can transmit signal and power supply, and it also can provide mechanical adhesion function.
Package substrates 3006 can be any known integrated circuit package substrates, and has a hole or emptying aperture (cavity, hole, void) at least among package substrates 3006.The hole 3007 of this package substrates 3006 gets another surface to package substrates 3006, the surface of the connection integrated circuit 3002 so that bonding wire 3012 passes hole 3007.In other embodiments, package substrates can have more than one hole.
Bonding wire 3012 provides the bonding wire connection pad 3010 on the integrated circuit 3002 to be connected to each other with bonding wire connection pad 3014 on the package substrates 3006.Package substrates 3006 provides various signal paths (signal path) 3018 to connect bonding wire connection pad 3014 and contact point 3004 to ball grid array (BGA) contact point 3008.Ball grid array contact point 3008 can encapsulate substrate 3006 certainly and transmit input/output signal electrically contacting to the integrated circuit outside.
Utilize a dielectric encapsulating material 3016, epoxy resin for example, with encapsulated integrated circuit 3002, bonding wire connection pad 3010,3014 and bonding wire 3012, perhaps, can utilize epoxy resin other encapsulating materials in addition, for example, epoxy resin envelope membranization compound, polyimides sticker or other similar materials.Encapsulating material 3016 can avoid moisture or pollution etc. to cause possible injury.
In said structure, package substrates 3006 can comprise polyimide tape (polyimide tape), epoxy resin copper-clad plate (FR-4), organic multilayer plate (organicbuild-up), ceramic bases or other similar materials; Contact point 3008 can comprise congruent melting (eutectic)/height lead/unleaded solder ball, nickel billon/congruent melting (eutectic)/height lead/unleaded scolding tin C4 projection or other similar materials; Bonding wire can comprise gold or other electric conducting materials; The bonding wire connection pad can wrap yellowcorall euphorbia leaf and root-bark (Au plate) joint sheet, copper/aluminium/nickel gold joint sheet or other electric conducting materials.
Said structure may exist bonding wire connection pad 3010, the bonding wire 3012 of contact point 3004, ball grid array contact point 3008, the integrated circuit of a plurality of integrated circuits, the bonding wire connection pad 3014 of package substrates.The quantity of those elements is decided by the demand of integrated circuit 3002 and encapsulation.
See also Fig. 4, it is the vertical view that illustrates according to the hybrid package structure of the flip-chip bonded of Fig. 3 and wire bonds.According to embodiments of the invention, this structure can make has more power supply/ground mat and signal output/input pad in the single encapsulating structure.In by vertical view as seen, the top of package substrates 3006 has ball grid array contact point 3008, and has hole 3007 among the package substrates 3006 and run through wherein to be received in the integrated circuit under the package substrates 3006.Hole 3007 gets so that bonding wire 3012 connects the bonding wire connection pad 3010 of integrated circuits and the bonding wire connection pad 3014 of package substrates.Various signal paths 3018 can connect bonding wire connection pad 3014 to ball grid array contact point 3008.
The hybrid package structure of upside-down mounting and wire bonds also can have a plurality of holes within the package substrates with the supply more line of integrated circuit or a plurality of integrated circuits can be gathered in single encapsulating structure.Fig. 5 to Fig. 7 is the encapsulating structure that illustrates according to the embodiment of the invention, this with Fig. 3 in similar elements adopt identical label.
See also Fig. 5, it is the vertical view that illustrates according to the hybrid package structure 5000 of the upside-down mounting of the embodiment of the invention and wire bonds, and this structure can make has more power supply/ground mat and signal output/input pad in the single encapsulating structure.One package substrates 3006 can be in conjunction with a plurality of integrated circuit 3002A, 3002B.Though, only illustrate two integrated circuit 3002A, 3002B among the figure, yet, can needs according to circumstances and use any amount of integrated circuit 3002.A plurality of hole 3007A, 3007B, 3007C can be formed in the package substrates 3006, so that the connection between package substrates and the integrated circuit to be provided, and available boring of the formation of hole 3007A, 3007B, 3007C or additive method.Hole is not defined as rectangle, and it can be Any shape, as long as the linkage function that hole can make bonding wire smoothly.
See also Fig. 6, it is to illustrate according to the embodiment of the invention, and the hybrid package structure of the upside-down mounting of single IC for both and wire bonds, this structure have power supply/ground mat and the signal output/input pad of a plurality of holes so that greater number to be provided.This embodiment explanation can have a plurality of holes so that the linkage function of bonding wire is carried out smoothly in package substrates.Can have plural hole 3007 in the package substrates 3006, and any amount of hole can be present among the package substrates 3006.Fig. 6 can be considered the profile of Fig. 5, from the integrated circuit 3002A crosscut of Fig. 5 and visible hole 3007A, 3007B.
See also Fig. 7, it is to illustrate according to the embodiment of the invention, and the hybrid package structure of the upside-down mounting of a plurality of integrated circuits and wire bonds, this structure have power supply/ground mat and the signal output/input pad of a plurality of holes so that greater number to be provided.This embodiment illustrates that a plurality of integrated circuits can be arranged under the package substrates 3006.Can have plural integrated circuit 3006 in the package substrates 3006, and any amount of integrated circuit can be present in the package substrates 3006.Fig. 7 can be considered the profile of Fig. 5, from the integrated circuit 3002A-3002B crosscut of Fig. 5 and visible hole 3007A, 3007C.
See also Fig. 8, it is the processing flow 8000 that illustrates the hybrid package structure of the upside-down mounting of the example according to the present invention and wire bonds.Step 8002 is that bonding wire connection pad and upside-down mounting connection pad are set on the surface of one or more integrated circuit; Step 8004 provides one to be had the package substrates of hole or provides a base material to have drillable space; Step 8006 is the one sides that integrated circuit are connected in this package substrates with the method for flip-chip bonded.If there are a plurality of integrated circuits need be engaged in this package substrates, then constantly carry out engagement step and all engage up to all integrated circuits and finish, as step 8008.Step 8010 is to be connected to the another side of package substrates through hole with bonding wire at the bonding wire connection pad of integrated circuit surface.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
1000: the flip-chip bonded encapsulating structure
1002: integrated circuit substrate
1004: contact point
1006: package substrates
1008: BGA
2000: the wire bonds encapsulating structure
2002: integrated circuit substrate
2006: package substrates
2008: ball grid array
2010: contact mat
2012: lead
2014: contact mat
3000: the hybrid package structure of flip-chip bonded and wire bonds
3002: integrated circuit
3002A, 3002B: integrated circuit
3003: the upside-down mounting connection pad
3004: contact point
3006: package substrates
3007: hole
3007A, 3007B, 3007C: hole
3008: ball grid array (BGA) contact point
3010: the bonding wire connection pad
3012: bonding wire
3014: the bonding wire connection pad
3016: encapsulating material
3018: signal path
8000: processing flow
8002,8004,8006,8008,8010: fabrication steps

Claims (12)

1. a semiconductor line encapsulating structure is characterized in that, described semiconductor line encapsulating structure comprises:
One package substrates, this package substrates has a hole at least, and this package substrates has a top and a bottom;
A plurality of upside-down mounting connection pads be fixed in the bottom of this package substrates, and described upside-down mounting connection pad are in order to accept an integrated circuit; And
A plurality of bonding wire connection pads are fixed in the top of this package substrates.
2. semiconductor line encapsulating structure according to claim 1 is characterized in that, comprises that more a ball grid array is fixed in the top of this package substrates, and this package substrates and described upside-down mounting connection pad and bonding wire connection pad transmit the signal of telecommunication mutually to this ball grid array.
3. semiconductor line encapsulating structure according to claim 2 is characterized in that, described upside-down mounting connection pad is by a contact point, and in order to accept this integrated circuit, this contact point is the grafting material of tool conductivity.
4. semiconductor line encapsulating structure according to claim 3 is characterized in that described bonding wire connection pad is electrically connected to this integrated circuit by a lead, and this lead is connected to this integrated circuit via the hole of this package substrates.
5. semiconductor line encapsulating structure according to claim 4 is characterized in that, more comprises an encapsulating material, the hole of dielectric this package substrates of encapsulation of this encapsulating material.
6. semiconductor line encapsulating structure according to claim 5 is characterized in that this package substrates has more than one hole.
7. semiconductor line encapsulating structure according to claim 6 is characterized in that this package substrates is in order to accept more than one integrated circuit.
8. semiconductor line encapsulating structure according to claim 7 is characterized in that, this encapsulating material comprises epoxy resin, epoxy resin envelope membranization compound or polyimides sticker.
9. the method for attachment of semiconductor line encapsulation and integrated circuit is characterized in that described semiconductor line encapsulation comprises with the method for attachment of integrated circuit:
Fix the bottom of an integrated circuit in a package substrates, this package substrates has the bottom that a plurality of upside-down mounting connection pads are fixed in this package substrates, and described upside-down mounting connection pad is in order to accept this integrated circuit;
Connect a plurality of joint sheets of a plurality of bonding wire connection pads to this integrated circuit by a plurality of leads, wherein said bonding wire connection pad is fixed in the top of this package substrates, and described lead passes a hole of this package substrates; And
Encapsulate described lead and this hole with a non-conductive material.
10. the method for attachment of semiconductor line encapsulation according to claim 9 and integrated circuit is characterized in that this non-conductive material comprises epoxy resin, epoxy resin envelope membranization compound or polyimides sticker.
11. the method for attachment of semiconductor line encapsulation according to claim 10 and integrated circuit is characterized in that described upside-down mounting connection pad comprises gold, copper, aluminium or nickel.
12. the method for attachment of semiconductor line encapsulation according to claim 11 and integrated circuit is characterized in that this package substrates comprises polyimide tape, epoxy resin copper-clad plate, organic multilayer plate, ceramic bases.
CNA2006101276758A 2006-03-29 2006-09-05 Semiconductor connection line packaging structure and its method of connection with IC Pending CN101047160A (en)

Applications Claiming Priority (2)

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US11/393,301 2006-03-29
US11/393,301 US20070235862A1 (en) 2006-03-29 2006-03-29 Hybrid flip-chip and wire-bond connection package system

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CN102983087A (en) * 2011-09-06 2013-03-20 台湾积体电路制造股份有限公司 Flip-chip BGA assembly process
CN109003949A (en) * 2018-08-01 2018-12-14 灿芯半导体(上海)有限公司 A kind of interface that bonding line encapsulation is shared with flip-chip packaged
CN112542442A (en) * 2020-12-25 2021-03-23 南京蓝洋智能科技有限公司 Low-cost multi-chip high-speed high-bandwidth interconnection structure

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KR20090039411A (en) * 2007-10-18 2009-04-22 삼성전자주식회사 Semiconductor package, module, system having a solder ball being coupled to a chip pad and manufacturing method thereof

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CN102983087A (en) * 2011-09-06 2013-03-20 台湾积体电路制造股份有限公司 Flip-chip BGA assembly process
CN102983087B (en) * 2011-09-06 2015-06-10 台湾积体电路制造股份有限公司 Flip-chip BGA assembly process
CN109003949A (en) * 2018-08-01 2018-12-14 灿芯半导体(上海)有限公司 A kind of interface that bonding line encapsulation is shared with flip-chip packaged
CN112542442A (en) * 2020-12-25 2021-03-23 南京蓝洋智能科技有限公司 Low-cost multi-chip high-speed high-bandwidth interconnection structure

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