CN1920931B - 液晶驱动电路 - Google Patents
液晶驱动电路 Download PDFInfo
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Abstract
本发明的液晶驱动电路,在4个输出晶体管(TR1~TR4)的每一个中,设置有每个输出晶体管2个、总计8个的控制晶体管。按照点信号(DA)以及场信号(DF),使8个控制晶体管导通截止,从4个输出晶体管(TR1~TR4)中选择1个输出晶体管。通过使施加在各输出晶体管(TR1~TR4)上的(DFp、DFBp)的上升沿和(DFn、DFBn)的下降沿变得急剧,将各输出晶体管提前从导通转移到截止。此外,通过使(DFp、DFBp)的下降沿和(DFn、DFBn)的上升沿变得缓慢,使各输出晶体管延迟从截止转移到导通。从而,在液晶驱动电路中,大幅削减输出控制电路的晶体管数目,实现耗电的减小以及驱动电压的稳定化。
Description
技术领域
本发明涉及液晶驱动电路,尤其涉及STN-LCD面板(STN-LCD是超扭曲向列液晶)用的驱动电路。
背景技术
一般来说,STN-LCD面板用的驱动电路,分为公共驱动器(commondriver)和节段驱动器(segment driver)两种。公共驱动器和节段驱动器,将多位的驱动信号向分别对应的数据线(行线或列线)输出,每一位具备4个输出晶体管,通过使这些输出晶体管中的一个导通,其他的输出晶体管截止,而输出V1、V2、V3、V4的4个驱动电压中的任一个的驱动电压。在行线与列线的交叉点处形成有液晶电容,通过在该液晶电容中施加所述驱动电压,进行点矩阵的液晶显示。
图4是表示公共驱动器的一位的输出控制电路的电路图。该公共驱动器,具备将第1驱动电压V1施加在其源极上的第1输出晶体管TR1、将第2驱动电压V2施加在其源极上的第2输出晶体管TR2、将第3驱动电压V3施加在其源极上的第3输出晶体管TR3和将第4驱动电压V4施加在其源极上的第4输出晶体管TR4。这4个输出晶体管TR1~TR4的漏极与输出端子P公共连接。第1以及第3的输出晶体管TR1、TR3为P沟道型MOS晶体管,第2及第4的输出晶体管TR2、TR4为N沟道型MOS晶体管。
此外,第1输出晶体管TR1的栅极电压通过第1NAND电路50的输出控制,第2输出晶体管TR2的栅极电压通过第2NAND电路51的输出控制,第3输出晶体管TR3的栅极电压通过第1NOR电路52的输出控制,第4输出晶体管TR4的栅极电压通过第2NOR电路53的输出控制。
而且,在第1NAND电路50中输入作为显示信号的点(dot)信号DA以及场(field)信号DF,在第2NAND电路51中输入对点信号DA进行了反相的反相点信号DAB以及对场信号DF进行了反相的反相场信号DFB。在第1NOR电路52中输入点信号DA以及反相场信号DFB,在第2NOR电路53中输入反相点信号DAB以及场信号DF。
该公共驱动器的真值表如表2所示。节段驱动器也具有与公共驱动器相同的输出控制电路的结构,但设定为DFB=DF。
专利文献1:特开平11-510622号公报。
但是,现有的液晶驱动电路由两个NAND电路(第1以及第2NAND电路50、51)和两个NOR电路(第1以及第2NOR电路52、53),进行输出晶体管的导通截止控制,因此该输出控制电路部分的晶体管数目多达16个。从而,存在驱动电路的LSI的芯片尺寸变大的问题。尤其由于驱动电压为30V~40V的高电压,因此不但输出晶体管,而且构成NAND电路或NOR电路的晶体管也需要用占有面积大的高耐压晶体管设计,晶体管数目的增加对芯片尺寸带来较大的影响。
此外,随着点信号DA和场信号DF的转移(从低向高的转移或者从高向低的转移),NAND电路或NOR电路以及输出晶体管的贯通电流或充放电电流变地非常大,导致耗电的增大以及驱动电压的电压变动。
发明内容
本发明正是为了解决上述问题而提出的。
在此,本发明的液晶驱动电路,具备:在源极上分别施加4个驱动电压,漏极与一个输出端子互相公共连接的4个输出晶体管;和输出控制电路,由多个控制晶体管构成,按照点信号以及作为其反相信号的反相点信号,从所述4个输出晶体管中选择两个输出晶体管,还按照场信号以及作为其反相信号的反相场信号,从按照所述点信号以及所述反相点信号所选择的两个输出晶体管中选择一个输出晶体管,将所述4个驱动电压中的一个驱动电压输出到所述输出端子,对所述场信号或者所述反相场信号的上升沿或下降沿的时序进行调整,使各所述输出晶体管提前从导通转移到截止,使各输出晶体管延迟从截止转移到导通,以防止在所述场信号或者所述反相场信号转移时,贯通电流流过所述输出晶体管。
此外,所述输出控制电路,与所述4个输出晶体管的各个栅极连接,具有按照所述点信号以及所述反相点信号互补地导通的一对控制晶体管,按照下述方式工作:所述一对控制晶体管的一方导通时,使所述输出晶体管截止,所述一对控制晶体管的另一方导通时,在所述输出晶体管的栅极上施加所述场信号或者所述反相场信号。
还有,对所述场信号或者所述反相场信号的上升沿或下降沿的时序进行调整,以防止在所述场信号或者所述反相场信号转移时,贯通电流流过所述输出晶体管。
(发明效果)
根据本发明的液晶驱动电路,由于输出控制电路不采用NAND电路或NOR电路,而只由多个控制晶体管构成,因此与以往相比,能够大幅削减晶体管的数目。此外,在场信号或反相场信号转移时,调整场信号或反相场信号的上升沿或下降沿的时序,因此能够防止贯通电流流过输出晶体管,并能实现耗电的降低以及驱动电压的稳定化。
附图说明
图1是表示有关本发明的实施方式的点矩阵型的STN-LCD面板的结构的图。
图2是表示有关本发明的实施方式的公共驱动器CD的一个公共驱动器/单元CDU的电路图。
图3是有关本发明的实施方式的公共驱动器CD的一个公共驱动器/单元CDU的动作说明图。
图4是表示现有的公共驱动器的一位的输出控制电路的电路图。
图中:10-行线;11-列线;CD-公共驱动器;SDU-节段驱动器;12-输出控制电路;13-场信号发生电路;P-输出端子。
具体实施方式
接下来,参照附图对本发明的实施方式进行说明。图1是表示点矩阵型的STN-LCD面板的结构的图。该STN-LCD面板中,在显示区域100的周边设置有公共驱动器CD和节段驱动器SD。公共驱动器CD具有相同电路结构的多个公共驱动器/单元CDU。在各个驱动器/单元CDU中,被供给点信号DA、与各个驱动器/单元CDU公共的场信号DF以及反相场信号DFB。节段驱动器SD也具有相同电路结构的多个节段驱动器/单元SDU,但场信号DF和反相场信号DFB被设定为相同信号。
驱动器/单元CDU的输出信号输出到分别对应的行线10,节段驱动器/单元SDU的输出信号输出到分别对应的列线11。在行线10与列线11的各交叉点形成有液晶电容LC,按照各交叉点的行线10和列线11的电压,进行黑或白的液晶显示。
图2是公共驱动器CD的一个公共驱动器/单元CDU的电路图。第1至第4的输出晶体管TR1~TR4的漏极与输出端子P公共连接。在第1输出晶体管TR1的源极上施加第1驱动电压V1,在第2输出晶体管TR2的源极上施加第2驱动电压V2,在第3输出晶体管TR3的源极上施加第3驱动电压V3,在第4输出晶体管TR4的源极上施加第4驱动电压V4。第1以及第3输出晶体管TR1、TR3为P沟道型MOS晶体管,第2以及第4输出晶体管TR2、TR4为N沟道型MOS晶体管。这4个输出晶体管TR1~TR4的漏极与输出端子P公共连接。
而且,设置有只使这些第1到第4的输出晶体管TR1~TR4中、一个晶体管导通的输出控制电路12。输出控制电路12由8个控制晶体管构成。在第1输出晶体管TR1的栅极公共连接着第1控制晶体管TRP1和第2控制晶体管TRP2的漏极。在第1控制晶体管TRP1的栅极上施加点信号DA,在其源极上施加电源电压Vdd。在第2控制晶体管TRP2的栅极上施加反相点信号DAB,在其源极上施加场信号DFp。
在第3输出晶体管TR3的栅极公共连接有第3控制晶体管TRP3和第4控制晶体管TRP4的漏极。在第3控制晶体管TRP3的栅极上施加反相点信号DAB,在其源极上施加电源电压Vdd。在第4控制晶体管TRP4的栅极上施加点信号DA,在其源极上施加反相场信号DFBp。在此,第1至第4的控制晶体管TRP1、TRP2、TRP3、TRP4为P沟道型MOS晶体管。此外,电源电压Vdd为与第1以及第3驱动电压V1、V3相同或比其高的电压。
在第2输出晶体管TR2的栅极公共连接有第5控制晶体管TRN1和第6控制晶体管TRN2的漏极。在第5控制晶体管TRN1的栅极上施加反相点信号DAB,在其源极上施加接地电压Vss。在第6控制晶体管TRN2的栅极上施加点信号DA,在其源极上施加场信号DFn。
在第4输出晶体管TR4的栅极公共连接有第7控制晶体管TRN3和第8控制晶体管TRN4的漏极。在第7控制晶体管TRN3的栅极上施加点信号DA,在其源极上施加接地电压Vss。在第8控制晶体管TRN4的栅极上施加反相点信号DAB,在其源极上施加反相场信号DFBn。
在此,第5至第8控制晶体管TRN1、TRN2、TRN3、TRN4为N沟道型MOS晶体管。此外,接地电压Vss为与第2以及第4驱动电压V2、V4相同,或比其低的电压。
此外,设置有产生场信号DFp、DFn以及反相场信号DFBp、DFBn的场信号发生电路13。DFp、DFn为相同的逻辑值,DFBp、DFBn为相同的逻辑值,但为了防止输出晶体管的贯通电流,如后所述,调整这些信号的下降沿、上升沿。
接下来,参照图3,对上述的公共驱动器/单元CDU的动作进行说明。从逻辑上来说,按照点信号DA,选择第1至第4输出晶体管TR1~TR4中的两个输出晶体管,从这两个输出晶体管中根据场信号DF的逻辑选择一个。
点信号DA为低电平(L=Vss)时,TRP1导通,TRP2截止,因此第1输出晶体管TR1的栅极电压变为高电平(H=Vdd),第1输出晶体管TR1截止。此外,TRP3截止,TRP4导通,因此第3输出晶体管TR3的栅极电压变为DFBp。此外,由于TRN4导通,TRN3截止,因此第4输出晶体管TR4的栅极电压DFBn。此外,TRN2截止,TRN1导通,因此第2输出晶体管TR2的栅极电压变为低电平,第2输出晶体管TR2截止。因此,如图3(a)所示,点信号DA为低电平(L=Vss)时,TR1以及TR2截止,TR3的栅极电压为DFBp,TR4的栅极电压为DFBn。即由于DFBp与DFBn为相同的逻辑值DFB,结果根据DFB的信号逻辑,选择驱动电压V3或V4,向输出端子P输出。
接下来,在点信号DA为高电平(H=Vdd)时,TRP1截止,TRP2导通,因此第1输出晶体管TR1的栅极电压变为DFp。此外TRP3导通,TRP4截止,因此第3输出晶体管TR3的栅极电压变为高电平,第3输出晶体管TR3截止。此外,由于TRN4截止,TRN3导通,因此第4输出晶体管TR4的栅极电压变为低电平,第4输出晶体管TR4截止。此外,由于TRN2导通、TRN1截止,因此第2输出晶体管TR2的栅极电压变为DFn。因此,如图3(b)所示,点信号DA为高电平(L=Vdd)时,TR3以及TR4截止,TR1的栅极电压变为DFp,TR2的栅极电压变为DFn。即由于DFp与DFn为相同逻辑值DF,因此结果根据DF的信号逻辑,选择驱动电压V1或V2,向输出端子P输出。
根据以上的逻辑,公共驱动器/单元CDU的真值表如表1所示。另外,关于节段驱动器/单元SDU,按照场信号DF和反相场信号DFB为相同信号的方式设定。
表1
*逻辑上,DFp=DFn=DF、DFBp=DFBn=DFB
接下来,考虑各信号的时序,则第1至第4输出晶体管TR1~TR4的栅极电压的转移,根据场信号DF的信号能力、控制晶体管TRP2、TRP4、TRN2、TRN4的驱动能力以及第1至第4输出晶体管TR1~TR4的栅极电容和布线电容决定。其中,支配的要素为场信号DF的信号能力。在此,通过使DFp、DFBp的上升沿和DFn、DFBn的下降沿变地急剧,将各输出晶体管提前从导通转移到截止,使DFp、DFBp的下降沿和DFn、DFBn的上升沿变得缓慢,使各输出晶体管延迟从截止转移到导通,从而能够防止在各输出晶体管中流过贯通电流。
此外,根据场信号发生电路13,通过在点信号DA的转移期间之间固定为DFp=DFBp=高电平(H)、DFn=DFBn=低电平(L),使输出晶体管TR1~TR4截止,也可防止点信号DA的转移期间中产生贯通电流。
Claims (3)
1.一种液晶驱动电路,具备:
在源极上分别施加4个驱动电压,漏极与一个输出端子互相公共连接的4个输出晶体管;和
输出控制电路,由多个控制晶体管构成,按照点信号以及作为其反相信号的反相点信号,从所述4个输出晶体管中选择两个输出晶体管,还按照场信号以及作为其反相信号的反相场信号,从按照所述点信号以及所述反相点信号所选择的两个输出晶体管中选择一个输出晶体管,将所述4个驱动电压中的一个驱动电压输出到所述输出端子,
对所述场信号或者所述反相场信号的上升沿或下降沿的时序进行调整,使各所述输出晶体管提前从导通转移到截止,使各输出晶体管延迟从截止转移到导通,以防止在所述场信号或者所述反相场信号转移时,贯通电流流过所述输出晶体管。
2.根据权利要求1所述的液晶驱动电路,其特征在于,
所述输出控制电路,与所述4个输出晶体管的各个栅极连接,具有按照所述点信号以及所述反相点信号互补地导通的一对控制晶体管,按照下述方式工作:所述一对控制晶体管的一方导通时,使所述输出晶体管截止,所述一对控制晶体管的另一方导通时,在所述输出晶体管的栅极上施加所述场信号或者所述反相场信号。
3.根据权利要求1或2所述的液晶驱动电路,其特征在于,
在所述点信号的转移期间,按照使所述输出晶体管截止的方式固定所述场信号或者所述反相场信号的逻辑。
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JP2005243810 | 2005-08-25 | ||
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JP2005243810A JP4803711B2 (ja) | 2005-08-25 | 2005-08-25 | Stn−lcdパネル用の駆動回路 |
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CN1920931B true CN1920931B (zh) | 2010-06-30 |
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JP (1) | JP4803711B2 (zh) |
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US5747979A (en) * | 1995-09-12 | 1998-05-05 | Sharp Kabushiki Kaisha | Multiple value voltage output circuit and liquid crystal display driving circuit |
CN1411150A (zh) * | 2001-10-03 | 2003-04-16 | 日本电气株式会社 | 取样电平移动电路、两相和多相展开电路以及显示装置 |
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EP0559321B1 (en) * | 1992-01-31 | 1997-07-09 | Canon Kabushiki Kaisha | Active matrix liquid crystal light valve with driver circuit |
JP3243581B2 (ja) * | 1992-01-31 | 2002-01-07 | キヤノン株式会社 | アクティブマトリクス液晶光バルブ |
JP3105074B2 (ja) * | 1992-05-29 | 2000-10-30 | 株式会社東芝 | 電圧切換回路 |
KR100188081B1 (ko) | 1995-02-24 | 1999-06-01 | 김광호 | 액정 표시 장치를 구동하기 위한 출력 회로 |
KR970076456A (ko) * | 1996-05-15 | 1997-12-12 | 엄길용 | 펄스 폭 변조를 이용한 다중 라인 선택 전압 인가 방식의 큰휨 네마틱 액정 표시기(stn-lcd) 구동 회로 |
JP4100407B2 (ja) * | 2004-12-16 | 2008-06-11 | 日本電気株式会社 | 出力回路及びデジタルアナログ回路並びに表示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5747979A (en) * | 1995-09-12 | 1998-05-05 | Sharp Kabushiki Kaisha | Multiple value voltage output circuit and liquid crystal display driving circuit |
CN1411150A (zh) * | 2001-10-03 | 2003-04-16 | 日本电气株式会社 | 取样电平移动电路、两相和多相展开电路以及显示装置 |
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US20070046598A1 (en) | 2007-03-01 |
TWI344627B (en) | 2011-07-01 |
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TW200709152A (en) | 2007-03-01 |
JP4803711B2 (ja) | 2011-10-26 |
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US7683879B2 (en) | 2010-03-23 |
KR20070024392A (ko) | 2007-03-02 |
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