CN1917196A - Packaging structure of pillar grid array, and electronic device - Google Patents
Packaging structure of pillar grid array, and electronic device Download PDFInfo
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- CN1917196A CN1917196A CNA2005100931786A CN200510093178A CN1917196A CN 1917196 A CN1917196 A CN 1917196A CN A2005100931786 A CNA2005100931786 A CN A2005100931786A CN 200510093178 A CN200510093178 A CN 200510093178A CN 1917196 A CN1917196 A CN 1917196A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Packaging structure of pole grid array includes a base plate, a wafer setup on up surface of the base plate, and multiple lugs of tie line formed on low surface of the base plate. Lugs of tie line are in pole grid array. There is a shaved off top surface on each lug of tie line. The electronic equipment includes following parts and structures: a base plate with an up surface and a low surface; a wafer setup on up surface of the base plate; and the multiple lugs of tie line described above. Through conducting resin, wafer is jointed to a printing circuit board in order to reach to thin type assembly. The invention solves issue of warp of base plate in packaging structure of ball grid array caused by procedure of soldering back solder balls.
Description
Technical field
The present invention relates to a kind of wafer packaging construction, particularly relate to a kind of packaging structure of pillar grid array and electronic installation thereof (pillar grid array package (PGA) and electronic device).
Background technology
Existing known ball grid array encapsulation construction (ball grid array package, BGA) be soldered ball (solder ball) to be planted be connected to a substrate and for the trellis array, in order to surface engagement (SurfaceMount Technology, SMT) in a printed circuit board (PCB), can reach the connection of high-end subnumber at the area of coverage (footprint) of a limitation, be the packaging structure kenel of extensively using at present.
Seeing also shown in Figure 1ly, is the schematic cross-section of existing known ball grid array encapsulation construction.A kind of existing known slimming ball grid array encapsulation construction 100 mainly comprises a substrate 110, a wafer 120 and a plurality of soldered ball 140 (solder ball).One upper surface 111 of this substrate 110 is provided with wafer 120, and this wafer 120 is to be the projection wafer, and its active surface 121 is provided with a plurality of chip-covered boss 122, with chip bonding to substrate 110.A lower surface 112 of this substrate 110 is provided with those soldered balls 140, and it is to be the trellis array, for a composition surface 11 of surface engagement to a printed circuit board (PCB) 10.Usually, a underfill 130 is to be formed between wafer 120 and the substrate 110, to seal those chip-covered boss 122.
When this ball grid array encapsulation construction 100 surface engagement during to printed circuit board (PCB) 10, for making those soldered balls 213 can be soldered to the connection gasket of this printed circuit board (PCB) 10, must be through reflow (Reflow) process of one high temperature, make substrate 110 produce warping phenomenon easily, cause those soldered balls 213 fractures of part, stress raiser is near the soldered ball 213 at substrate 110 edges usually.If merely those soldered ball 213 quantity delivered increases then can be increased the thickness after the assembling, and be easy to generate the phenomenon of soldered ball bridge joint.
This shows that above-mentioned existing packaging structure of pillar grid array obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem that packaging structure of pillar grid array exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of novel packaging structure of pillar grid array and electronic installation thereof, just become the current industry utmost point to need improved target.
Because the defective that above-mentioned existing packaging structure of pillar grid array exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of novel packaging structure of pillar grid array and electronic installation thereof, can improve general existing packaging structure of pillar grid array, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing packaging structure of pillar grid array and electronic installation thereof exist, and provide a kind of novel packaging structure of pillar grid array and electronic installation thereof, technical problem to be solved is that to make a plurality of tie lines projections (stud bump) be for the trellis array and is formed at a lower surface of a substrate, and each tie lines projection has the end face of scabbling, so can utilize anisotropic conductive or ultrasonic waves keyed jointing mode surface engagement to a printed circuit board (PCB), can solve the substrate warp problem of known ball grid array encapsulation construction under the high temperature reflow, and can reach the assembling of thin type electronic device, thereby the industry that is suitable for is more used.
Another object of the present invention is to, a kind of packaging structure of pillar grid array and electronic installation thereof are provided, technical problem to be solved is to make its each tie lines projection under a substrate have the end face of scabbling and is copline, can be electrically connected to a printed circuit board (PCB) for an anisotropic conductive.In addition, those tie lines projections are to have non-vertical matter sidewall, can reduce the electrical bridge joint of side direction, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of packaging structure of pillar grid array that the present invention proposes, it comprises: a substrate, and it has a upper surface and a lower surface; One wafer, it is arranged at this upper surface of this substrate; And a plurality of tie lines projections (stud bump), it is for the trellis array and is formed at this lower surface of this substrate, and each tie lines projection has the end face of scabbling.
The object of the invention to solve the technical problems also adopts following technical measures further to realize.
Aforesaid packaging structure of pillar grid array, wherein said those tie lines projections are to form (wire-bonding) by routing, and the end face that scabbles of those tie lines projections is to be copline.
Aforesaid packaging structure of pillar grid array, wherein said substrate has an open slot, to appear a plurality of weld pads of this wafer.
Aforesaid packaging structure of pillar grid array, this open slot of wherein said substrate have an end difference and a plurality of be located at this end difference in connect finger, a plurality of bonding wires electrically connect this wafer via this open slot those weld pads connect finger to those of this substrate.
Aforesaid packaging structure of pillar grid array, it includes an adhesive body in addition, and it is formed at this open slot.
Aforesaid packaging structure of pillar grid array, wherein said wafer are to be an overlay crystal chip, and it is to be connected to this substrate with a plurality of chip-covered boss, and comprises an adhesive body in addition, and it is formed at this upper surface of this substrate, to seal those chip-covered boss of this wafer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of electronic installation that the present invention proposes, it comprises: a printed circuit board (PCB); And a packaging structure of pillar grid array, it is arranged at this printed circuit board (PCB), and comprises: a substrate, and it has a upper surface and a lower surface; One wafer is arranged at this upper surface of this substrate; And a plurality of tie lines projections (stud bump), it is for the trellis array and is formed at this lower surface of this substrate, and each tie lines projection has the end face of scabbling.
The object of the invention to solve the technical problems also adopts following technical measures further to realize.
Aforesaid packaging structure of pillar grid array, it comprises an anisotropic conductive (Anisotropicconductive paste in addition, ACP) or the anisotropy conducting film (Anisotropic conductive film, ACF), its be electrically connect those tie lines projections scabble end face to this printed circuit board (PCB).
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of packaging structure of pillar grid array that the present invention proposes, it comprises: a substrate, and it has a upper surface and a lower surface; One wafer, it is arranged at this upper surface of this substrate; And a plurality of column-like projection blocks (pillar bump), it is for the trellis array and is formed at this lower surface of this substrate, and each column-like projection block has the end face of scabbling and a non-perpendicular sidewall.
The object of the invention to solve the technical problems also adopts following technical measures further to realize.
Aforesaid packaging structure of pillar grid array, the end face that scabbles of wherein said those column-like projection blocks is to be copline.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to achieve the above object, the invention provides a kind of packaging structure of pillar grid array.According to packaging structure of pillar grid array of the present invention, comprise a substrate, a wafer and a plurality of tie lines projection, this substrate has a upper surface and a lower surface, this wafer is arranged at this upper surface of this substrate, those tie lines projections are for the trellis array and are formed at this lower surface of this substrate, and each tie lines projection has the end face of scabbling, to replace the soldered ball of known ball grid array encapsulation construction, so can save the surface engagement of known product with the high temperature reflow.
By technique scheme, packaging structure of pillar grid array of the present invention and electronic installation thereof have following advantage at least:
Packaging structure of pillar grid array of the present invention and electronic installation thereof, making a plurality of tie lines projections (studbump) is trellis array and a lower surface that is formed at a substrate, and each tie lines projection has the end face of scabbling, so can utilize anisotropic conductive or ultrasonic waves keyed jointing mode surface engagement to a printed circuit board (PCB), can solve the substrate warp problem of known ball grid array encapsulation construction under the high temperature reflow, and can reach the assembling of thin type electronic device, thereby the industry that is suitable for is more used.
In addition, the present invention is that each the tie lines projection under a substrate has the end face of scabbling and is copline, and can be electrically connected to a printed circuit board (PCB) for an anisotropic conductive.
In addition, above-mentioned those tie lines projections have non-vertical matter sidewall, and can reduce the electrical bridge joint of side direction, thereby are suitable for practicality more.
In sum, packaging structure of pillar grid array that the present invention is special and electronic installation thereof, comprise that mainly a substrate, is arranged at wafer and a plurality of tie lines projection that is formed at this base lower surface of this upper surface of base plate, those tie lines projections are the trellis array, and each tie lines projection has the end face of scabbling, can be by anisotropic conductive surface engagement to a printed circuit board (PCB), the slimming assembling can be reached, and known ball grid array encapsulation construction causes substrate warp in reflow soldered ball process defective can be solved.It has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it all has bigger improvement on the structure of product, equipment or function, have large improvement technically, and produced handy and practical effect, and more existing packaging structure of pillar grid array and electronic installation thereof have the multinomial effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section that has known ball grid array encapsulation construction now.
Fig. 2 is according to a specific embodiment of the present invention, a kind of schematic cross-section of packaging structure of pillar grid array.
Fig. 3 is according to a specific embodiment of the present invention, the schematic cross-section in encapsulation formation bonding wire and tie lines projection process of this packaging structure of pillar grid array.
Fig. 4 is according to another specific embodiment of the present invention, the schematic cross-section of another kind of packaging structure of pillar grid array.
10: printed circuit board (PCB) 11: composition surface
21: thin capillary 22: thick capillary
30: anisotropic conductive 100: ball grid array encapsulation construction
110: substrate 111: upper surface
112: lower surface 120: wafer
121: active surface 122: chip-covered boss
130: underfill 140: soldered ball
200: packaging structure of pillar grid array 210: substrate
211: upper surface 212: lower surface
213: open slot 214: end difference
215: in connect and refer to 216: outer connection pad
220: wafer 221: active surface
222: weld pad 230: glutinous brilliant material
240: bonding wire 250: the tie lines projection
251: scabble end face 252: non-perpendicular sidewall
260: adhesive body 300: packaging structure of pillar grid array
310: substrate 311: upper surface
312: lower surface 320: wafer
321: active surface 322: chip-covered boss
330: underfill 340: the tie lines projection
341: scabble end face
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to packaging structure of pillar grid array and its embodiment of electronic installation, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Seeing also shown in Figure 2ly, is according to a specific embodiment of the present invention, a kind of schematic cross-section of packaging structure of pillar grid array.According in first preferred embodiment of the present invention, a kind of packaging structure of pillar grid array 200, mainly include a substrate 210, a wafer 220 and a plurality of tie lines projection (stud bump) 250, this substrate 210 has a upper surface 211 and a lower surface 212.In the present embodiment, this substrate 210 has more an open slot 213, in order to the weld pad 222 that appears wafer 220.Preferable, this open slot 213 has an end difference 214, and connects in substrate 210 a plurality of and refer to that 215 is to be arranged at this end difference 214, the camber of a plurality of bonding wires 240 when reducing routing, and the slimming that is beneficial to an adhesive body 260 forms.In addition, a plurality of outer connection pads 216 are arranged at the lower surface 212 of substrate 210.
Please consult shown in Figure 2ly again, this wafer 220 is arranged at the upper surface 211 of substrate 210, can be by a glutinous brilliant material 230 with active surface 221 gluings of wafer 220 upper surface 211 to substrate 210.In the present embodiment, a plurality of weld pads 222 at this active surface 221 are to be revealed in open slot 213.Connect in those of those bonding wires 240 electrically connect wafers 220 via this open slot 213 those weld pads 222 and substrate 210 and refer to 215.
In addition, those tie lines projections 250 are to be the trellis array, and are formed at the lower surface 212 of substrate 210, and promptly those tie lines projections 250 are to be engaged to those outer connection pads 216, as the column-like projection block of 200 pairs of outer engagement of packaging structure of pillar grid array, replace the soldered ball of known ball grid array encapsulation construction.Those tie lines projections 250 are to be formed by routing, and can contain gold, copper, aluminium etc. or other metal.And each tie lines projection 250 should have the end face of scabbling 251, so that the connection area of anisotropy conductive bond or ultrasonic waves keyed jointing to be provided.Preferable, those scabble end face 251 is to be copline, connects to reach good anisotropy conduction.
In addition, an adhesive body 260 is to be formed at open slot 213, with seal those bonding wires 240, those weld pads 222 with those in connect and refer to 215.Because the camber of those bonding wires 240 reduces, so this adhesive body 260 can excessively not protrude in the lower surface 212 of substrate 210.In the present embodiment, this adhesive body 260 more extends and covers to the side of wafer 220.
Because those bonding wires 240 form by routing with those tie lines projections 250, see also shown in Figure 3, can be in a routing processing procedure, provide those bonding wires 240 with a thin capillary 21, and can provide those tie lines projections 250 with a thick capillary 22, make substrate 210 scabble processing machine (not drawing among the figure) plane lappingout through one again, make those tie lines projections 250 have above-mentioned coplanar end face 251 that scabbles.Do not need existing known soldered ball to plant the step of ball, so have the effect of simplifying processing procedure.In addition, the tie lines projection 250 that utilizes those routings to form, each tie lines projection 250 has a non-perpendicular sidewall 252, is different from general column-like projection block, has the effect that reduces the electrical bridge joint of side direction when anisotropy conduction (ACF) engages.
Therefore, this packaging structure of pillar grid array 200 (PGA) can connect or ultrasonic waves keyed jointing mode surface engagement to a printed circuit board (PCB) (not drawing among the figure) by the anisotropy conduction, to be assembled into a thin type electronic device.No longer need the existing known high temperature reflow process of ball grid array encapsulation construction (BGA) when surface engagement (SMT), can reduce the warpage of substrate 210 and opening circuit of those tie lines projections 250.
Seeing also shown in Figure 4ly, is according to another specific embodiment of the present invention, is the schematic cross-section of another kind of packaging structure of pillar grid array.According to second specific embodiment of the present invention, a kind of packaging structure of pillar grid array 300 can be by an anisotropic conductive 30 (Anisotropic conductive paste, ACP) or anisotropy conducting film (Anisotropic conductive film, ACF), one composition surface 11 of surface engagement to a printed circuit board (PCB) 10 is to form a thin type electronic device.This packaging structure of pillar grid array 300 mainly includes a substrate 310, a wafer 320 and a plurality of tie lines projection 340.This substrate 310 is to be a hard circuit substrate or a flexible base plate.This substrate 310 has a upper surface 311 and a lower surface 312.This wafer 320 is arranged at the upper surface 311 of substrate 310.In the present embodiment, this wafer 320 is to be an overlay crystal chip.This wafer 320 has an active surface 321 and a plurality of chip-covered boss 322, and those chip-covered boss 322 are the active surfaces 321 that are formed at this wafer 320, with the upper surface 311 of chip bonding in substrate 310.One underfill 330 or other adhesive body are to be formed between the active surface 321 of the upper surface 311 of this substrate 310 and wafer 320, to seal those chip-covered boss 322.
A plurality of tie lines projections 340, be for the trellis array and be formed at the lower surface 312 of substrate 310, and each tie lines projection 340 has the end face of scabbling 341, wherein those to scabble end face 341 be preferable for copline, in order to the electrical conduction of the conducting particles that in anisotropic conductive 30, has consistent particle diameter.But if this substrate 310 is when having pliability, those scabble 341 of end faces may be non-copline, for surface engagement to nonplanar printed circuit board (PCB).
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art are not in breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1, a kind of packaging structure of pillar grid array is characterized in that it comprises:
One substrate, it has a upper surface and a lower surface;
One wafer, it is arranged at this upper surface of this substrate; And
A plurality of tie lines projections (stud bump), it is for the trellis array and is formed at this lower surface of this substrate, and each tie lines projection has the end face of scabbling.
2, packaging structure of pillar grid array according to claim 1 is characterized in that wherein said those tie lines projections are to form (wire-bonding) by routing, and the end face that scabbles of those tie lines projections is to be copline.
3, packaging structure of pillar grid array according to claim 1 is characterized in that wherein said substrate has an open slot, to appear a plurality of weld pads of this wafer.
4, packaging structure of pillar grid array according to claim 3, this open slot that it is characterized in that wherein said substrate have an end difference and a plurality of be located at this end difference in connect finger, a plurality of bonding wires electrically connect this wafer via this open slot those weld pads connect finger to those of this substrate.
5, packaging structure of pillar grid array according to claim 3 is characterized in that it includes an adhesive body in addition, and it is formed at this open slot.
6, packaging structure of pillar grid array according to claim 1, it is characterized in that wherein said wafer is to be an overlay crystal chip, it is to be connected to this substrate with a plurality of chip-covered boss, and comprise an adhesive body in addition, it is formed at this upper surface of this substrate, to seal those chip-covered boss of this wafer.
7, a kind of electronic installation is characterized in that it comprises:
One printed circuit board (PCB); And
One packaging structure of pillar grid array, it is arranged at this printed circuit board (PCB), and comprises:
One substrate, it has a upper surface and a lower surface;
One wafer, it is arranged at this upper surface of this substrate; And
A plurality of tie lines projections (stud bump), it is for the trellis array and is formed at this lower surface of this substrate, and each tie lines projection has the end face of scabbling.
8, electronic installation according to claim 7, it is characterized in that it comprises an anisotropic conductive (Anisotropic conductive paste in addition, ACP) or anisotropy conducting film (Anisotropicconductive film, ACF), its be electrically connect those tie lines projections scabble end face to this printed circuit board (PCB).
9, a kind of packaging structure of pillar grid array is characterized in that it comprises:
One substrate, it has a upper surface and a lower surface;
One wafer, it is arranged at this upper surface of this substrate; And
A plurality of column-like projection blocks (pillar bump), it is for the trellis array and is formed at this lower surface of this substrate, and each column-like projection block has the end face of scabbling and a non-perpendicular sidewall.
10, packaging structure of pillar grid array according to claim 9 is characterized in that the end face that scabbles of wherein said those column-like projection blocks is to be copline.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100931786A CN1917196A (en) | 2005-08-19 | 2005-08-19 | Packaging structure of pillar grid array, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100931786A CN1917196A (en) | 2005-08-19 | 2005-08-19 | Packaging structure of pillar grid array, and electronic device |
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| CN1917196A true CN1917196A (en) | 2007-02-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2005100931786A Pending CN1917196A (en) | 2005-08-19 | 2005-08-19 | Packaging structure of pillar grid array, and electronic device |
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| CN (1) | CN1917196A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104843632A (en) * | 2014-02-14 | 2015-08-19 | 南茂科技股份有限公司 | Micro-electromechanical chip package and manufacturing method thereof |
| US10008461B2 (en) | 2015-06-05 | 2018-06-26 | Micron Technology, Inc. | Semiconductor structure having a patterned surface structure and semiconductor chips including such structures |
-
2005
- 2005-08-19 CN CNA2005100931786A patent/CN1917196A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104843632A (en) * | 2014-02-14 | 2015-08-19 | 南茂科技股份有限公司 | Micro-electromechanical chip package and manufacturing method thereof |
| US10008461B2 (en) | 2015-06-05 | 2018-06-26 | Micron Technology, Inc. | Semiconductor structure having a patterned surface structure and semiconductor chips including such structures |
| US10354966B2 (en) | 2015-06-05 | 2019-07-16 | Micron Technology, Inc. | Methods of forming microelectronic structures having a patterned surface structure |
| US10950564B2 (en) | 2015-06-05 | 2021-03-16 | Micron Technology, Inc. | Methods of forming microelectronic devices having a patterned surface structure |
| US11640948B2 (en) | 2015-06-05 | 2023-05-02 | Micron Technology, Inc. | Microelectronic devices and apparatuses having a patterned surface structure |
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