CN1956179A - Chip package structure and lug manufacturing process - Google Patents
Chip package structure and lug manufacturing process Download PDFInfo
- Publication number
- CN1956179A CN1956179A CN200510117212.9A CN200510117212A CN1956179A CN 1956179 A CN1956179 A CN 1956179A CN 200510117212 A CN200510117212 A CN 200510117212A CN 1956179 A CN1956179 A CN 1956179A
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- China
- Prior art keywords
- substrate
- chip
- projection
- packaging structure
- sticky material
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Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000463 material Substances 0.000 claims abstract description 52
- 238000004806 packaging method and process Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims description 86
- 229920001187 thermosetting polymer Polymers 0.000 claims description 24
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000003466 welding Methods 0.000 abstract 3
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000009477 glass transition Effects 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229920000292 Polyquinoline Polymers 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000010422 painting Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A packaging structure of chip is prepared as arranging multiple first welding pad on the first base plate and setting the second base plate with multiple second pad above the first one, setting lug separately on the first or the second welding pad and electric-connecting the first base plate to the first one through said lug, arranging adhesive material with B order character between two said welding pads and using said material to surround each lug, applying tie-lines lug or electric-plated lug as said lug.
Description
Technical field
The invention relates to a kind of chip-packaging structure and lug manufacturing process, and particularly relevant for a kind of by projection and be enclosed in chip-packaging structure and the lug manufacturing process of its peripheral sticky material to electrically connect two substrates.
Background technology
Along with increasing of the I/O contact of integrated circuit, chip (chip is wafer, below all be called chip) encapsulation technology becomes more and more diversified.This is owing to flip-chip (FC) interconnection technique minimization Chip Packaging size and reduce the fact of signal transmission path etc.The most frequently used chip-packaging structure of using the flip chip interconnects technology comprises such as flip-chip ball grid array (FC/BGA) and flip-chip stitch grid array chip-packaging structures such as (FC/PGA).
The flip chip interconnects technology adopts a kind of like this method, promptly by most weld pads are set on the active surface of chip, and forms most projections respectively on described weld pad, comes the delimited area array.Then, with flip-chip, with the soldering projection that connects chip respectively be arranged on such as most contact mats on the carrier of circuit substrate.Therefore, chip electrically connects and is mechanically attached to described carrier by projection.In addition, chip can be electrically connected to external electronic by the internal circuit of carrier.Usually, projection has some types, for example solder projection, golden projection, copper bump, conducting polymer projection, macromolecular convex etc.
See also shown in Figure 1ly, illustrate cutaway view for chip-packaging structure with macromolecular convex.Chip-packaging structure 100 comprises first substrate 110, most macromolecular convex 120, chip 130 and scolders 140.First substrate 110 has surperficial 110a, and surperficial 110a is provided with most contact mats 112.Chip 130 has active surface 130a, and active surface 130a is provided with most weld pads 132.The macromolecular convex of being made by the macromolecular material with conductive characteristic 120 is configured in respectively between contact mat 112 and the weld pad 132, to electrically connect substrate 110 and chip 130.Because macromolecular convex 120 also is not attached to contact mat 112, therefore need scolder 140 that macromolecular convex 120 is fixed on the substrate 110.The surfaces A of scolder 140 is attached to contact mat 112, and its surperficial B is attached to macromolecular convex 120.Therefore. when chip-packaging structure is subjected to time spent of doing of external force or thermal stress (not shown), scolder 140 can be by breaking away from the contact mat 112, and macromolecular convex 120 will no longer be electrically connected to contact mat 112.Therefore, will reduce the reliability of chip-packaging structure.
Summary of the invention
Main purpose of the present invention provides a kind of chip-packaging structure, this chip-packaging structure is to utilize most projections to electrically connect a chip and a substrate, in addition, and by sticky material with B rank characteristic surrounding projection, and then improve the reliability of chip-packaging structure.
Another object of the present invention provides a kind of lug manufacturing process.At first, on substrate surface, form most projections, then, form a sticky material with B rank characteristic surrounding above-mentioned projection respectively, and then guarantee the electrical connection between substrate and another substrate.
Based on above-mentioned purpose or other purposes, the invention provides a kind of chip-packaging structure, it comprises first substrate, second substrate, most individual projection and sticky material.First substrate has most first weld pads.Second substrate is arranged on the top of first substrate, and has most second weld pads.A most projection are configured in respectively on first weld pad or second weld pad, and second substrate is electrically connected to first substrate by above-mentioned projection.Sticky material with B rank characteristic is disposed between first substrate and second weld pad, and surrounds each projection.
In one embodiment of this invention, projection comprises tie lines projection or plated bumps.
In one embodiment of this invention, sticky material is an adhesion coating, and adhesion coating is non-conductive.
In one embodiment of this invention, sticky material comprises most adhesion pieces, and the adhesion piece can be conduction or non-conductive.
In one embodiment of this invention, first substrate and second substrate the two can be all chip.
In one embodiment of this invention, first substrate can be a carrier, and second substrate can be a chip.
In one embodiment of this invention, its glass transition temperature of adhesion piece with B rank characteristic is between-40 ℃ and 175 ℃.
In one embodiment of this invention, chip-packaging structure further comprises a carrier and most bar routing lead.First substrate and second substrate are arranged on this carrier, and first substrate is electrically connected to carrier by described routing lead.
Based on above-mentioned purpose or other purposes, the invention provides a kind of lug manufacturing process, it comprises: the substrate with most weld pads is provided; On each weld pad, form projection; On this substrate, form thermosetting sticky material, to surround each projection with two rank characteristic; This has the thermosetting sticky material of two rank characteristic, the sticky material that has B rank characteristic with formation precuring.
In one embodiment of this invention, projection comprises tie lines projection or plated bumps.
In one embodiment of this invention, the thermosetting sticky material with two rank characteristic is to form by screen painting, printing, spraying, spin coating or dipping.
In one embodiment of this invention, the thermosetting sticky material is the thermosetting adhesion coating.
In one embodiment of this invention, the thermosetting sticky material comprises most thermosetting adhesion pieces.
In one embodiment of this invention, the thermosetting sticky material precuring that has two rank characteristic by being exposed to ultraviolet light.
In one embodiment of this invention, the thermosetting sticky material precuring that has two rank characteristic by heating.
In one embodiment of this invention, has its glass transition temperature of sticky material of B rank characteristic between-40 ℃ and 175 ℃.
In sum, chip-packaging structure of the present invention is to utilize the sticky material with B rank characteristic to surround projection.Substrate is by projection or by projection and be enclosed in its peripheral sticky material to be electrically connected to another substrate.The top and bottom of sticky material are attached to the weld pad of upper substrate and infrabasal plate respectively.Therefore, when chip-packaging structure is subjected to time spent of doing of external force or thermal stress, the sticky material that is enclosed in the projection periphery can be guaranteed the electric connection between upper substrate and the infrabasal plate, and then promotes the reliability of chip-packaging structure.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the cutaway view for the known chip-packaging structure with macromolecular convex.
Fig. 2 illustrate into the chip-packaging structure of the first embodiment of the present invention cutaway view.
Fig. 3 illustrates the cutaway view according to the chip-packaging structure of the second embodiment of the present invention.
Fig. 4 illustrates the cutaway view into the stack type chip packaging structure of one embodiment of the present of invention.
Fig. 5 A to Fig. 5 D illustrates the making flow process cutaway view into lug manufacturing process of the present invention.
100: 110: the first substrates of chip-packaging structure
110a: surface 112: contact mat
120: macromolecular convex 130: chip
130a: active surface 132: weld pad
140: scolder 200: chip-packaging structure
200 ': 210: the first substrates of chip-packaging structure
212: the first weld pads of 210 ': the first chip
220: the second substrate 220 ': the second chips
Weld pad 230 in 222: the second: projection
230a: tie lines projection 230b: plated bumps
240: sticky material 240a: the adhesion piece
240b: adhesion coating 310: substrate
312: weld pad 320: projection
320a: tie lines projection 330: sticky material
330a: thermosetting adhesion piece 340: adhesion piece with B rank characteristic
400: stack type chip packaging structure 410: carrier
420: routing lead 430: adhesion coating
S1: surperficial S2: surface
S3: surface
Embodiment
See also shown in Figure 2ly, illustrate cutaway view into the chip-packaging structure of the first embodiment of the present invention.Chip-packaging structure 200 of the present invention mainly comprises first substrate 210, second substrate 220, most projections 230 and the sticky material 240 with B rank characteristic.The present invention utilizes projection 230 to electrically connect first substrate 210 and second substrate 220.In addition, the sticky material 240 with B rank characteristic that surrounds projection 230 is in order to increasing the adhesion between first substrate 210 and second substrate 220, and then the reliability of raising chip-packaging structure 200.
On the surperficial S1 of first substrate 210, dispose most first weld pads 212.Second substrate 220 is configured in first substrate, 210 tops, also disposes most second weld pads 222 on its surperficial S2.According to one embodiment of present invention, first substrate 210 and second substrate 220 the two can be all chip.In addition, first substrate 210 can be a carrier, for example: and printed circuit board (PCB) (PCB), and second substrate 220 can be a chip.The present invention does not impose any restrictions for the pattern of first substrate 210 and second substrate 220.Projection 230 is configured in respectively on first weld pad 212 or second weld pad 222, and the upper end of each projection 230 contacts with second weld pad 222, and its lower end contacts with first weld pad 212.In this embodiment, projection 230 is tie lines projection 230a, and tie lines projection 230a can be golden tie lines projection.Therefore, second substrate 220 is electrically connected to first substrate 210 by tie lines projection 230a.
See also shown in Figure 3ly, illustrate cutaway view according to the chip-packaging structure of the second embodiment of the present invention.Chip-packaging structure 200 ' is identical with chip-packaging structure shown in Figure 2 200 haply.And these two kinds of chip-packaging structure differences are, in a second embodiment, projection 230 is plated bumps 230b, and sticky material 240 is the adhesion coating 240b with non-conductive characteristic.The material of plated bumps 230b can comprise gold.Similarly, be configured in the suitable electric connection of guaranteeing between first substrate 210 and second substrate 220 of adhesion coating 240b between first substrate 210 and second substrate 220.Therefore, the reliability of chip-packaging structure 200 ' improves.
Yet the tie lines projection 230a of first embodiment also can be applicable among second embodiment, to replace plated bumps 230b.Similarly, the non-conductive adhesion coating 240b of second embodiment also can be applicable among first embodiment, to replace adhesion piece 240a.
Fig. 2 and structure shown in Figure 3 can be applicable to stack type chip packaging structure.Fig. 4 illustrates the cutaway view into the stack type chip packaging structure of one embodiment of the present of invention.See also shown in Figure 4ly, stack type chip packaging structure 400 mainly comprises carrier 410, first chip 210 ', second chip 220 ', most projections 230, sticky material 240 and a plurality of routing leads 420.Because first chip 210 ', second chip 220 ', projection 230 are identical with first embodiment with the configuration of sticky material 240, so, no longer repeat at this.In this embodiment, first chip 210 ' is to be fixed on the carrier 410 by adhesion coating 430, and is electrically connected to carrier 410 by routing lead 420.
Fig. 5 A to Fig. 5 D illustrates the making flow process cutaway view into lug manufacturing process of the present invention.Lug manufacturing process as herein described adopts above-mentioned first embodiment to describe as an example.At first, see also shown in Fig. 5 A, a substrate 310 with most weld pads 312 is provided.Substrate 310 can be a carrier, for example: PCB, chip etc.This weld pad 312 is to be disposed on the surperficial S3 of substrate 310.Then, please referring to Fig. 5 B, form projection 320 on each weld pad 312, the material of projection 320 comprises gold.Substrate 310 can be electrically connected to another substrate (not shown) by projection 320.In this embodiment, projection 320 is tie lines projection 320a.Except that the tie lines projection 320a shown in Fig. 5 B, also can use plated bumps 230b shown in Figure 3 to replace tie lines projection 320a, to electrically connect substrate 310 and another carrier.
Subsequently, see also shown in Fig. 5 C, on substrate 310, form a thermosetting sticky material 330 with two rank (A rank and B rank) characteristic, to surround each projection 320.In this embodiment, thermosetting sticky material 330 comprises most thermosetting adhesion piece 330a.The material of thermosetting adhesion piece 330a can be polyimides (polyimide), poly quinoline (polyquinolin), benzocyclobutene materials such as (benzocyclobutene).In addition, thermosetting adhesion piece 330a can conduct electricity or be non-conductive, and these thermosettings adhesion pieces 330a not only can form by screen painting, also can form by printing, spraying, spin coating or impregnating mode.In this step, the thermosetting mixture is liquid or gel state, therefore is easy to be coated on the surperficial S3 of substrate 310.In another embodiment of the present invention, thermosetting sticky material 330 also can be the adhesion coating 240b with non-conductive characteristic shown in Figure 3.Therefore, the present invention does not impose any restrictions for the pattern of thermosetting sticky material 330.
At last, see also shown in Fig. 5 D, precuring has the thermosetting adhesion piece 330a of two rank characteristic, to form most the adhesion pieces 340 with B rank characteristic.So far, finish lug manufacturing process of the present invention.In this embodiment, the thermosetting adhesion piece 330a with two rank characteristic can heat and precuring the adhesion piece 340 that has B rank characteristic with formation by being exposed to ultraviolet light 500 or passing through.Glass transition temperature with adhesion piece 340 of B rank characteristic is between-40 ℃ and 175 ℃.In addition, the adhesion piece 340 with B rank characteristic at room temperature is solid-state, and does not have adherence.
In sum, the adhesion piece of chip-packaging structure utilization of the present invention with B rank characteristic surrounds projection.Substrate is electrically connected to another substrate by projection or by projection and the sticky material that surrounds projection.The top and bottom of sticky material are attached to the weld pad of upper substrate and infrabasal plate respectively.Therefore, when chip-packaging structure is subjected to time spent of doing of external force or thermal stress, the sticky material that surrounds projection can be in order to guaranteeing the electric connection between upper substrate and the infrabasal plate, and then promote the reliability of chip-packaging structure.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1, a kind of chip-packaging structure is characterized in that it comprises:
One first substrate, it has most first weld pads;
One second substrate is configured in this first substrate top, and has most second weld pads;
A most projection, it is configured in respectively on those first weld pads or those second weld pads, and this second substrate sees through this projection and is electrically connected to this first substrate; And
One has the sticky material of B rank characteristic, is disposed between those first weld pads and those second weld pads, and surrounds respectively this projection.
2, chip-packaging structure according to claim 1 is characterized in that wherein those projections comprise tie lines projection or plated bumps.
3, chip-packaging structure according to claim 1 it is characterized in that wherein said sticky material is an adhesion coating, and this adhesion coating is non-conductive.
4, chip-packaging structure according to claim 1 is characterized in that wherein said sticky material comprises most adhesion pieces.
5, chip-packaging structure according to claim 1 is characterized in that wherein said first substrate and this second substrate are all chip.
6, chip-packaging structure according to claim 1 it is characterized in that wherein said first substrate is a carrier, and this second substrate is a chip.
7, chip-packaging structure according to claim 1, it is characterized in that it more comprises a carrier and a plurality of routing leads, wherein this first substrate and this second substrate are configured on this carrier, and this first substrate sees through those routing leads and is electrically connected to this carrier.
8, a kind of lug manufacturing process is characterized in that it comprises:
One substrate with most weld pads is provided;
In respectively forming a projection on this weld pad;
On this substrate, form a thermosetting sticky material with two rank characteristic, to surround respectively this projection; And
This has the thermosetting sticky material of two rank characteristic precuring, to form a sticky material with B rank characteristic.
9, lug manufacturing process according to claim 8 is characterized in that wherein those projections comprise tie lines projection or plated bumps.
10, lug manufacturing process according to claim 8 is characterized in that wherein said thermosetting sticky material precuring by being exposed to ultraviolet light or heating with two rank characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101172129A CN100433320C (en) | 2005-10-28 | 2005-10-28 | Chip package structure and lug manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101172129A CN100433320C (en) | 2005-10-28 | 2005-10-28 | Chip package structure and lug manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1956179A true CN1956179A (en) | 2007-05-02 |
| CN100433320C CN100433320C (en) | 2008-11-12 |
Family
ID=38063402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101172129A Expired - Fee Related CN100433320C (en) | 2005-10-28 | 2005-10-28 | Chip package structure and lug manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100433320C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101252096B (en) * | 2007-11-16 | 2010-08-11 | 日月光半导体制造股份有限公司 | Chip package structure and preparation method thereof |
| US7847414B2 (en) | 2005-09-22 | 2010-12-07 | Chipmos Technologies Inc. | Chip package structure |
| US7960214B2 (en) | 2005-09-22 | 2011-06-14 | Chipmos Technologies Inc. | Chip package |
| US7981725B2 (en) | 2005-09-22 | 2011-07-19 | Chipmos Technologies Inc. | Fabricating process of a chip package structure |
| CN103703610A (en) * | 2011-12-02 | 2014-04-02 | 松下电器产业株式会社 | Wireless module |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821456A (en) * | 1996-05-01 | 1998-10-13 | Motorola, Inc. | Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same |
| US6189208B1 (en) * | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
| US6410415B1 (en) * | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
| WO2001029895A1 (en) * | 1999-10-19 | 2001-04-26 | Motorola Inc. | Method of forming a microelectronic assembly |
| JP2002270637A (en) * | 2001-03-09 | 2002-09-20 | Toshiba Corp | Flip-chip connecting method and chip bonder |
| CN1617316A (en) * | 2003-11-10 | 2005-05-18 | 南茂科技股份有限公司 | Packaging process for improving effective adhesive crystal area and B step film layer for carrying out said package process |
-
2005
- 2005-10-28 CN CNB2005101172129A patent/CN100433320C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7847414B2 (en) | 2005-09-22 | 2010-12-07 | Chipmos Technologies Inc. | Chip package structure |
| US7960214B2 (en) | 2005-09-22 | 2011-06-14 | Chipmos Technologies Inc. | Chip package |
| US7981725B2 (en) | 2005-09-22 | 2011-07-19 | Chipmos Technologies Inc. | Fabricating process of a chip package structure |
| CN101252096B (en) * | 2007-11-16 | 2010-08-11 | 日月光半导体制造股份有限公司 | Chip package structure and preparation method thereof |
| CN103703610A (en) * | 2011-12-02 | 2014-04-02 | 松下电器产业株式会社 | Wireless module |
| CN103703610B (en) * | 2011-12-02 | 2016-07-27 | 松下知识产权经营株式会社 | Wireless module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100433320C (en) | 2008-11-12 |
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Granted publication date: 20081112 Termination date: 20181028 |