WO2001029895A1 - Method of forming a microelectronic assembly - Google Patents

Method of forming a microelectronic assembly Download PDF

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Publication number
WO2001029895A1
WO2001029895A1 PCT/US2000/029014 US0029014W WO0129895A1 WO 2001029895 A1 WO2001029895 A1 WO 2001029895A1 US 0029014 W US0029014 W US 0029014W WO 0129895 A1 WO0129895 A1 WO 0129895A1
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WO
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Patent type
Prior art keywords
die
substrate
face
bond pads
method
Prior art date
Application number
PCT/US2000/029014
Other languages
French (fr)
Inventor
John A. Burroughs
Daniel Gamota
Jeffrey J. Norton
James A. Wrezel
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Motorola Inc.
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/0554External layer
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Abstract

A method of forming a microelectronic assembly (10) is disclosed. The method includes the steps of providing an integrated circuit die (12) having a die face (16) and a plurality of solder bumps (22) deposited on a plurality of bond pads (20). The die face (16) is coated with a self-sustaining polymeric layer (28). A substrate (30) is provided having a plurality of bond pads (34), and the die (12) is superimposed over the die face (16) so that each of the solder bumps (22) registers with a corresponding one of the substrate bond pads (34). The die (12) and the substrate (30) are heated to a reflow temperature thereby forming a solder connection (36) between each solder bump (22) and its corresponding substrate bond pad (34) and thereby encapsulating the solder connections so formed in the polymeric layer.

Description

METHOD OF FORMING A MICROELECTRONIC ASSEMBLY

Field of the Invention The present invention relates generally to a method of forming a microelectronic assembly using the flip chip on board technique, and more specifically relates to a method of forming a coated integrated circuit die and a method of attaching the same to a substrate.

Background of the Invention

Many microelectronic assemblies are manufactured using the well- known flip chip on board (FCOB) technique. In FCOB assembly, an integrated circuit die is provided which includes a plurality of bond pads, with each of the bond pads having deposited thereon a solder bump. The die is turned over or flipped and is superimposed over a substrate having a plurality of bond pads, such that each of the solder bumps is aligned with a corresponding one of the bond pads on the substrate. The die and the substrate are then reflow soldered together to form solder connections. The gap that remains between the downwardly facing die face and the upwardly facing substrate face is then filled using any one of a number of known underfill materials. The underfill material, which typically contains silica, serves to encapsulate the solder connections, serves to bond the die to the substrate, increases reliability by enhancing the mechanical connection, and also serves to lessen thermal expansion problems caused by the differing coefficients of thermal expansion (CTE's) between the die and the substrate.

One prior art method of applying the underfill material has been to simply apply the underfill material to the assembly after the reflow soldering has been completed. The underfill material is drawn into the gap between the die and the substrate by capillary action. The assembly is then placed in an oven for curing. Unfortunately, the capillary action may result in voids around the solder connections which diminish the quality and reliability of the finished assembly, while the extra time, space, and production facilities necessitated by the extra curing step greatly increases cycle time and production costs. Moreover, the crosslinked epoxy formulations typically employed are not reworkable after curing. Accordingly, there exists a continuing need for improved FCOB assembly methods.

Brief Description of the Drawings

Fig. 1 is a fragmentary bottom plan view of a silicon wafer prior to dicing and having formed thereon a plurality of integrated circuit dies, with each of the dies having a plurality of solder bumps deposited thereon;

Fig. 2 is a cross-sectional view of an individual integrated circuit die having deposited thereon a polymeric layer in accordance with the teachings of the present invention;

Fig. 3 is a cross-sectional view of the individual integrated circuit die of Fig. 2 shown superimposed over a substrate with each of the solder bumps being aligned or in registration with a corresponding bond pad on the substrate; and

Fig. 4 is a cross-sectional view of a resulting microelectronic assembly formed upon reflow soldering of the device shown in Fig.3 with the polymeric material encapsulating the solder connections.

Detailed Description of the Preferred Embodiments

The following descriptions of the preferred embodiments are not intended to limit the scope of the invention to the precise forms disclosed, but instead are intended to be illustrative of the principles of the invention so that others may follow its teachings. Referring now to the drawings, Fig. 4 illustrates a microelectronic assembly assembled in accordance with the teachings of the present invention and which is generally referred to by the reference numeral 10. The microelectronic assembly 10 includes an integrated circuit die 12 of the type generally well known in the art. As shown in Figs. 2-4, the die 12 includes a die body 14, a die face 16, and a plurality of lateral edge portions 18. The die 12 has circuitry formed thereon (not shown) as is well known, and also includes a plurality of bond pads 20 disposed on the die face 16. As shown in Figs. 2 and 3, each of the bond pads 20 has deposited thereon a solder bump 22 so that the face 16 of the die 12 is bumped. The solder bumps 22 may be deposited using well-known methods. As shown in Fig. 1 , the die 12 is typically formed from a silicon wafer 24 which has formed thereon a plurality of integrated circuit dies 12a, 12b, 12c, . . . 12n. While only the dies 12a-12g are shown in Fig. 1 , it will be understood that the wafer 24 may contain a much greater number of dies 12 as may be contemplated by those of skill in the art. The wafer 24 is diced using known methods prior to assembly of the microelectronic assembly 10.

As shown in Figs. 2 and 3, the face 16 of the die 12 includes a coating 26, which coating 26 is preferably applied to the wafer 24 prior to dicing as will be explained in further detail below. The coating 26 is preferably a polymeric material, and after application of the coating 26 to the face 16 of the die 12 the coating 26 will preferably form a self- sustaining polymeric layer 28. As shown in Figs. 3 and 4, a substrate 30, such as a printed wiring board of the type commonly employed in the art and having circuitry (not shown) defined thereon, includes a face 32 having formed thereon a plurality of bond pads 34. As shown in Fig. 3, when the die 12 is flipped over such that the die face 16 faces the substrate face 32, each of the solder bumps 22 on the die 12 will be registered or aligned with a corresponding one of the bond pads 34 on the substrate 30. It will be noted that there is a gap 35 between a surface 37 of the layer 28 and the face 32 of the substrate 30. As shown in Fig. 4, to complete the microelectronic assembly 10, the die 12 must be mechanically and electrically connected to the substrate 30. To accomplish this, the subassembly of Fig. 3 is heated to reflow temperature (i.e., that temperature that is sufficient to cause the solder bumps 22 to melt). During reflow, the solder bumps 22 melt and are wetted to the surface of the bond pads 34 on the substrate 30, thus forming a plurality of solder connections 36 between the aligned and corresponding bond pads 22, 34 of the die 12 and the substrate 30, respectively. During heating, the layer 28 also melts such that the gap 35 is eliminated and the polymeric material forms an underfill 38, with each of the solder connections 36 being substantially encapsulated by polymeric material. Upon the formation of the underfill 38, a bond 39 is formed at the interface of the underfill 38 and the face 32 of the substrate 30.

Preferably, the coating 26 is a thermoplastic polymer, such as a phenoxy resin. One such commercially available phenoxy resin is Paphen manufactured by Phenoxy Associates. Other suitable thermoplastic materials, which soften in the presence of heat, may be employed as long as such thermoplastics exhibit softening point below the melting point of the solder material. Other examples of suitable thermoplastic materials would be DuPont Fusabond MD-353D (an anhydride-grafted polypropylene/polyethylene copolymer), DuPont Nucrel 599 (a 10% acrylic acid/ethylene copolymer), or Poly(hydroxy ether) resins available from Dow Chemical Company or Phenoxy Associates. The Poly(hydroxy ether) resins may be mixed with an organic activator, such as adipic acid, which acts a wetting agent. As an alternative, the coating 26 may be a thermoset polymer, which hardens in the presence of heat. A preferred thermoset material may be 80% Ciba Geigy Araldite GT6084 epoxy, 0.5% Ciba Geigy Araldite PY322 epoxy, 19% methylhexahydrophthalic anhydride, and 0.5% Lindride accelerator. The methylhexahydrophthalic anhydride serves as both a fluxing agent to reduce metal oxides and also as a crosslinking agent to cure the material. Such a thermoset material is preferably partially curable to a B stage polymer to form the self sustaining layer 28 (i.e., a layer exhibiting some shear strength) as will be discussed in greater detail below. The thermoset material is preferably fully curable at reflow temperatures to form the underfill 38. As another alternative, a reversible thermoset polymer, such as Shell Cariverse furan malemide resin, mixed with an organic activator such as adipic acid may be used. Referring again to Figs. 2 and 3, it will be noted that the solder bumps 22 have a height 40 (i.e., the height 40 being the total distance that a tip 42 of the bump 22 extends above the face 16 of the die 12, taking into account the extent to which the bond pads 20 extend beyond the face 16 of the die 12). Preferably, the height 40 of the solder bumps 22 is greater than the thickness of the layer 28 of the polymeric material. It will be noted that, depending on the constituency of the coating 26, the coating 26 when first applied may have a thickness greater than the height 40 of the solder bumps 22 and may subsequently shrink such that the height 40 of the solder bumps 22 is greater than a thickness 44 of the layer 28. It will also be noted that the coating 26 may be applied such that the thickness 44 of the layer 28 is greater than the height 40 of the solder bumps 22, in which case the layer 28 could be washed or etched using known methods to reach the desired thickness 44. It will also be noted that the tip 42 of the solder bumps 22 may at times have a thin covering thereon of the coating 26.

Preferably, the coating 26 will include a fluxing agent to promote wetting of the solder bumps 22 to the bond pads 34 on the substrate 30. Agents such as adipic acid, succinic acid and other suitable organic activators, as well as other known fluxing and/or wetting agents may be used. Also, in the event a thermoplastic material is used, a softening agent such as methyl ethyl ketone (MEK), Propylene Glycol Methyl Ether Acetate, or Ethyl Lactate may be added to the coating 26 in order to promote softening of the material so that the coating will become tacky. Tackiness will reduce skewing of the die 12 relative to the substrate 30 during placement of the die 12 on the substrate 30. Such a thermoplastic material will preferably have a softening point less than the melting point of the solder bumps 22, with the softening point preferably falling in the range between about 110°C and 160°C, with the most advantageous results being obtained at about 140°C. The solder material is preferably a eutectic 37% Pb and 63% Sn composition having a liquidous point of about 183°C.

In preparation, the wafer 24 is prepared by applying the coating material 26 to the active surface of the wafer 24, either from solution (e.g., by spin-coating or curtain-coating) or via heating prior to dicing or singulating the dies 12a-12n. The adipic acid or any other suitable fluxing agent is preferably contained in the coating material 26 when applied to the wafer 24. Prior to die singulation, the solder bumps 22 are exposed by plasma or chemical etch in the event the layer 28 is thicker than the height of the solder bumps 22.

The die 12 is selected, scanned for alignment, and superimposed over the substrate 30. With each solder bump 22 in alignment with a corresponding bond pad 34, the die 12 is then tacked to the substrate 30 using a vaporizable tacking agent. Alternately, the assembly may be heated to soften the coating material 26, whereupon the material may flow into incidental contact with substrate 30 suitable for tacking purposes. The subassembly is then heated to reflow in an oven (i.e., at least to the liquidous point of the solder material). In the event the substrate 30 is bumped, a phenoxy resin-based flux may be used to accommodate the larger gap 35 between the die 12 and the substrate 30.

Using known assembly techniques, at reflow temperature the solder bumps 22, aided by the fluxing agents or the intrinsic fluxing capability of the polymeric coating 26, form the solder connections 36. The self-sustaining layer 28 flows in the presence of heat to form the underfill 38 in which the gap 35 is eliminated and the underfill 38 forms a bond 39 at the interface of the die 12 and the substrate 30.

Those skilled in the art will appreciate that, although the teachings of the invention have been illustrated in connection with certain embodiments, there is no intent to limit the invention to such embodiments. On the contrary, the intention of this application is to cover all modifications and embodiments fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.

Claims

What is claimed:
1. A method of forming a microelectronic assembly, comprising the steps of: providing an integrated circuit die having a die face and a plurality of solder bumps deposited on said die face; coating the die face with a self-sustaining polymeric layer; providing a substrate having a plurality of bond pads; superimposing the die face over the substrate so that each of the solder bumps registers with a corresponding one of the substrate bond pads; and heating the die and the substrate to a reflow temperature thereby forming a solder connection between each solder bump and its corresponding substrate bond pad and thereby encapsulating the solder connections so formed in the polymeric layer.
2. The method of claim 1 , wherein the polymeric layer comprises a thermoplastic polymer.
3. The method of claim 1 , wherein the polymeric layer comprises a thermoset polymer.
4. The method of claim 1 , wherein the solder bumps have a height greater than a thickness of the polymeric layer.
5. The method of claim 1 , wherein the step of heating the die and the substrate includes the step of bonding the polymeric layer to the substrate.
6. The method of claim 1 , wherein the polymeric layer includes a fluxing agent to promote wetting of the solder bumps to the substrate bond pads during heating.
7. The method of claim 3, including the step of applying a polymerizable material and heating to partially cure said polymerizable material to form a B stage polymer in said self-sustaining layer, and wherein the step of heating the die and the substrate includes further curing the B stage polymer to form the polymeric layer.
8. The method of claim 2, wherein the thermoplastic material is a phenoxy resin.
9. The method of claim 2, including the thermoplastic material has a softening point less than a melting point of the solder bumps.
10. The method of claim 1 , wherein the thermoplastic material has a softening point between about 110° C and about 160° C.
11. A method of preparing an integrated circuit die comprising the steps of: providing a silicon wafer having a wafer face, the wafer face having at least one integrated circuit die formed thereon, the die including a die face and a plurality of bond pads disposed on the die face, the die further including a solder bump deposited on each of the bond pads; coating the die face with a self-sustaining polymeric material selected from the group consisting of thermoplastic polymers and partially cured thermoset polymers; at least partially processing the polymeric material to form a self- sustaining polymeric layer; and dicing the wafer to segregate the integrated die;
12. A silicon wafer comprising: a wafer face, the wafer face having at least one integrated circuit die formed thereon, the die including a die face and a plurality of bond pads disposed on the die face, the die further including a solder bump deposited on each of the bond pads; and a coating formed of a self-sustaining polymeric layer covering the die face and having a thickness, wherein the solder bumps have a height greater than the thickness of the self-sustaining polymeric layer, said layer being selected from the group consisting of thermoplastic polymers and partially cured thermoset polymers.
13. An integrated circuit die comprising: a die face having disposed thereon a plurality of bond pads, a solder bump deposited on each of the bond pads; and a coating of polymeric material covering the die face, the coating being at least partially cured to form a self-sustaining polymeric layer.
14. The integrated circuit die of claim 13, in combination with a substrate to form a microelectronic assembly, having a plurality of bond pads, the die being superimposed over the substrate so that each of the solder bumps is generally aligned with a corresponding one of the substrate bond pads, the die and the substrate being heat bonded together to thereby form a solder connection between each solder bump and its corresponding substrate bond pad and to thereby fully cure the coating.
PCT/US2000/029014 1999-10-19 2000-10-19 Method of forming a microelectronic assembly WO2001029895A1 (en)

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