CN2881956Y - Chip package - Google Patents
Chip package Download PDFInfo
- Publication number
- CN2881956Y CN2881956Y CN 200520147476 CN200520147476U CN2881956Y CN 2881956 Y CN2881956 Y CN 2881956Y CN 200520147476 CN200520147476 CN 200520147476 CN 200520147476 U CN200520147476 U CN 200520147476U CN 2881956 Y CN2881956 Y CN 2881956Y
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- CN
- China
- Prior art keywords
- wafer
- those
- encapsulation body
- wafer encapsulation
- body according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model relates to a wafer package, which comprises a coreless packaging baseplate and a wafer. The coreless packaging baseplate comprises an interior wiring structure and a ceramic supporting board. The interior wiring structure comprises a first interior circuit, a bearing surface and a joint surface. In the first interior circuit, a plurality of joint-holding pads are provided, which are located on the joint surface. The ceramic supporting board is located on the bearing surface, and is provided with a first hole. The wafer is located on the bearing surface and in the first hole, and is electrically connected with at least one of the joint-holding pads. From above, one can see that the strength and wiring density of the coreless packaging baseplate can be enhanced.
Description
Technical field
The utility model relates to a kind of semiconductor element, and particularly relevant for a kind of wafer encapsulation body.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the encapsulation (IC package) of the making (ICprocess) of the design of integrated circuit (IC design), integrated circuit and integrated circuit.In the making of integrated circuit, naked wafer (die) is made, is formed step such as integrated circuit and cutting crystal wafer and finishes via wafer (wafer).Wafer has an active surface (active surface), the surface with active member (activedevice) of its general reference wafer.After the integrated circuit of wafer was finished, the active surface of wafer more disposed a plurality of wafer connection pads (die pad), so that finally cut formed naked wafer by wafer, can outwards be electrically connected at a carrier (carrier) via these wafer connection pads.Carrier for example is a lead frame (leadframe) or a base plate for packaging (package substrate), and wafer can routing engages the mode of (wire bonding) or chip bonding (flip chip bonding) and is connected on the carrier, make the wafer connection pad of wafer can be electrically connected at the contact of carrier, to constitute a wafer encapsulation body.
With regard to chip bonding technology (flip chip bonding technology), before cutting crystal wafer, meeting is made projection (bump) on these wafer connection pads of the active surface of wafer usually, to electrically connect the usefulness of outside substrate as wafer.Because these projections are arranged on the active surface of wafer in the mode of face array (areaarray) usually, make the chip bonding technology be suitable for being used in the chip package structure of high number of contacts and high contactor density, the crystalline substance/sphere grid array formula (flip chip/ball grid array) of covering that for example is applied at large at present in the semiconductor packages industry encapsulates.In addition, compared to the applied elongated lead of routing joining technique,, make the chip bonding technology can promote the electrical property efficiency of wafer encapsulation body (electrical performance) because these projections can provide transmission path short between wafer and the carrier.
See also Fig. 1, it illustrates the generalized section of known a kind of flip chip packaging body.Known flip chip packaging body (flip chip package) 100 comprises a substrate 110, a wafer 120, a plurality of solder projection (solder bump) 130, one primer layer (underfill) 140 and a plurality of soldered balls (solder ball) 150.Substrate 110 comprises an internal connection-wire structure 112, and it has an internal wiring 112a, a loading end 112b and a corresponding contact face 112c, and internal wiring 112a has most contact connection pad 112d, and it is positioned on the contact face 112c.In addition, wafer 120 is configured on the loading end 112b, and makes wafer 120 and these contact connection pads 112d electrically connect mutually by these solder projections 130 with internal wiring 112a.In addition, primer layer 140 and coats these solder projections 130 between wafer 120 and substrate 110.Primer layer 140 is in order to protecting these solder projections 130, and can cushion between substrate 110 and the wafer 120 when being heated the unmatched phenomenon of the thermal strain that both produced (thermal strain) simultaneously.Moreover these soldered balls 150 are configured in respectively on these contact connection pads 112d, in order to electrically connect the electronic installation of next level, and printed circuit board (PCB) (Fig. 1 does not illustrate) for example.
Internal connection-wire structure 112 comprises a dielectric core layer (dielectric core layer) 112e, a plurality of plated-through-holes road (plating through hole, PTH) 112f, a plurality of organic dielectric layer (organicdielectric layer) 112g, a plurality of conductions duct (conductive via) 112h and a plurality of line layer (wire layer) 112i.These plated-through-hole roads 112f runs through dielectric core layer 112e, and each conduction duct 112h runs through these organic dielectric layer 112g one of them.In addition, electrically connect mutually by at least one of at least one of these plated-through-hole roads 112f or these conductions duct 112h between the wantonly two line layer 112i, and these plated-through-hole roads 112f, these conduction duct 112h and these line layers 112i constitute above-mentioned internal wiring 112a.Yet in known flip chip packaging body 100, the spacing between these plated-through-hole roads 112f can't be dwindled, and makes the wiring density (layoutdensity) of substrate 110 to promote.
Summary of the invention
The purpose of this utility model is providing a kind of wafer encapsulation body exactly, with stiffness and the wiring density that promotes its coreless capsulation substrates.
Based on above-mentioned purpose or other purposes, the utility model proposes a kind of wafer encapsulation body, comprise a coreless capsulation substrates and a wafer.Coreless capsulation substrates comprises an internal connection-wire structure and ceramic support slab.Internal connection-wire structure has one first internal wiring, a loading end and a corresponding contact face, and first internal wiring has most contact connection pads, and it is positioned on the contact face.Ceramic support slab is configured on the loading end, and has one first perforate.In addition, wafer configuration is on loading end and be positioned at first perforate, and wafer electrically connects mutually with at least one of these contact connection pads.
Based on above-mentioned, because the stiffness of the ceramic support slab of the coreless capsulation substrates of wafer encapsulation body of the present utility model is stronger, this is compared to metal profile, therefore in the process of making coreless capsulation substrates, ceramic support slab is difficult for buckling deformation and can reduces the residual stress of coreless capsulation substrates, and then promotes coplane (coplanarity) property of coreless capsulation substrates.In addition, because the coreless capsulation substrates of wafer encapsulation body of the present utility model does not have the plated-through-hole road, so the wiring density of coreless capsulation substrates can promote.In addition, because the ceramic support slab of the coreless capsulation substrates of wafer encapsulation body of the present utility model has second perforate or second internal wiring, therefore can be so that electronic component arrangements in second perforate or on the ceramic support slab, and then increase the area of electronic component arrangements.
For above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the generalized section of known a kind of flip chip packaging body.
Fig. 2 A illustrates the generalized section of the wafer encapsulation body of the utility model first embodiment.
Fig. 2 B illustrates the schematic top plan view of the wafer encapsulation body of Fig. 2 A.
Fig. 3 A illustrates the generalized section of the wafer encapsulation body of the utility model second embodiment.
Fig. 3 B illustrates the schematic top plan view of the wafer encapsulation body of Fig. 3 A.
Fig. 4 illustrates the generalized section of the wafer encapsulation body of the utility model the 3rd embodiment.
100: known flip chip packaging body 110: substrate
112,312: internal connection-wire structure 112a: internal wiring
112b, 312b, 412b: loading end 112c, 312c: contact face
112d, 312d: contact connection pad 112e: dielectric core layer
112f: plated-through-hole road 112g: organic dielectric layer
112h, 312f, 514e: conduction duct 112i, 312g, 514f: line layer
120,320: wafer 130: solder projection
140,340: primer layer 150: soldered ball
300,400,500: wafer encapsulation body of the present utility model
310: coreless capsulation substrates 312a, 412a, 512a: first internal wiring
312e: dielectric layer 314,414,514: ceramic support slab
314a: first perforate 330: projection
350: electrical contact 414b: second perforate
460,560: electronic component 514c: second internal wiring
514d: ceramic dielectric layers
Embodiment
See also Fig. 2 A, illustrate the generalized section of the wafer encapsulation body of the utility model first embodiment, Fig. 2 B illustrates the schematic top plan view of the wafer encapsulation body of Fig. 2 A.See also Fig. 2 A and Fig. 2 B, the wafer encapsulation body 300 of first embodiment comprises a coreless capsulation substrates 310 and a wafer 320.Coreless capsulation substrates 310 comprises an internal connection-wire structure 312 and ceramic support slab 314.Internal connection-wire structure 312 has one first internal wiring 312a, a loading end 312b and a corresponding contact face 312c, and the first internal wiring 312a has most contact connection pad 312d, and it is positioned on the contact face 312c.In addition, ceramic support slab 314 is configured on the loading end 312b, and has one first perforate 314a.In addition, wafer 320 is configured in loading end 312b and goes up and be positioned at the first perforate 314a, and the electric connection mutually at least wherein of wafer 320 and these contact connection pads 312d.In this mandatory declaration is that in first embodiment, the external form of the first perforate 314a for example is a rectangle, but the external form of the first perforate 314a still can be done different variations according to design requirement.
See also Fig. 2 A, wafer encapsulation body 300 for example more comprises most projections 330, primer layer 340 and electrical contact (electric contact) 350.These projections 330 are configured between wafer 320 and the internal connection-wire structure 312, and wafer 320 is to electrically connect mutually by these projections 330 with the first internal wiring 312a.In addition, the material of these projections 330 for example is a scolder (solder).In addition, primer layer 340 and coats these projections 330 between wafer 320 and coreless capsulation substrates 310.Primer layer 340 is in order to protecting these projections 330, and can cushion between coreless capsulation substrates 310 and the wafer 320 when being heated the unmatched phenomenon of the thermal strain that both produced simultaneously.Via as can be known above-mentioned, in first embodiment, be wafer 320 to be connected to internal connection-wire structure 312 in structure and electrically by these projections 330.In addition, in another embodiment, still can use anisotropic conductive (ACF) wafer 320 is connected to internal connection-wire structure 312 in structure and electrically.
In first embodiment, these electrical contacts 350 for example are conducting sphere (conductive ball), it is configured in respectively on these contact connection pads 312d, in order to electrically connect the electronic installation of next level, printed circuit board (PCB) (Fig. 2 A does not illustrate) for example, but also can be conduction stitch (conductive pin) or conductive pole (conductive column), look closely design requirement and decide.What deserves to be mentioned is that under situation about a plurality of electrical contacts 350 not being disposed respectively to these contact connection pads 312d, these contact connection pads 312d can be applicable to fill up lattice array (land grid array, LGA) the signal output-input interface of type.In addition, if these electrical contact 350 conducting spheres, then in order to sphere grid array (ball gridarray, BGA) the signal output-input interface of type to be provided.In addition, if these electrical contacts 350 are conduction stitch, then in order to pin lattice array (pin grid array, PGA) the signal output-input interface of type to be provided; If these electrical contacts 350 are conductive pole, then in order to pillar grid array (column gridarray, CGA) the signal output-input interface of type to be provided.
See also Fig. 2 A, internal connection-wire structure 312 comprises most dielectric layer 312e, most individual conduction duct 312f and most line layer 312g.The material of these dielectric layers 312e for example is BT, ABF or epoxy resin (epoxy resin), and each conduction duct 312f (its material for example is copper) then runs through one of them of these dielectric layers 312e.In addition, these a few line layer 312g and these dielectric layers 312e are interconnected, and these line layers 312g and these conduction duct 312f constitutes the first internal wiring 312a, and between the two line layer 312g be by these conductions duct 312f at least one of them and electrically connect mutually.In addition, the processing procedure of coreless capsulation substrates 310 for example is prior to forming internal connection-wire structure 312 in the mode that increases layer (build-up) on the lower surface of a ceramic wafer (Fig. 2 A does not illustrate), forming one again and run through the first perforate 314a of ceramic wafer to form ceramic support slab 314 on the upper surface of ceramic wafer.
See also Fig. 3 A, illustrate the generalized section of the wafer encapsulation body of the utility model second embodiment, Fig. 3 B illustrates the schematic top plan view of the wafer encapsulation body of Fig. 3 A.See also Fig. 3 A and Fig. 3 B, first embodiment has similar structure to second embodiment, but both main differences be in, the ceramic support slab 414 of the wafer encapsulation body 400 of second embodiment can comprise at least one second perforate 414b (Fig. 3 B illustrates two), wherein for example dispose at least one electronic component 460 (Fig. 3 B illustrates three altogether) in each second perforate 414b, and these electronic components 460 electrically connect mutually with the first internal wiring 412a.In addition, these electronic components 460 for example are configured on the loading end 412b by the surface adhering technology, and these electronic components 460 can be passive device or integrated circuit components (IC component) such as capacitor, inductor and resistor.In this mandatory declaration is that among second embodiment, the external form of the second perforate 414b for example is a rectangle, but the external form of the second perforate 414b still can be done different variations according to design requirement.
See also Fig. 4, it illustrates the generalized section of the wafer encapsulation body of the utility model the 3rd embodiment.The 3rd embodiment and first embodiment also have similar structure, but both main differences be in, the ceramic support slab 314 of the wafer encapsulation body 300 of first embodiment only is single ceramic layer, but 514 of the ceramic support slabs of the wafer encapsulation body 500 of the 3rd embodiment can comprise most ceramic dielectric layers 514d, most individual conduction duct 514e and most line layer 514f.Each conduction duct 514e runs through one of these ceramic dielectric layers 514d.In addition, these line layers 514f and these ceramic dielectric layers 514d are interconnected, and these line layers 514f and these conductions duct 514e constitute the second internal wiring 514c, and are to electrically connect mutually by at least one of these conductions duct 514e between the two line layer 514f.In addition, wherein at least one electronic component 560 for example is configured on the ceramic support slab 514 by the surface adhering technology, and electrically connect mutually with the second internal wiring 514c, and these electronic components 560 can be passive device or integrated circuit components such as capacitor, inductor and resistor.
In this mandatory declaration is that in the 3rd embodiment, the second internal wiring 514c electrically connects mutually with the first internal wiring 512a, but both also can be according to design requirement electrically connect each other mutually.In addition, second embodiment and the 3rd embodiment can be according to design requirement matched combined, but do not illustrate with drawing in this.
In sum, the coreless capsulation substrates of wafer encapsulation body of the present utility model has the following advantages at least:
(1) because the ceramic support slab of the coreless capsulation substrates of wafer encapsulation body of the present utility model has stronger stiffness, this is compared to metal profile, therefore in the process of making coreless capsulation substrates, ceramic support slab is difficult for buckling deformation and can reduces the residual stress of coreless capsulation substrates, and then promotes coplane (coplanarity) property of coreless capsulation substrates;
(2) because the coreless capsulation substrates of wafer encapsulation body of the present utility model does not have the plated-through-hole road, so the wiring density of coreless capsulation substrates can promote;
(3) because the ceramic support slab of the coreless capsulation substrates of wafer encapsulation body of the present utility model has second perforate or second internal wiring, therefore can be so that electronic component arrangements in second perforate or on the ceramic support slab, and then increase the area of electronic component arrangements.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; anyly have the knack of this skill person; in not breaking away from spirit and scope of the present utility model; when can doing a little change and retouching, therefore protection range of the present utility model is aforesaidly applied for a patent the scope that technical scheme defines and is as the criterion when looking.
Claims (10)
1, a kind of wafer encapsulation body is characterized in that it comprises:
One coreless capsulation substrates comprises:
One internal connection-wire structure has one first internal wiring, a loading end and a corresponding contact face, and this first internal wiring has most contact connection pads, and it is positioned on this contact face; And
One ceramic support slab is configured on this loading end, and has one first perforate; And
One wafer is configured on this loading end and is positioned at this first perforate, and this wafer electrically connects mutually with at least one of those contact connection pads.
2, wafer encapsulation body according to claim 1 more comprises most projections, and it is configured between this wafer and this internal connection-wire structure, and this wafer is to electrically connect mutually by those projections with this first internal wiring.
3, wafer encapsulation body according to claim 1, wherein this internal connection-wire structure comprises:
A most dielectric layer;
Most conduction ducts, respectively one of those dielectric layers are run through in this conduction duct; And
Most line layers, with those dielectric layers be interconnected, and those line layers constitute this first internal wiring with those conduction ducts, and are by at least one of those conduction ducts and electric connection mutually between two those line layers.
4, wafer encapsulation body according to claim 1, wherein this ceramic support slab comprises at least one second perforate.
5, wafer encapsulation body according to claim 4, wherein at least one electronic component arrangements are in this second perforate, and this electronic component electrically connects mutually with this first internal wiring.
6, wafer encapsulation body according to claim 5, wherein this electronic component comprises passive device.
7, wafer encapsulation body according to claim 5, wherein this electronic component comprises integrated circuit component.
8, wafer encapsulation body according to claim 1, wherein this ceramic support slab comprises:
A most ceramic dielectric layers;
Most conduction ducts, respectively one of those ceramic dielectric layers are run through in this conduction duct; And
Most line layers, with those ceramic dielectric layers be interconnected, and those line layers constitute this second internal wiring with those conduction ducts, and are by at least one of those conduction ducts and electric connection mutually between two those line layers.
9, wafer encapsulation body according to claim 8, wherein at least one electronic component arrangements are on this ceramic support slab, and this electronic component electrically connects mutually with this second internal wiring.
10, wafer encapsulation body according to claim 9, wherein this electronic component comprises passive device or integrated circuit component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520147476 CN2881956Y (en) | 2005-12-26 | 2005-12-26 | Chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520147476 CN2881956Y (en) | 2005-12-26 | 2005-12-26 | Chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2881956Y true CN2881956Y (en) | 2007-03-21 |
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ID=37881797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200520147476 Expired - Lifetime CN2881956Y (en) | 2005-12-26 | 2005-12-26 | Chip package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2881956Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543927A (en) * | 2010-12-14 | 2012-07-04 | 欣兴电子股份有限公司 | Packaging substrate with embedded through-hole interposer and manufacturing method thereof |
| CN103107144A (en) * | 2011-11-10 | 2013-05-15 | 钰桥半导体股份有限公司 | Three dimensional semiconductor assembly board |
-
2005
- 2005-12-26 CN CN 200520147476 patent/CN2881956Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543927A (en) * | 2010-12-14 | 2012-07-04 | 欣兴电子股份有限公司 | Packaging substrate with embedded through-hole interposer and manufacturing method thereof |
| CN102543927B (en) * | 2010-12-14 | 2014-12-10 | 欣兴电子股份有限公司 | Packaging substrate with embedded through-hole interposer and manufacturing method thereof |
| CN103107144A (en) * | 2011-11-10 | 2013-05-15 | 钰桥半导体股份有限公司 | Three dimensional semiconductor assembly board |
| CN103107144B (en) * | 2011-11-10 | 2015-07-08 | 钰桥半导体股份有限公司 | Three dimensional semiconductor assembly board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070321 |
|
| EXPY | Termination of patent right or utility model |