CN101030565A - High-frequency IC circuit packing structure and its production - Google Patents
High-frequency IC circuit packing structure and its production Download PDFInfo
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- CN101030565A CN101030565A CNA2006100578483A CN200610057848A CN101030565A CN 101030565 A CN101030565 A CN 101030565A CN A2006100578483 A CNA2006100578483 A CN A2006100578483A CN 200610057848 A CN200610057848 A CN 200610057848A CN 101030565 A CN101030565 A CN 101030565A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000012856 packing Methods 0.000 title description 18
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 120
- 238000005538 encapsulation Methods 0.000 claims description 80
- 239000011231 conductive filler Substances 0.000 claims description 41
- 239000013078 crystal Substances 0.000 claims description 41
- 239000000853 adhesive Substances 0.000 claims description 29
- 230000001070 adhesive effect Effects 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 25
- 238000000576 coating method Methods 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 66
- 235000012431 wafers Nutrition 0.000 description 65
- 238000010586 diagram Methods 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000007639 printing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 210000000481 breast Anatomy 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/301—Electrical effects
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Abstract
The invention is concerned with the conformation and the manufacture method of the high frequency integrated circuit, it comprising of: the base plate, the protruding chip and plural number of conducting filling. The base plat consists of the circuit layer and plural number of protruding containing via hole crossing from upper surface to bottom surface. The initiative surface of the protruding chip sticks to the upper surface of the base plate in order that the plural number of the protruding blocks of the protruding chip contains in the corresponding protruding containing via hole. The conducting filling forms in the protruding containing via hole in order to electric connect the protruding blocks to the circuit layer.
Description
Technical field
The present invention relates to a kind of high-frequency integrated circuit encapsulation structure and manufacture method thereof, particularly relate to a kind of high frequency memory chip packaging structure and manufacture method thereof (High frequent IC package andmethod for fabricating the same).
Background technology
In integrated circuit (being integrated circuit) packaging structure, the method that electrically connects wafer and substrate mainly is to can be routing (wire-bonding) mode to electrically connect wafer and substrate, or adopt overlay crystal chip to engage (flip chip mounting) mode, make the projection on overlay crystal chip surface directly be engaged to substrate, to finish the electric connection between substrate and the wafer, two kinds of above-mentioned methods can be implemented according to this at the IC circuit packing structure of various objectives and purposes.
Seeing also shown in Figure 1ly, is a kind of schematic cross-section of existing known routing kenel IC circuit packing structure.Existing known routing kenel IC circuit packing structure 100 comprises a substrate 110, a wafer 120 and a plurality of bonding wire 130.This substrate 110 is to have a upper surface 111 and a lower surface 112, as shown in Figure 2, it is the base lower surface schematic diagram that has known IC circuit packing structure now, wherein this substrate 110 has a long and narrow fluting 114, and the long and narrow fluting of this of this lower surface 112 114 both sides are provided with a plurality of connection gaskets 113.One active surface 121 of this wafer 120 is to be formed with a plurality of weld pads 122, this wafer 120 is the upper surfaces 111 that are arranged at substrate 110, long and narrow fluting 114 manifests those all weld pads 122 during routing, those bonding wires 130 that routing forms are with those weld pads 122 of electric connection wafer 120 and those connection gaskets 113 of substrate 110 by long and narrow fluting 114, and with an adhesive body 140 sealing wafers 120 and those bonding wires 130, with sealing wafer 120 and those bonding wires 130, the lower surface 112 of this substrate 110 is formed with a plurality of ball pads 115, for a plurality of soldered balls 150 are set, and then (Surface Mount Technology is SMT) to a printed circuit board (PCB) can to make packaging structure 100 outer surface joint.Yet for the electronic product of needs height computing, the transmission speed of the IC circuit packing structure 100 of this routing kenel can't meet demand, and when forming this adhesive body 140 with pressing mold, can breast the tape and makes those bonding wire 130 short circuits.
Seeing also shown in Figure 3ly, is the schematic cross-section of another kind of existing known flip chip type attitude IC circuit packing structure.This another kind has known flip chip type attitude IC circuit packing structure 200 now, comprises a substrate 210, an overlay crystal chip 220 and a underfill 230.This substrate 210 is to be a kind of bilayer or multilayer circuit board, as shown in Figure 4, it is the base lower surface schematic diagram that has known IC circuit packing structure now, this substrate 210 has a plurality of vias 214 to electrically conduct at the connection gasket 213 of the upper surface 211 of substrate 210 and ball pad 216 at its lower surface 212, this upper surface 211 is that definition has one to cover crystalline region 215, and its size is corresponding to overlay crystal chip 220.This overlay crystal chip 220 has an active surface 221 and plurality of bump 223, those projections 223 are for arranged and are arranged on a plurality of heavy distribution weld pads 222 that it is to utilize heavy distributed lines layer (not drawing among a figure) connecting wafer weld pad of wafer 220 inside to those heavy distribution weld pads 222.Those projections 223 are a plurality of connection gaskets 213 that are engaged to substrate 210, make between overlay crystal chip 220 and the substrate 210 to reach electric connection, again with those projections 223 of underfill 230 seal protections.And the lower surface 212 of this substrate 210 is to be formed with a plurality of ball pads 216, and a plurality of soldered balls 240 are to be arranged on those ball pads 216, for being external to a circuit board.Though this flip chip type attitude IC circuit packing structure 200 can reach the demand of the electronic product of height computing, but because substrate 210 is to be the circuit board of multilayer line, and overlay crystal chip 220 needs to make a heavy distributed lines layer, therefore the cost of substrate 210 and overlay crystal chip 220 all is higher than existing known memory chip and encapsulates employed substrate and wafer, (memory body is a storage medium and be not suitable for the high frequency memory body, memory, internal memory below all is called memory body) encapsulation of wafer.In addition, the thickness of overall package structure is also thicker.
This shows that above-mentioned existing integrated circuits packaging structure and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in product structure, manufacture method and use.In order to solve the problem that IC circuit packing structure and manufacture method thereof exist, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new high-frequency integrated circuit encapsulation structure and manufacture method thereof, just become the current industry utmost point to need improved target.
Because the defective that above-mentioned existing integrated circuits packaging structure and manufacture method thereof exist, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new high-frequency integrated circuit encapsulation structure and manufacture method thereof, can improve general existing integrated circuits packaging structure and manufacture method thereof, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective that the existing integrated circuits packaging structure exists, and provide a kind of new high-frequency integrated circuit encapsulation structure, technical problem to be solved is to make it can shorten electrical conducting path between substrate and the wafer, and do not need additionally to increase the cost of manufacture of substrate and wafer, thereby be suitable for practicality more.
A time purpose of the present invention is, a kind of new high-frequency integrated circuit encapsulation structure is provided, and technical problem to be solved is that to make substrate be single layer board, utilizes bump height hiding of thin substrate and wafer, and can reach the thinning of overall package.In addition, can also reduce production costs, thereby be suitable for practicality more.
Another object of the present invention is to, a kind of new high-frequency integrated circuit encapsulation structure is provided, technical problem to be solved is to make gluing wafer and substrate person be the glutinous crystal layer of a patterning, it is to have the gummosis passage, fill up gap between this wafer and this substrate in order to an adhesive body, and help the discharge of volatilization gas during reflow again of the outer conductive filler of projection or projection, thereby be suitable for practicality more.
A further object of the present invention is, a kind of manufacture method of new high-frequency integrated circuit encapsulation structure is provided, technical problem to be solved is to make it can replace the routing processing procedure, shorten electrical conducting path between substrate and the wafer, and can make the thinner easier control of package thickness, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of high-frequency integrated circuit encapsulation structure that the present invention proposes, it comprises: a substrate, and it has a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface, and this substrate comprises a line layer; One wafer, it has an active surface and a plurality of projection on this active surface, and wherein this active surface is this upper surface that is attached at this substrate, and those projections are placed in the corresponding ccontaining through hole of those projections; And the plural conductive filler, it is formed in the ccontaining through hole of those projections, and electrically connects those projections to this line layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said line layer includes a plurality of connection gaskets, and it is a wherein ora terminalis that is positioned at the ccontaining through hole of those projections.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those connection gaskets are to be annular, with the ccontaining through hole of those projections around correspondence, this substrate includes a welding cover layer in addition, it is formed at this lower surface, wherein this welding cover layer is local those connection gaskets of covering, defines pad (SMD pad) so that those connection gaskets become the weldering cover.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said substrate are the individual layer circuit soft boards for a shortage plated-through-hole (PTH).
Aforesaid high-frequency integrated circuit encapsulation structure, wherein the inwall at the ccontaining through hole of those projections is to be formed with an electrodeposited coating, it is to be electrically connected to this line layer.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those conductive fillers are to be scolder or conducting resinl.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those conductive fillers also are formed on a plurality of outer connection pad of this line layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of high-frequency integrated circuit encapsulation structure that proposes according to the present invention, it may further comprise the steps: a substrate is provided, this substrate has a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface, and this substrate comprises a line layer; One wafer is set in this substrate, this wafer has an active surface and a plurality of projection on this active surface, and wherein this active surface is this upper surface that is attached at this substrate, is to be placed in the corresponding ccontaining through hole of those projections and make those projections; And forming the plural conductive filler in the ccontaining through hole of those projections, those conductive fillers are to electrically connect those projections to this line layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said line layer are to include a plurality of connection gaskets, and it is a wherein ora terminalis that is positioned at the ccontaining through hole of those projections.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said substrate are the individual layer circuit soft boards for a shortage plated-through-hole (PTH).
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein the inwall at the ccontaining through hole of those projections is to be formed with an electrodeposited coating, it is to be electrically connected to this line layer.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said those conductive fillers are to be scolder or conducting resinl.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.According to a kind of high-frequency integrated circuit encapsulation structure that the present invention proposes, it comprises: a substrate, and it has a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface; One wafer, it has an active surface and a plurality of projection on this active surface; One patterning sticks crystal layer, and it is to stick this active surface of this wafer and this upper surface of this substrate, and to make those projections be to be placed in the corresponding ccontaining through hole of those projections, and the glutinous crystal layer of this patterning is to be formed with the gummosis passage; And an adhesive body, it is formed between this wafer and this substrate at least and fills up this gummosis passage of the glutinous crystal layer of this patterning, to coat the glutinous crystal layer of this patterning and again in conjunction with this wafer and this substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid high-frequency integrated circuit encapsulation structure, the glutinous crystal layer of wherein said patterning is made up of a plurality of projections that stick together.
Aforesaid high-frequency integrated circuit encapsulation structure, the glutinous crystal layer of wherein said patterning is the B rank mucigel that forms for a patterned print.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said adhesive body are to be underfill.
Aforesaid high-frequency integrated circuit encapsulation structure, it includes the plural conductive filler in addition, and it is to be formed in the ccontaining through hole of those projections, so that those projections are electrically connected to substrate.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said substrate are a pliability circuit substrate.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, major technique of the present invention thes contents are as follows:
According to the present invention, a kind of high-frequency integrated circuit encapsulation structure mainly comprises a substrate, a wafer and plural conductive filler.This substrate is to have a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface, and comprise a line layer, this wafer is to have an active surface and a plurality of projection on this active surface, this active surface is this upper surface that is attached at this substrate, and make those projections is to be placed in the corresponding ccontaining through hole of those projections, those conductive fillers are to be formed in the ccontaining through hole of those projections, and electrically connect those projections to this line layer.
By technique scheme, high-frequency integrated circuit encapsulation structure of the present invention and manufacture method thereof have following advantage at least:
High-frequency integrated circuit encapsulation structure of the present invention, the one substrate is to have a upper surface, a lower surface and a plurality of this upper surface that runs through are to the ccontaining through hole of the projection of this lower surface, when glutinous crystalline substance, the plurality of bump of one wafer is to be placed in the corresponding ccontaining through hole of those projections, the plural conductive filler is to be formed in the ccontaining through hole of those projections, to electrically connect the line layer of those projections to this substrate, and can shorten electrical conducting path between this substrate and this wafer, and do not need additionally to increase the cost of manufacture of substrate and wafer, and have industrial utilization.
High-frequency integrated circuit encapsulation structure of the present invention, wherein this substrate is the single layer board for a shortage plated-through-hole (PTH), those conductive fillers that are formed in the ccontaining through hole of those projections are to be scolder or conducting resinl, because this substrate is a single layer board, so the bump height of thin substrate of utilization and wafer is hiding, and can reach the thinning of overall package.In addition, can also reduce production costs.
High-frequency integrated circuit encapsulation structure of the present invention, it is when glutinous crystalline substance, the plurality of bump of one wafer is to be placed in accordingly in the ccontaining through hole of plurality of bump of a substrate, wherein this wafer of gluing and this substrate person are the glutinous crystal layer of a patterning, it is to have the gummosis passage, fill up gap between this wafer and this substrate and can be beneficial to an adhesive body, and can help the discharge of projection or the outer conductive filler volatilization gas when reflow of projection, be very suitable for practicality.
The manufacture method of high-frequency integrated circuit encapsulation structure of the present invention can replace the routing processing procedure, shortens electrical conducting path between substrate and the wafer, and can make the thinner easier control of package thickness, thereby be suitable for practicality more.
In sum, the high-frequency integrated circuit encapsulation structure of novelty of the present invention and manufacture method thereof, have electrical conducting path short, prevent the effect of breasting the tape and encapsulating thinning.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure, manufacture method or function, have technically than much progress, and produced handy and practical effect, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a kind of schematic cross-section that has known routing kenel IC circuit packing structure now.
Fig. 2 is the base lower surface schematic diagram that has known IC circuit packing structure now.
Fig. 3 is the another kind of schematic cross-section that has known flip chip type attitude IC circuit packing structure now.
Fig. 4 is the base lower surface schematic diagram that has known IC circuit packing structure now.
Fig. 5 is according to first specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure.
Fig. 6 is according to first specific embodiment of the present invention, the lower surface schematic diagram of the substrate of this high-frequency integrated circuit encapsulation structure.
Fig. 7 is according to first specific embodiment of the present invention, the schematic partial cross-sectional view of the substrate of this high-frequency integrated circuit encapsulation structure.
Fig. 8 is according to second specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure.
Fig. 9 is according to the 3rd specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure.
Figure 10 is according to the 3rd specific embodiment of the present invention, and the upper surface of the substrate of this high-frequency integrated circuit encapsulation structure has been formed with the schematic diagram of the glutinous crystal layer of patterning.
100: routing kenel IC circuit packing structure 110: substrate
111: upper surface 112: lower surface
113: connection gasket 114: long and narrow fluting
115: ball pad 120: wafer
121: active surface 122: weld pad
130: bonding wire 140: adhesive body
150: soldered ball 200: flip chip type attitude IC circuit packing structure
210: substrate 211: upper surface
212: lower surface 213: connection gasket
214: via 215: cover the crystalline region
216: ball pad 220: overlay crystal chip
221: active surface 222: heavily distribute weld pad
223: projection 230: underfill
240: soldered ball 300: high-frequency integrated circuit encapsulation structure
310: substrate 311: upper surface
312: lower surface 313: the ccontaining through hole of projection
314: line layer 315: connection gasket
316: welding cover layer 317: outer connection pad
320: wafer 321: active surface
322: weld pad 323: projection
324: glutinous crystal layer 330: conductive filler
340: 350: the first adhesive bodies of soldered ball
410: substrate 411: upper surface
412: lower surface 413: the ccontaining through hole of projection
414: line layer 415: connection gasket
416: outer connection pad 420: wafer
421: active surface 422: weld pad
423: projection 424: glutinous crystal layer
430: conductive filler 440: soldered ball
460: the second adhesive bodies of 450: the first adhesive bodies
500: high-frequency integrated circuit encapsulation structure 510: substrate
511: upper surface 512: lower surface
513: the ccontaining through hole 514 of projection: electrodeposited coating
515: line layer 516: outer connection pad
520: wafer 521: active surface
522: weld pad 523: projection
524: the back side 530: patterning sticks crystal layer
531: gummosis passage 540: conductive filler
552: the second adhesive bodies of 551: the first adhesive bodies
560: soldered ball
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to high-frequency integrated circuit encapsulation structure and its embodiment of manufacture method, structure, manufacture method, step, feature and the effect that foundation the present invention proposes, describe in detail as after.
Seeing also shown in Figure 5ly, is according to first specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure.The high-frequency integrated circuit encapsulation structure 300 of the present invention's first concrete preferred embodiment comprises that mainly a substrate 310, is provided with the wafer 320 and the plural conductive filler 330 of plurality of bump 323.
In the present embodiment, this substrate 310, it is the individual layer circuit soft board for a shortage plated-through-hole (PTH), for example circuit films such as COF, TCP or PI.This substrate 310 has a upper surface 311, a lower surface 312 and a plurality of this upper surface 311 that runs through to the ccontaining through hole 313 of the projection of this lower surface 312 and include a line layer 314.In the present embodiment, the ccontaining through hole 313 of those projections is to be cylindrical hole, and its aperture only is a bit larger tham the external diameter of those projections 323, and this line layer 314 is to be formed at lower surface 312, and includes a plurality of connection gaskets 315.
Please shown in Figure 6 in conjunction with consulting, it is lower surface schematic diagram according to the substrate of this high-frequency integrated circuit encapsulation structure in the present invention's first specific embodiment, preferably, those connection gaskets 315 are the below ora terminalis that are positioned at the ccontaining through hole 313 of those projections, it is to be hollow ring, with the ccontaining through hole 313 of those projections, for the joint of conductive filler 330 around correspondence.
Please shown in Figure 7 in conjunction with consulting, it is schematic partial cross-sectional view according to the substrate of this high-frequency integrated circuit encapsulation structure in the present invention's first specific embodiment, this substrate 310 includes a welding cover layer 316, it is to be formed at lower surface 312, this welding cover layer 316 is local outer rim and lateral walls that cover those connection gaskets 315, so that becoming the weldering cover, those connection gaskets 315 define pad (SMD pad, Solder Mask Definedpad), with the pull-out capacity that increases those connection gaskets 315 and prevent conductive filler 330 diffusions.In addition, the line layer 314 of this substrate 310 includes a plurality of outer connection pads 317 in addition, is to be provided with a plurality of soldered balls 340 on those outer connection pads 317, and (Ball Grid Array, encapsulation kenel BGA) is for connecting an external circuits plate and become sphere grid array.
This wafer 320 is to have an active surface 321.In the present embodiment, this wafer 320 is to be a Dynamic Random Access Memory wafer (DRAM), refers in particular to high frequency memory chips such as above doubly fast data transmission DDR II of 333MHz or DDR III.In addition, this wafer 320 also has those projections 323 through projectionization, and it is to be arranged on a plurality of weld pads 322 of active surface 321.This active surface 321 is the upper surfaces 311 that are attached at substrate 310 with a glutinous crystal layer 324, and those projections 323 are to be placed in the corresponding ccontaining through hole 313 of those projections when glutinous crystalline substance, the height that is beneficial to reach indivedual electrical isolation of those projections 323 and hides those projections 323.Wherein, this glutinous crystal layer 324 can be that printing forms and through the B rank of prebake conditions mucigel, non-conductive glue (Non-Conductive Paste, NCP) or other glutinous brilliant material commonly used.
Those conductive fillers 330 are formed in the ccontaining through hole 313 of those projections, make those projections 323 be electrically connected to those corresponding connection gaskets 315, with the electrical interconnects between the line layer 314 that reaches wafer 320 and substrate 310.Usually those projections 323 are to can be to electroplate column-like projection block or the spherical projection or the tie lines projection (stud bump) of routing formation that forms, and its material can be gold, tin lead or copper tin silver etc.Those conductive fillers 330 are to be scolder or conducting resinl, can utilize lower surface 312 modes that are printed in substrate 310 to form.Preferably, those conductive fillers 330 also are formed on those outer connection pads 317, are engaged to an external printed circuit board (not drawing among the figure) in order to the setting or the direct surface that engage those soldered balls 340.
This high-frequency integrated circuit encapsulation structure 300 can include one first adhesive body 350 in addition, and in the present embodiment, this first adhesive body 350 is to be formed at the lower surface 312 of substrate 310 and to seal those conductive fillers 330 with pressing mold (molding) or spot printing mode.And this high-frequency integrated circuit encapsulation structure 300 also can include one second adhesive body 360, this second adhesive body 360 is to form in the pressing mold mode, and injecting glue is with the upper surface 311 that is formed at substrate 310 and the side that seals wafer 320 and the back side and glutinous crystal layer 324 in mould.Make wafer 320 be electrically connected to substrate 310 by those projections 323 and conductive filler 330, and have the effect that shortens electrical conducting path.In addition, because those projections 323 are to be placed in corresponding projection perforate 313 individually, and substrate 310 is to be the individual layer circuit soft board, and can make these packaging structure 300 thinnings and can reduce production costs.
In addition, seeing also shown in Figure 8ly, is according to second specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure.In the of the present invention second concrete preferred embodiment, this high-frequency integrated circuit encapsulation structure 400 mainly comprises a substrate 410, a wafer 420 and plural conductive filler 430.
This substrate 410, it has a upper surface 411, a lower surface 412 and a plurality of ccontaining through hole 413 of projection that runs through this lower surface 412 by this upper surface 411, and include a line layer 414, can be formed at this lower surface 412 or this upper surface 411, this line layer 414 includes a plurality of connection gaskets 415, and those connection gaskets 415 are the below ora terminalis that are positioned at the ccontaining through hole 413 of those projections.
This wafer 420, be to be a Dynamic Random Access Memory wafer, it has an active surface 421 and plurality of bump 423, this active surface 421 is to be attached at the upper surface 411 of substrate 410 by a glutinous crystal layer 424, is to be placed in the corresponding ccontaining through hole 413 of those projections and make those projections 423 on a plurality of weld pads 422 of active surface 421.
Those conductive fillers 430 are to be formed in the ccontaining through hole 413 of those projections, to electrically connect those projections 423 to line layer 414.Usually those conductive fillers 430 are to be scolder or conducting resinl.In the present embodiment, one first adhesive body 450 is to be formed at the lower surface 412 of substrate 410 to seal those conductive fillers 430 in the spot printing mode.
This high-frequency integrated circuit encapsulation structure 400 can include one second adhesive body 460 in addition, the curing colloid that forms of underfill or other spot printing for example, this second adhesive body 460 is the upper surfaces 411 that are formed at substrate 410, and it is the local side that appears part and wafer 420 that covers glutinous crystal layer 424.Preferably, the line layer 414 of this substrate 410 is to include a plurality of outer connection pads 416, and a plurality of soldered balls 440 can be arranged on those outer connection pads 416, can be for connecting an external circuits plate.As shown in Figure 8, those projections 423 are to be placed in the corresponding ccontaining through hole 413 of those projections, and the substrate 410 of this IC circuit packing structure 400 is to can be an individual layer circuit soft board, and have the effect of encapsulation thinning.In addition, this second adhesive body 460 only spot printing is formed at the side periphery of wafer 420, can fall the consumption of few adhesive body, and appears the back side of this wafer 420 and can promote thermal diffusivity.
Seeing also shown in Figure 9ly, is according to the 3rd specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure, and the present invention's the 3rd concrete preferred embodiment is the another kind of high-frequency integrated circuit encapsulation structure of exposure.This high-frequency integrated circuit encapsulation structure 500 mainly comprises a substrate 510, a wafer 520, the glutinous crystal layer 530 of a patterning and plural conductive filler 540.
This substrate 510 has a upper surface 511, a lower surface 512 and a plurality of this upper surface 511 that runs through to the ccontaining through hole 513 of the projection of this lower surface 512, and comprises a line layer 515.Wherein the hole inwall of the ccontaining through hole 513 of those projections is to be formed with an electrodeposited coating 514, and it is to electrically connect with this line layer 515.
This wafer 520, have an active surface 521 and plurality of bump 523, those projections 523 are arranged on a plurality of weld pads 522 on this active surface 521, and those projections 523 are the middle positions that can be arranged in this active surface 521, also can be arranged in the peripheral position of this active surface 521.Stick the active surface 521 of wafer 520 and the upper surface 511 of substrate 510 by the glutinous crystal layer 530 of this patterning, and to make those projections 523 be to be placed in the corresponding ccontaining through hole 513 of those projections.
In the present embodiment, seeing also shown in Figure 10ly, is the schematic diagram that has been formed with the glutinous crystal layer of patterning according to the upper surface of the substrate of this high-frequency integrated circuit encapsulation structure in the 3rd specific embodiment of the present invention.This patterning sticks crystal layer 530, is made up of a plurality of projections that stick together, and can be circle or other shape, and the glutinous crystal layer 530 (being that those stick together between the projection) of this patterning is formed with a plurality of gummosis passages 531.The generation type of the glutinous crystal layer 530 of this patterning then can be formed at the active surface 521 of wafer 520 or the upper surface 511 of substrate 510 with a kind of liquid glue that can multistage curing with patterned print technology such as screen printing, mould printings in advance, is roasted into a B rank mucigel through preliminary drying again.
Those conductive fillers 540 are to be formed in the ccontaining through hole 513 of those projections, can be via reflow steps, and to electrically connect those projections 523 to those electrodeposited coatings 514 and then be electrically connected to line layer 515.And the circuit of this line layer 515 is to be electrically connected to a plurality of outer connection pads 516.In addition, first adhesive body 551 of an electrical insulating property is the lower surface 512 that can be formed at substrate 510, to cover the ccontaining through hole 513 of those projections and those conductive fillers 540.A plurality of soldered balls 560 are to be engaged in those outer connection pads 516, promptly are arranged at the lower surface 512 of substrate 510.
Therefore, the present invention is that to utilize those projections 523 of wafer 520 be the ccontaining through hole 513 of those projections of correspondence that individually is placed in substrate 510 when glutinous brilliant, and those projections 523 are towards being imported by upper surface 511 directions by the ccontaining through hole 513 of those projections; And those conductive fillers 540 and first adhesive body 551 can be by the ccontaining through hole 513 of those projections towards being inserted by lower surface 512 directions.Electrically connect in those projections 523 and the ccontaining through hole 513 of those projections electrodeposited coatings 514 and then electrically conduct to line layer 515 by those conductive fillers 540.Therefore, the present invention has the effect that is issued to encapsulation thinning, electrical conducting path weak point and prevents to breast the tape in the cost of manufacture that does not additionally increase substrate and wafer, is specially adapted to a large amount of encapsulation of high frequency memory chip.
In addition, this high-frequency integrated circuit encapsulation structure 500 can comprise one second adhesive body 552 in addition, it is the gummosis passage 531 that is formed between wafer 520 and the substrate 510 at least and fills up the glutinous crystal layer 530 of patterning, coating the glutinous crystal layer 530 of this patterning and, and strengthen the anchorage of this wafer 520 again in conjunction with wafer 520 and substrate 510.In the present embodiment, this second adhesive body 552 is to be underfill.Therefore, this second adhesive body 552 can fill up the gap between wafer 520 and the substrate 510, avoids the bag that returns of bubble to form, and helps those projections 523 or be positioned at the discharge of conductive filler 540 volatilization gas when reflow of those projection 523 outsides.Moreover the glutinous crystal layer 530 of this patterning also has the function that buffering is disperseed for the thermal stress that acts on wafer 520.When substrate 510 is during for the pliability circuit substrate, have more benefiting of stress buffer.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1, a kind of high-frequency integrated circuit encapsulation structure is characterized in that it comprises:
One substrate, it has a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface, and this substrate comprises a line layer;
One wafer, it has an active surface and a plurality of projection on this active surface, and wherein this active surface is this upper surface that is attached at this substrate, and those projections are placed in the corresponding ccontaining through hole of those projections; And
The plural conductive filler, it is formed in the ccontaining through hole of those projections, and electrically connects those projections to this line layer.
2, high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said line layer includes a plurality of connection gaskets, and it is a wherein ora terminalis that is positioned at the ccontaining through hole of those projections.
3, high-frequency integrated circuit encapsulation structure according to claim 2, it is characterized in that wherein said those connection gaskets are to be annular, with the ccontaining through hole of those projections around correspondence, this substrate includes a welding cover layer in addition, it is formed at this lower surface, wherein this welding cover layer is local those connection gaskets of covering, defines pad (SMD pad) so that those connection gaskets become the weldering cover.
4, high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said substrate is the individual layer circuit soft board for a shortage plated-through-hole (PTH).
5, high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein the inwall at the ccontaining through hole of those projections is to be formed with an electrodeposited coating, and it is to be electrically connected to this line layer.
6, high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said those conductive fillers are to be scolder or conducting resinl.
7, high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said those conductive fillers also are formed on a plurality of outer connection pad of this line layer.
8, a kind of manufacture method of high-frequency integrated circuit encapsulation structure is characterized in that it may further comprise the steps:
One substrate is provided, and this substrate has a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface, and this substrate comprises a line layer;
One wafer is set in this substrate, this wafer has an active surface and a plurality of projection on this active surface, and wherein this active surface is this upper surface that is attached at this substrate, is to be placed in the corresponding ccontaining through hole of those projections and make those projections; And
Form the plural conductive filler in the ccontaining through hole of those projections, those conductive fillers are to electrically connect those projections to this line layer.
9, the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 8 is characterized in that wherein said line layer is to include a plurality of connection gaskets, and it is a wherein ora terminalis that is positioned at the ccontaining through hole of those projections.
10, the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 8 is characterized in that wherein said substrate is the individual layer circuit soft board for a shortage plated-through-hole (PTH).
11, the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 8 is characterized in that wherein the inwall at the ccontaining through hole of those projections is to be formed with an electrodeposited coating, and it is to be electrically connected to this line layer.
12, the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 8 is characterized in that wherein said those conductive fillers are to be scolder or conducting resinl.
13, a kind of high-frequency integrated circuit encapsulation structure is characterized in that it comprises:
One substrate, it has a upper surface, a lower surface and a plurality of this upper surface that runs through to the ccontaining through hole of the projection of this lower surface;
One wafer, it has an active surface and a plurality of projection on this active surface;
One patterning sticks crystal layer, and it is to stick this active surface of this wafer and this upper surface of this substrate, and to make those projections be to be placed in the corresponding ccontaining through hole of those projections, and the glutinous crystal layer of this patterning is to be formed with the gummosis passage; And
One adhesive body, it is formed between this wafer and this substrate at least and fills up this gummosis passage of the glutinous crystal layer of this patterning, to coat the glutinous crystal layer of this patterning and again in conjunction with this wafer and this substrate.
14, high-frequency integrated circuit encapsulation structure according to claim 13 is characterized in that the glutinous crystal layer of wherein said patterning is made up of a plurality of projections that stick together.
15, high-frequency integrated circuit encapsulation structure according to claim 13 is characterized in that the glutinous crystal layer of wherein said patterning is the B rank mucigel that forms for a patterned print.
16, high-frequency integrated circuit encapsulation structure according to claim 13 is characterized in that wherein said adhesive body is to be underfill.
17, high-frequency integrated circuit encapsulation structure according to claim 13 is characterized in that it includes the plural conductive filler in addition, and it is to be formed in the ccontaining through hole of those projections, so that those projections are electrically connected to substrate.
18, high-frequency integrated circuit encapsulation structure according to claim 13 is characterized in that wherein said substrate is to be a pliability circuit substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100578483A CN100438008C (en) | 2006-03-01 | 2006-03-01 | High-frequency IC circuit packing structure and its production |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100578483A CN100438008C (en) | 2006-03-01 | 2006-03-01 | High-frequency IC circuit packing structure and its production |
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| CN101030565A true CN101030565A (en) | 2007-09-05 |
| CN100438008C CN100438008C (en) | 2008-11-26 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8053907B2 (en) | 2008-07-15 | 2011-11-08 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for forming conductive bumping with copper interconnection |
| CN102171805B (en) * | 2008-12-19 | 2013-09-11 | 英特尔公司 | Bump stress mitigation layer for integrated circuits |
| CN105990299A (en) * | 2015-02-06 | 2016-10-05 | 展讯通信（上海）有限公司 | BGA (Ball Grid Array) packaging structure and preparation method thereof |
| CN107958844A (en) * | 2016-10-14 | 2018-04-24 | 凤凰先驱股份有限公司 | Packaging structure and manufacturing method thereof |
| WO2022166133A1 (en) * | 2021-02-05 | 2022-08-11 | 长鑫存储技术有限公司 | Packaging substrate and semiconductor structure having same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3385872B2 (en) * | 1995-12-25 | 2003-03-10 | 三菱電機株式会社 | Solder supply method and solder supply apparatus |
| JP3610999B2 (en) * | 1996-06-07 | 2005-01-19 | 松下電器産業株式会社 | Mounting method of semiconductor element |
| JP4492233B2 (en) * | 2003-11-27 | 2010-06-30 | 株式会社デンソー | Semiconductor chip mounting structure and semiconductor chip mounting method |
-
2006
- 2006-03-01 CN CNB2006100578483A patent/CN100438008C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8053907B2 (en) | 2008-07-15 | 2011-11-08 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for forming conductive bumping with copper interconnection |
| US8293635B2 (en) | 2008-07-15 | 2012-10-23 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for forming conductive bumping with copper interconnection |
| US8581366B2 (en) | 2008-07-15 | 2013-11-12 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for forming conductive bumping with copper interconnection |
| CN102171805B (en) * | 2008-12-19 | 2013-09-11 | 英特尔公司 | Bump stress mitigation layer for integrated circuits |
| CN105990299A (en) * | 2015-02-06 | 2016-10-05 | 展讯通信（上海）有限公司 | BGA (Ball Grid Array) packaging structure and preparation method thereof |
| CN107958844A (en) * | 2016-10-14 | 2018-04-24 | 凤凰先驱股份有限公司 | Packaging structure and manufacturing method thereof |
| CN107958844B (en) * | 2016-10-14 | 2021-03-26 | 恒劲科技股份有限公司 | Packaging structure and manufacturing method thereof |
| WO2022166133A1 (en) * | 2021-02-05 | 2022-08-11 | 长鑫存储技术有限公司 | Packaging substrate and semiconductor structure having same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100438008C (en) | 2008-11-26 |
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