CN1906799A - 耦合器资源模块 - Google Patents

耦合器资源模块 Download PDF

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CN1906799A
CN1906799A CNA2004800259222A CN200480025922A CN1906799A CN 1906799 A CN1906799 A CN 1906799A CN A2004800259222 A CNA2004800259222 A CN A2004800259222A CN 200480025922 A CN200480025922 A CN 200480025922A CN 1906799 A CN1906799 A CN 1906799A
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layer
circuit
signal processing
assembly
processing circuit
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CN100565870C (zh
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J·J·洛戈赛蒂斯
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Merrimac Industries Inc
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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Waveguide Connection Structure (AREA)

Abstract

一种耦合组件，包括以层叠布局熔融地粘结在一起的多个复合基板层和凸缘层。在凸缘层的顶部设置该基板层并包括连接于信号输入和信号输出的内嵌信号处理电路。贯通基板层一个区域而形成腔，从而露出信号连接端。这些信号连接端耦合于内嵌信号处理电路并且它们能在熔融粘结凸缘层和基板层之后将电路部件添加到组件中，并且能将所添加的部件耦合到信号处理电路。

Description

耦合器资源模块
技术领域
本申请请求提交于2003年9月10日的美国10/659542号专利申请的优先权。
背景技术
平面传输媒介在20世纪50年代年早期的发展对微波电路和元件封装技术产生了较大的冲击。微波印刷电路设计和带状线和微带状线的支持分析理论以很快的步伐产生。早期的带状线电路设计几乎全部专注于无源电路的设计，例如定向耦合器、功率分配器、滤波器和天线馈电网络。早期的配置被容纳在大金属壳体内，并由共轴接插件连接。
为减少尺寸和重量，研制成功了无壳体和无接插件的耦合器。这些后来的配置有时被称为“filmbrids”并包括由焊料或用热塑或热固膜彼此焊接在一起的层压条状线组件。然后在诸如用于这些元件的介电材料的区域中和微波电路制造工序本身的区域中进行进一步纯化。对微波集成电路的发展和应用的历史纵览可在“Microwave Integrated Circuits-An Historical Perspective”，H.Howe，Jr.，IEEE Trans.MTT-S，MTT-32卷、991-996页，1984年9月以及“Microwave Printed Circuit-The early years”，R.M.Barrett，IEEE Trans.MTT-S，MTT-32卷、983-990页，1984年9月中找到。
在多种场合下，对于壳体和封装件以及普通基板上的单版印刷法的各种应用已经集成带状线和微带状元件。集成和封装方法影响系统接口和安装、模块应付后处理温度的能力(即带状线或微带状元件的后续制造)以及模块的工作热学控制能力(即其热传递能力)。集成元件的普遍技术要求使用例如环氧树脂、粘合剂和焊料而将它们结合在一起。在某些场合下，使用环氧树脂、粘合剂和焊料和/或其它粘结剂的模块将受到将模块暴露在高温或其它处理条件下的后续处理步骤的影响。这些后续处理步骤必须与用来形成模块的粘结剂和粘结材料相容。例如，当模块以传统的环氧树脂、粘合剂和焊料形成时，则需要避免高温后处理，由于这样会造成模块粘结的劣化。
所需要的微波耦合器是可经受所要求的更大范围的制造工序的影响的并在这些制造工序中保持其整体性。因此，需要将微波耦合器电路、DC隔离结构、阻抗匹配网络、偏置去耦合结构和RF负载端集成在能够承受高温处理或模块在制造完成后可能遇到的其它处理步骤的结构中。在微波模块与电路组件中其它元件集成的时候可能产生这样的高温处理。另外，还要求将承受理想热传导的微波耦合器电路、DC隔离结构、阻抗匹配网络、偏置去耦合结构和RF负载端集成在一起。此外，还要求可由耦合组件的额外元件后处理而容易地定制的耦合器电路。
发明内容
已公开一种耦合器模块，例如，它可用于微波耦合器、DC隔离结构、阻抗匹配网络、偏置去耦合结构和RF负载端的集成。在本文中也被称为“资源模块”的这种模块具有包括熔融粘结于金属凸缘的多个电路层的多层模块结构。金属凸缘可用于器件安装和热学控制以及封装接口和安装。该资源模块可包括器件安装区域(也被称为贯通于基板层的“资源井”或“腔”)。该资源井允许将器件添加到模块中，并在形成模块本身后，将那些器件耦合到资源模块的电路中。也就是说，可在熔融粘结资源模块层后，将额外器件添加到资源井中。在某些配置中，资源井内包括井内的安装点，藉此所添加的器件能信号连接于形成在资源模块的介电层中的耦合器电路，并能耦合器到模块的金属凸缘上。可使用集成有凸缘的熔融粘结资源模块来提供用于多种微波电路应用的公共平台，以及提供通过允许高温器件安装处理和理想工作的热学控制而提供显著自由度的系统接口方法和安装方法。可通过将多种电路和电路元件添加到资源模块中而定制这种公共平台。这些电路元件可以包括微波电路、晶体管、变容二极管、PIN二极管和肖特基二极管。
在一种配置中，该耦合组件包括以层叠形式熔融地粘合在一起的多个复合基板层和凸缘层。把该基板层被设置在凸缘层的顶部并包括连接于信号输入和信号输出的内嵌的信号处理电路。在基板层一个区域上贯设有腔以露出信号连接端。这些信号连接端耦合于内嵌的信号处理电路并且在熔融粘合凸缘层和基板层后，它们能使电路元件添加到组件中，并且它们能将所添加的元件耦合到信号处理电路。
这种配置可包括下列特征的一个或多个。内嵌的信号处理电路(包括例如微波耦合器电路、阻抗匹配电路、DC隔离电路、偏置去耦合电路和/或RF负载端)包括：耦合于信号输入和耦合于露出在腔内的第一信号连接端的第一信号处理电路；以及耦合于信号输出和耦合于露出在腔内的第二信号连接端的第二信号处理电路。可配置该腔以接收所添加的电路元件(诸如微波电路、晶体管、变容二极管、PIN二极管、肖特基二极管)或其它电路元件。在腔内还可有露出的导电端，这些导电端耦合于组件的外表面上的导电端以提供添加到腔体的电路元件和外部信号源之间的信号连接。
这些配置还可包括下列特征中的一个或多个。腔内可露出将所添加的电路元件耦合(即电气耦合或热耦合)到凸缘层的凸缘层顶表面。凸缘层可由基本同质的金属内核形成。可将电镀金属(例如镍、金或其它防止金属内核氧化的金属)施加到凸缘层的表面。能在采用经由电镀通孔在基板层之间形成互连。
耦合组件的制造包括对基板层进行钻孔以产生多个通路，以及在基板层上形成切口。对这些切口如此定位以致当基板层在凸缘层顶部熔化成层叠的配置时，切口形成贯通基板层的腔，该腔露出凸缘层的顶表面。在熔融粘结之前，使基板层的表面金属化以形成内嵌的信号处理电路元件、信号输入和输出端、腔内露出的信号连接端、以及当多个复合基板层以层叠形式定位时，将前述结构互连的导电通孔。可在熔融连接后将切口形成在最顶上的基板层内，而其它基板层中的切口可在熔融连接前形成。
下面将结合附图和说明书对本发明的一个或多个配置的细节进行阐述。从说明书、附图和权利要求书看，本发明的其它特征、目的和优点将变得更明显。
附图说明
图1示出组合的资源模块的俯视图、侧视图和仰视图。
图2是表示能够包括在图1资源模块的配置中的信号处理电路元件的方框图；
图3是表示能够包含在图1的资源模块的另一配置中的信号处理电路元件的方框图；
图4-图6表示实现图2的信号处理电路的三个介电基板层的顶部金属层和底部金属层；
图7表示金属凸缘层的俯视图和仰视图；
图8表示面板阵列；
图9-图12表示不同类型的条状线；
图13表示条形线(slab line)传输线；
图14表示耦合器资源模块的另一实施例；
图15表示图14的耦合器资源模块的俯视图、侧视图和仰视图；
图16-图18示出实现图14的信号处理电路的三个介电基板的顶部金属层和底部金属层；
图19示出金属凸缘层的俯视图和仰视图。
具体实施方式
本文中将公开一种“资源模块”，图1中示出该模块的俯视图、侧视图和仰视图。如侧视图所示，并且如图4-7中更详细地示出的那样，资源模块100可由一堆粘合的基板层和金属凸缘层表示。基板层较为有利地由聚四氟乙烯(PTEE)、玻璃和陶瓷形成。每个基板层在一侧或两侧上包括电路。该电路包括例如微波定向耦合器、3dB正交耦合器、阻抗匹配网络、DC隔离、偏置去耦合以及RF负载端。凸缘层提供资源的安装并改善热学特性。
图2和图3是资源模块的不同配置的方框图。图2的方框图示出图4-6的基板层中形成的电路200。对于为12.5欧姆的情况，给出该电路如何工作的一个例子，尽管其它阻抗值的电路也能产生同样的操作。所示出的例子是3dB耦合器构成情况，然而也可由具有其它耦合值的耦合器的其它网络。在整个公开所使用的附图中，相同标号的部分表示相同结构(不管是在图2、3的方框图中，还是在图4-图7的介电层和凸缘层中)。当输入15和输出16处的阻抗与添加到资源井17的器件的阻抗不同时，则使用表示在图2的方框图中的电路。特别地，电路200用于一种配置，其中输入和输出阻抗为50欧姆并且模块能将12.5欧姆的器件安装到资源井17中。图3的方框图中的电路用于一种配置，其中输入、输出和所添加的资源阻抗相同。图3所示的电路部件与图2中的电路部件基本相同，除了图3的方框图缺少图2中的变换器部分1、14。对于配置300的基板层是从图2的电路200中的基板层中得出的。
电路200在端子15接收RF输入信号。通过变换器1，输入信号从50欧姆变至12.5欧姆，输出信号22随后被第一耦合器2分割。所产生的两路信号24、25随后被分别馈送至单独的耦合器4、5。耦合器4、5执行DC隔离功能。现在在资源井端18、19处可分别获得两个RF信号26、27。端子18、19处的信号被连接于诸如晶体管、变容二极管、PIN二极管和肖特基二极管等的器件，可在形成模块100后，将这些器件添加到资源井17中。在资源井17中可出现额外的信号端，用于例如对外部信号源的接地连接或连接。此外，其它成块元件(诸如电阻器、电容器和电感)可置于资源井17中。在资源井7中的器件处理RF信号后，把RF信号输出到端子20、21并由电路8-14处理。电路8-14实现对电路1-7的补充功能。即，端子20-21上的信号在输入33、34被提供给耦合器10、11和四分之一波条状线8、9。耦合器10、11用来隔离来自输入信号33、34的DC偏置。随后再次通过输出耦合器14将耦合器输出信号31、32结合，并把来自耦合器12的输出30提供给阻抗变换器14，它于信号点16处将输入信号30从12.5欧姆的阻抗变换成50欧姆的输出阻抗。
用于资源模块17的器件可能需要DC偏置以工作。通过DC隔离4、5、10、11在器件区17中包含该DC偏置。DC偏置28-29、36-37通过偏置去耦合线(即四分之一波条状线6-9)连接于器件区17，该偏置去耦合线对器件区17中的RF信号表现为开路。RF负载端3、13分别于信号点23、35连接于耦合器2、12，并提供经匹配的阻抗给耦合器的隔离端口。端子3、13的阻抗与耦合器阻抗匹配。
微波定向耦合器和3dB正交耦合器电路的设计的基本设计原理对本领域内技术人员而言是公知的，并在诸如论文“Shielded Coupled-StripTransmission Line”、S.B.Cohn、IEEE Trans.MTTS、MTT-3卷、第5期、29-39页、1955年10月，“Characteristic Impedances of Broadside-Coupled Strip Transmission Lines”、S.B.Cohn、IRE Trans.MTT-S、MTT-8卷、第6期、633-637页、1960年9月以及“Impedances of OffsetParallel-Coupled Strip Transmission Lines”、J.P.Shelton、Jr.、IEEE Trans.MTT-S、MTT-14卷、第1期、7-15页、1966年1月。定向耦合器一般被实现为边缘耦合的(edged-coupled)条状线(图10)或偏移耦合的条状线(图11、图12)，而正交耦合器一般被配置成偏移耦合条状线(图12)或全面耦合条状线(图9)。这些公开物的教义表示可将总结了这些理论的条状线耦合器集成在具有一体化凸缘的资源模块中。
可通过使用与厚金属凸缘粘结在一起的三个介电基板层而实现包括图2的电路的资源模块。这些基板层可由现代复合介电材料(包含PTFE、玻璃和陶瓷)形成。这些材料具有在很宽的温度范围下稳定的电气和机械特性，并具有改善微波频带性能的低损耗特性。热膨胀系数值接近铜则允许形成可靠的金属化孔和狭缝。使用这些金属化特征将导电层连接于层叠的带状线结构以及形成独立的接地面。接地狭缝可形成为数学近似于贯穿介电层的信号孔以形成条形传输线，该条形传输线对于Z方向上的传播保持受控的阻抗(即通过层叠的介电层结构从顶部到底部)。
图4-图6示出形成模块100的三个基板层400、500、600的俯视图、侧视图和仰视图。通过将由第一页侧视图形成的水平矩形折叠，俯视图与仰视图匹配。基板400、500、600可由聚四氟乙烯、玻璃和陶瓷的组合物构成，它们具有2.1-20.0范围的相对介电常数(Er)和0.001-0.06英寸范围的厚度(h)。该基板以铜箔(典型为0.007英寸厚，但可以是0.0001-0.003英寸)金属化，并被腐蚀以形成电路。镀铜的通孔和狭缝(即加长的孔和开口)将一个基板层连接于另一个。狭缝的例子包括狭缝401；通孔的例子包括孔402(图中所示的其它狭缝和孔未给予标号)。每层组件的细节如图4-7所示。这些模块被制造成阵列面板，如图8所示。
公开物中所描述的资源模块是根据美国第6099677(’677专利)号专利和第6395374号(’374专利)号专利所公开的工序制造而成的，这些内容援引于此作为参考。层400、500、600和厚金属凸缘700(图7)用熔融工序直接粘合在一起，它采用特殊温度和压力曲线以改变材料状态并形成同质的电介质，同时使电介质永久地附着于厚金属凸缘。将厚金属凸缘直接熔融地粘结于介电层为系统安装提供一种机械安装接口。藉由凸缘中的安装孔701将多层资源模块直接用螺栓固定到系统组件中。由于熔融粘结工序发生在350℃-400℃的温度之间，资源模块能轻易地承受因为将后处理组件安装在资源井17中的组件温度升高。这些后处理组件温度包括由使用焊料(Sn63、Sn96、Au/Si公晶体)、环氧树脂(填银环氧树脂、绝缘环氧树脂)和粘合剂(填银玻璃。填银氰酸盐酯)安装器件所引起的温度。
将厚金属凸缘700直接熔融粘结于介电层(特别是粘结于底层600)提供一种集成的散热装置，用于所散失的RF、DC功率散热的热控制。层400、500、600中的切口区475、575、675允许将器件直接安装到凸缘或安装到具有将热传导给凸缘的热学通路的介电层表面。在一些配置中，切口区475、575、675逐渐变小(从顶表面到底表面)以在不同介电层上露出不同的安装区。可将经腐蚀的金属膜电阻器和经印刷的厚膜电阻器包括在电路层中，同时也可将电阻器元件安装在资源井17中。所有这些电阻器(典型地配置成RF负载端)可得益于散热装置凸缘的安装，使它们能在更高的功率级下工作。
下面的步骤根据’677专利和’374专利中所公开的工序，对资源模块100的结构进行了概括。应该理解，各基板400-600和凸缘700被制造成为面板(即面板800)的一部分，它一般包括多个相同的基板部分(尽管在某些情况下，比如只需制造少量器件，可将面板制成具有多个不同基板的形式以形成不同配置的资源模块)。
下面将对资源模块的一种配置的结构进行说明。按照下面的方法制造凸缘板层和各基板层。
凸缘板的制造
1.各凸缘板700是通过选择地将铜面板镀以镍和金而形成的。
2.可在凸缘板700上贯通地钻出安装孔723以及狭缝以及对准销孔。当把完整的模块通过螺钉安装于另一表面时，包括安装孔723。
3.整个底表面710上可以镀以镍/金，而顶表面720可以是在整个顶表面上镀以镍/金，或在某些场合下，仅限于表面720的周缘724周围区域和包围安装孔723和狭缝的区域722内镀以镍/金。
4.可在资源井区域721内选择地镀以金。选择的镀金区域721为区域721提供改善的抗腐蚀性，并有助于保证凸缘板720和添加到资源井17的器件之间的良好电气连接。可使用光刻工序以限定所选的镀金区域。
基板层的制造
1.在基板层(400、500、600)中钻出狭缝和通孔。或者，通过钻孔形成贯通基板层的狭缝和通孔，然后在镀铜之前，对露出在孔和狭缝中的基板层进行等离子腐蚀。
2.首先使用无电镀铜晶籽层、然后使用电泳铜电镀将基板层(特别为孔和狭槽)镀以铜，铜层较为有利地具有0.0005-0.0010英寸的厚度。
3.随后在各层的两侧以光刻胶层叠基板层。用照相掩使光刻胶曝光在外，并随后显影以曝光基板层的选择区域。在暴露和显影光刻胶后，光刻胶仍然保护用来形成结构1-14和互连线路(例如15-37)的铜层。经电镀的铜随后从未受到光刻胶保护的基板层区域中被腐蚀去。
4.随后通过进一步腐蚀电阻器3、13区域内的铜而形成电阻器3和13，；露出铜层下的镍磷酸盐薄膜。这样，再次将光刻胶施加于基板层上。使用照相掩模，光刻胶被曝光并被显影以露出区域3、13中的铜，同时其它区域中的铜仍然受到光刻胶的保护。随后腐蚀区域3、13中露出的铜以界定电阻器。光刻胶随后被剥离。
5.随后为输入和输出接触连接、资源井接触连接和顶表面连接而进行选择地镀金。为此，再次将光刻胶施加于所有基板层的两侧，光刻胶使用照相掩模曝光和显影。基板随后被镀以镍和金。在电镀后，剩下的光刻胶被剥离。
6.然后研磨贯通所有基板的狭缝。在研磨后，通过酒精漂洗洗净板，并浸入热(70℃)蒸馏水中并在149℃下真空烘干1小时。
7.最后的组装步骤包括使用’374和’677专利中所述熔融工序粘结介电层。这种粘结可在250PSI压力和375℃温度下进行。然后在模块组件中研磨出狭缝，敞开所形成的腔(即腔17)。即，可在熔融焊接后形成顶层400中的腔开口475。各模块可通过机械加工而去除面板化。
如果不通过电磁建模和分析的方法进行补偿，则用于形成基板层之间互连和基板侧之间互连的通孔会表现出性能上的劣化。一般来说，可将建立这些通孔建模成垂直条形线传输线(图13)。为了在Z平面内提供受控的阻抗互连，可遵循“Microwave Transmission Line Impedance Data”，M.A.R Gunston，63-82页、Van Nostrand Reinhold公司、1971年的教义。本文中所公开的范例性耦合器组件包括宽带的宽定向耦合器和宽带宽的正交耦合器。宽带宽定向耦合器一般与其它方案结合使用，例如由“GeneralSynthesis Of Asymetric Multi-Element Coupled-Transmission-LineDirectional Couplers”，R.Levy.IEEE Trans.MTT-S、MTT-11卷、第4期、226-237页、1963年7月以及“Tables for Asymetric Multi-ElementCoupled-Transmission-Line Directional Couplers”，R.Levy.IEEETrans.MTT-S、MTT-12卷、第3期、275-279页、1964年5月中所公开的内容。另一方面，宽带宽正交耦合器可结合例如“Theory And Tables OfOptimum Symetrical TEM-Mode Coupled-Transmission-Line DirectionalCouplers”、E.G.Cristal和L.Young、IEEE Trans.MTT-S、MTT-13卷、第5期、544-558页、1965年9月中所给出的表格。另一种选择是遵循“FourPort Networks Synthesized From Interconnection of Coupled AndUncoupled Sections Of Line Lengths”、Joseph D.Cappucci、提交于1973年9月25日的#3761843美国专利所阐述的教义。3761843专利公开了如何将来自一组耦合/未耦合的条状线的宽带宽耦合器合成在一起。在这种情况下，将一组未经耦合的互连与一组耦合的部分结合以形成超宽带的正交耦合器。此外，在“The Design And Construction of Broadband，HighDirectivity，90-Degree Couplers Using Nonuniform Line Techniques”、C.P.Tresselt，IEEE Trans.MTT-S、MTT-14卷、第12期、647-656页、1966年12月以及“The Design And Computed Performance Of Three Classesof Equal-Ripple Nonuniform Line Couplers”、C.P.Tresselt，IEEETrans.MTT-S、MTT-17卷、第4期、218-230页、1969年4月中定义的非均一耦合结构可以是层叠的或垂直地前后连接的，从而提供非常宽带的性能，其特征为高通频率响应。
已对本发明的多个实施例进行了阐述。不过，要理解在不脱离本发明的精神和范围的前提下能作出多种修正。图14-图19示出其它实施例。这些图包括电路方框图(图14)，完整模块的俯视图、侧视图和仰视图(图15)，三个基板层的金属化的俯视图和仰视图(图16-图18)以及其它实施例的凸缘层19。图14的另一实施例包括位于电路1400输入侧的第二资源井40。
图14所示的电路包括电路部件和接头9-14、16、17、20-21、30-37，它们基本与图2中的相同。实施例1400还包括经修正的输入级50-66和第二资源井40。输入级于输入50处接收RF信号。通过变换器51将该信号从50欧姆转换成12.5欧姆，而输出信号在资源井40处被提供给触点52。可将其它器件(例如二极管、电阻器、晶体管或简单的桥接电路)耦合在资源井40的端子52、64之间。由资源井40中的任何器件转换得到的信号52被提供给端子64，并从那里提供至DC隔离耦合器59并送至信号耦合器61。信号耦合器61的输出62-63被提供给资源井17中的触点65-66。可以通过顶层表面触点36-37、54、80-87提供DC偏置。同样，可在连接于四分之一波条状线53的输入54处、连接于四分之一波条状线8的输入36处以及连接于四分之一波条状线9的输入37处提供DC偏置。可根据图2配置中所描述的工序，对基板层1600、1700、1800和凸缘板1900进行制造和粘结。基板层1600、1700、1800和凸缘板1900的其它特征遵循关于层400、500、600和凸缘板700而给出的描述。
因此，其它实施例落在下面权利要求书的范围内。

Claims (21)

1.一种耦合组件，包括：
以层叠布局熔融粘结在一起的凸缘层和多个复合基板层，其中所述基板层位于凸缘层上方，而所述基板层包括内嵌的信号处理电路；
各自耦合于内嵌的信号处理电路的信号输入和信号输出；以及
贯穿于多个基板层的区域形成的腔，所述腔将耦合于信号处理电路的信号连接端暴露在外以在熔融粘结凸缘和基板层后将电路部件添加到所述组件中，并能将所添加的电路部件耦合于所述信号处理电路。
2.如权利要求1所述的组件，其特征在于，所述内嵌的信号处理电路包括：
耦合于信号输入和露出于腔内的第一信号连接端的第一信号处理电路；以及
耦合于信号输出和露出于腔内的第二信号连接端的第二信号处理电路。
3.如权利要求2所述的组件，其特征在于，所述第一内嵌的信号处理电路和所述第二内嵌的信号处理电路包括微波耦合器电路。
4.如权利要求3所述的组件，其特征在于，所述第一和第二内嵌的信号处理电路还包括阻抗匹配电路。
5.如权利要求4所述的组件，其特征在于，所述第一内嵌的信号处理电路和所述第二内嵌的信号处理电路包括从由DC隔离电路、偏置去耦合电路和RF负载端所组成的组中选择的电路。
6.如权利要求3所述的组件，其特征在于，把所述组件配置成可添加额外的电路部件，所述电路部件从由微波电路、晶体管、变容二极管、PIN二极管和肖特基二极管所组成的组中选择。
7.如权利要求2所述的组件，其特征在于，还包括：暴露在腔内并耦合于组件外表面上的导电端的多个导电端，从而提供添加到腔中的电路部件和外部信号源之间的信号连接。
8.如权利要求2所述的组件，其特征在于，
所述腔露出可将添加的电路部件耦合到凸缘层的凸缘层的顶表面。
9.如权利要求1所述的组件，其特征在于，所述凸缘层包括基本上同质的金属内核，而所述复合基板层包括含氟聚合物复合材料。
10.如权利要求9所述的组件，其特征在于，将所添加的电路部件耦合于凸缘层包括所述电路部件和凸缘层之间的热耦合。
11.如权利要求10所述的组件，其特征在于，所述凸缘层由所述金属内核以及添加于所述金属内核表面的电镀金属组成。
12.如权利要求11所述的组件，其特征在于，所述添加于表面的电镀金属包括所述金属内核的抑制性氧化物。
13.如权利要求1所述的组件，其特征在于，所述多个基板层中的至少两层是通过电镀的通孔连接的。
14.一种耦合组件，包括：
凸缘层，所述凸缘层包括基本同质的金属内核和施加于所述金属内核表面并防止所述金属内核氧化的电镀金属；
多个熔融粘结的、包括含氟聚合物的复合基板层，所述复合基板层以层叠布局设置在凸缘层的顶部并包括第一和第二内嵌的信号处理电路；
耦合于第一内嵌的信号处理电路的信号输入；
耦合于第二内嵌的信号处理电路的信号输出；
贯穿于多个基板层的区域形成并露出凸缘层顶表面的腔，所述腔将耦合于第一信号处理电路的第一信号连接端以及耦合于第二信号处理电路的第二信号连接端暴露在外，所述腔允许在熔融粘结基板层后将电路部件添加到所述组件，并允许将所添加的部件耦合到所述信号处理电路和凸缘层。
15.如权利要求14所述的组件，其特征在于，所述第一内嵌的信号处理电路和所述第二内嵌的信号处理电路包括微波耦合器电路。
16.如权利要求15所述的组件，其特征在于，所述第一和第二内嵌的信号处理电路还包括阻抗匹配电路。
17.如权利要求14所述的组件，其特征在于，所述第一内嵌的信号处理电路和所述第二内嵌的信号处理电路包括从由DC隔离电路、偏置去耦合电路和RF负载端所组成的组中选择的电路。
18.如权利要求14所述的组件，其特征在于，还包括露出于腔内并耦合于组件外表面上的导电端的多个导电端，从而提供添加到腔的电路部件和外部信号源之间的信号连接。
19.如权利要求18所述的组件，其特征在于，所述第一信号处理电路是通过位于所述多个基板层的至少两层的表面上的金属化而形成的，而所述多个基板层的至少两层通过电镀的通孔彼此连接。
20.一种子组件，通过包括下列步骤的工序制造：
制造多个复合基板层；
制造包括基本同质的金属内核的凸缘层；
贯通于所述复合基板层钻孔以形成多个通路；
在多个复合基板层中的每一层形成切口，以使当复合基板层以层叠布局设置于凸缘层的顶部时，所述切口形成贯通于基板层的腔，所述腔将凸缘层顶表面暴露在外；
选择性地使所述复合基板层的表面金属化以形成：内嵌的信号处理电路部件；信号输入端；信号输出端；露出于所述所形成的腔内的第一和第二信号连接端；以及当多个复合基板层以层叠布局设置时，互连所述内嵌的信号处理电路部分、所述信号输入端、所述信号输出端、第一和第二信号连接端的导电通路；
将所述多个基板层彼此熔融粘结并将多个基板层熔融粘结到凸缘层，从而使多个基板层以层叠布局设置在凸缘层的顶部并形成具有贯穿多个基板层区域的腔的组件，藉此：
所述腔露出凸缘层的顶表面并露出耦合于内嵌的信号处理电路的信号连接端；以及
所述腔能在熔融粘结所述基板层后将电路部件添加至所述组件并能将所添加的电路部件耦合到信号处理电路和凸缘层。
21.如权利要求20所述的制造工序，其特征在于，在多个复合基板层的每个中形成切口包括：在熔融焊接所述多个基板层后，在多个基板层中的最上层内形成切口，以及在熔融焊接前，在多个层的最上层和所述凸缘层之间所夹的层内形成切口。
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Publication number Priority date Publication date Assignee Title
US7250827B2 (en) * 2003-09-10 2007-07-31 Merrimac Industries, Inc. Circuitry module
US8174338B2 (en) * 2008-06-02 2012-05-08 Innovative Power Products, Inc. Impedance transforming hybrid coupler
WO2011008981A1 (en) * 2009-07-15 2011-01-20 Regents Of The University Of Minnesota Implantable devices for treatment of sinusitis
US9888568B2 (en) 2012-02-08 2018-02-06 Crane Electronics, Inc. Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
US9420682B2 (en) * 2013-02-25 2016-08-16 Abl Ip Holding Llc Heterogeneous thermal interface
US9570222B2 (en) * 2013-05-28 2017-02-14 Tdk Corporation Vector inductor having multiple mutually coupled metalization layers providing high quality factor
US9230726B1 (en) 2015-02-20 2016-01-05 Crane Electronics, Inc. Transformer-based power converters with 3D printed microchannel heat sink
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US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5099309A (en) * 1990-04-30 1992-03-24 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5450046A (en) 1992-10-29 1995-09-12 Nec Corporation Composite microwave circuit module assembly and its connection structure
US5579207A (en) * 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking
JPH1013113A (ja) * 1996-06-21 1998-01-16 Oki Electric Ind Co Ltd 分布定数線路の結合方法及びマイクロ波回路
US6099677A (en) * 1998-02-13 2000-08-08 Merrimac Industries, Inc. Method of making microwave, multifunction modules using fluoropolymer composite substrates
US6320509B1 (en) * 1998-03-16 2001-11-20 Intermec Ip Corp. Radio frequency identification transponder having a high gain antenna configuration
US6165596A (en) * 1999-10-14 2000-12-26 Lucent Technologies, Inc. Multi-layer insulated metal substrate printed wiring board having improved thermal coupling of components
US6759743B2 (en) * 2000-09-11 2004-07-06 Xytrans, Inc. Thick film millimeter wave transceiver module
US6683512B2 (en) 2001-06-21 2004-01-27 Kyocera Corporation High frequency module having a laminate board with a plurality of dielectric layers
US6788171B2 (en) * 2002-03-05 2004-09-07 Xytrans, Inc. Millimeter wave (MMW) radio frequency transceiver module and method of forming same
US6707348B2 (en) * 2002-04-23 2004-03-16 Xytrans, Inc. Microstrip-to-waveguide power combiner for radio frequency power combining

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