CN1877815A - 用于制造半导体器件的方法 - Google Patents
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Abstract
提供了一种用于制造半导体器件的方法。该方法包括：通过进行蚀刻工艺在衬底上形成多个栅线；通过采用原子层沉积(ALD)方法在栅线和衬底上形成氧化物层；以及在氧化物层上依次形成缓冲氧化物层和氮化物层。
Description
技术领域
本发明涉及用于制造半导体器件的方法；尤其涉及用于制造能够防止接合塞(landing plug)接触的自对准接触(SAC)失效的半导体器件的方法。
背景技术
在用于制造80nm级以下的接合塞接触(LPC)模块的工艺中出现的最大局限之一是，栅间隔物并不在器件收缩时相应地在厚度上有所减小，对LPC开口和填缝工艺造成了很大负担。
当前，在80nm级器件中所需的单元间隔物氮化物层大多以从约280埃到约300埃范围的均匀厚度来形成。因此，实际上栅之间的间距持续减小。减小的间距可能：造成接触孔内增大的纵横比；在形成层间电介质(ILD)的同时由于填缝余量的减少而引起空隙；以及在通过自对准接触(SAC)工艺来蚀刻LPC氧化物层的同时引起将不被打开的接触。
另一方面，当半导体器件的大规模集成加速时，组成半导体器件的多种单元通常以堆叠的结构形成，于是引入接触塞(或垫)的概念。
为了形成这样的接触塞，引入和通常使用LPC技术。LPC技术引入开口，其具有大于底部区域的上部区域，以向较大的接触区域提供底部区域的最小部分，以及用于上部区域上的后续工艺的较大工艺余量。
而且，难以在这样的接触形成期间在具有高纵横比的结构之间蚀刻。这里引入SAC工艺，其中该SAC工艺通过利用两个不同材料即氧化物和氮化物之间的蚀刻选择性比来获得蚀刻轮廓(profile)。
基于CF和CHF的气体被用于SAC工艺。这里，通过采用氮化物层来形成的蚀刻停止层和间隔物被需要用来防止对底部传导图案的损坏。
在SAC工艺期间，为了最小化蚀刻目标的厚度，在形成层间绝缘层之后，蚀刻停止层、间隔物和层间绝缘层通过平坦化工艺即化学机械抛光(CMP)工艺来移除直至栅硬掩模氮化物层的上部区域。
另一方面，在用于在SAC工艺中形成间隔物和SAC孔的蚀刻工艺期间，由于栅传导层与塞之间的短路而可能发生SAC失效，其中该短路通常由栅线的栅硬掩模氮化物层中的蚀刻损耗所造成。
具体而言，当在动态随机存取存储器(DRAM)中采用凹栅以改进刷新特性时，硅化物层可能由于有源区域与场区域之间的高度差而具有不同的应力级。因此，硅化物层的侧壁上经常发生过度氧化，造成了SAC失效。
图1A至1B是图示了用于制造半导体器件的传统方法的截面图。
如图1A所示，器件隔离区域12通过利用浅沟槽隔离(STI)工艺在衬底11中形成。而且，尽管未示出，栅氧化物层在衬底11的上方形成，然后多个栅线在栅氧化物层上形成。这里，栅线的蚀刻包括依次形成的多晶硅层13、硅化物层14、硬掩模氮化物层15、以及抗反射涂敷层16。这时，在涂敷光阻剂(尽管未示出)于硬掩模氮化物层15上之后，在通过曝光工艺和后续显影工艺来图案化硬掩模氮化物层15时，形成抗反射涂敷层16，便于容易的曝光工艺。这里，抗反射涂敷层16由氧氮化硅(silicon oxynitride)制成(SiON)。
随后，在形成栅线之后进行光氧化工艺。通过光氧化工艺，氧化物层17在多晶硅层13和硅化物层14的蚀刻和暴露区域上形成。
另一方面，由于硅化物层14在光氧化工艺期间的异常氧化，氧化物层17的过度生长“A”在栅线的侧壁上生成。
如图1B所示，在上面所得的衬底结构上进行离子注入工艺。接着，形成缓冲氧化物层18以防止来自氮化物的应力。然后，在缓冲氧化物层18上形成氮化物层19。这里，缓冲氧化物层18在炉内形成。
尽管后续工艺在这里未被图示，但是如果层间氧化物层在包括栅线的上述衬底结构的上方形成并且进行LPC工艺，则可能出现如下结果。按照图1B中的蚀刻工艺，层间氧化物层被移除，其为SAC阻挡层的氮化物层19在蚀刻LPC时被打开，由于该蚀刻工艺而造成氮化物层19的特定深度的损耗。此时，氮化物层19的过度生长“A”部分受到上述蚀刻工艺的过度损坏，且被完全打开以造成缓冲氧化物层18的损耗，因此造成多晶硅层13中的SAC失效。
如上所述，由于硅化物应力差，异常氧化(过度生长)可能在光氧化工艺之后发生，随后栅线可能在LPC蚀刻期间被暴露，导致SAC失效。
发明内容
因此，本发明的目的是提供用于制造能够防止接合塞接触(LPC)的自对准接触(SAC)失效的半导体器件的方法.
根据本发明的一方面，提供了用于制造半导体器件的方法，包括：通过进行蚀刻工艺在衬底上形成多个栅线；通过采用原子层沉积(ALD)方法在栅线和衬底上形成氧化物层；以及依次在氧化物层上形成缓冲氧化物层和氮化物层。
附图说明
关于与附图相结合的特定实施例的如下描述，本发明的上述和其它目的及特征将变得更好理解，在附图中：
图1A和1B是图示用于制造半导体器件的传统方法的截面图；以及
图2是图示根据本发明具体实施例用于制造半导体器件的方法的截面图。
具体实施方式
参考附图，将具体地描述根据本发明具体实施例用于制造半导体器件的方法。
图2是图示了根据本发明具体实施例用于制造半导体器件的方法的截面图。
如图2所示，器件隔离区域22通过利用浅沟槽隔离(STI)工艺在衬底21中形成。然后，栅氧化物层(未示出)、多晶硅层23、硅化物层24以及硬掩模氮化物层25在衬底21上依次形成。
随后，光阻层在硬掩模氮化物层25上形成，光阻图案(尽管未示出)是通过以曝光和显影工艺来图案化光阻层而形成的。然后，使用光阻图案作为蚀刻掩模来蚀刻硬掩模氮化物层25。这里，如图2所示，由氧氮化硅制成的抗反射涂敷(ARC)层26可在硬掩模氮化物层25上形成，便于光阻图案的简易曝光工艺。
而且，进行用于光阻图案的剥离(strip)工艺以及用于移除硬掩模氮化物层25的蚀刻后残余的清洁工艺。
而且，使用硬掩模氮化物层25作为蚀刻阻挡，蚀刻硅化物层24、多晶硅层23以及栅氧化物层。
然后，在栅线形成之后，氧化物层27在栅线和衬底21上形成。这里，进行氧化工艺，其方式为将硅化物层24内的氧气和硅(Si)种子之间的反应抑制至最小，以及在衬底21上仅生长必需的氧化物层27。
具体而言，通过采用在上述所得的衬底结构上使用氧气作为源气体的原子层沉积(ALD)方法，来重复进行形成氧化物层的工艺，氧化物层27以从约100埃到约200埃范围的均匀厚度，不仅形成于衬底21的顶部上成，而且形成于栅线的水平和垂直表面上。
为了形成氧化物层27，在从约80℃到约200℃范围的温度进行ALD方法，通过抑制硅化物层24内的氧气和硅种之间的反应来防止异常氧化。这里，氧化物层27是通过重复进行循环直至实现所需厚度为止来形成的。该循环包括：注入作为源气体的HCD，流量约为100sccm，约为1分钟到约2分钟；抽运作为净化气体的HCD约3分钟；注入作为反应气体的H2O，流量约为600sccm，约为2分钟；以及抽运作为净化气体的H2O，约为4分钟。
另一方面，在通过采用ALD方法形成的氧化物层27中可能存在一些杂质，因此，可进行使用臭氧等离子体的附加后续工艺来改进器件可靠性。这里，臭氧等离子体工艺的时间期间可根据氧化物层27的总厚度而变化，优选为随着氧化物层27的厚度增大而延长该时间期间。
随后，缓冲氧化物层和氮化物层在上面所得的衬底结构上方形成，尽管未示出。此外，层间绝缘层在上面所得的包括栅线的衬底结构上方形成，然后进行LPC蚀刻。因此，氮化物层起到蚀刻阻挡物的作用，自对准接触(SAC)可在没有栅线损耗的情况下形成。
根据本发明的具体实施例，上述氧化工艺支持传统光氧化工艺的目的，同时抑制硅化物层内存在的硅种反应，以防止由应力引起的硅化物氧化。结果，硅化物层的侧壁上的过度氧化并未发生，在LPC掩模和蚀刻工艺期间防止了SAC失效。
本申请包含与2005年6月7日向韩国专利局提交的韩国专利申请No.KR2005-0048474有关的主题内容，这里引入其全部内容作为参考。
尽管已经结合某些具体实施例描述了本发明，但是对于本领域的技术人员明显的是，在不脱离如所附权利要求中限定的本发明的精神和范围情况下，可进行各种变化和改型。
Claims (11)
1.一种用于制造半导体器件的方法，包括：
通过进行蚀刻工艺在衬底上形成多个栅线；
通过采用原子层沉积(ALD)方法在栅线和衬底上形成氧化物层；以及
在氧化物层上依次形成缓冲氧化物层和氮化物层。
2.权利要求1的方法，其中ALD方法通过重复进行循环来生长氧化物层，该循环包括：
注入作为源气体的HCD；
抽运作为净化气体的HCD；
注入作为反应气体的H2O；以及
抽运作为净化气体的H2O。
3.权利要求2的方法，其中作为源气体的HCD的注入是以约为100sccm的流量进行约1分钟到约2分钟。
4.权利要求2的方法，其中作为净化气体的HCD的抽运是进行约3分钟。
5.权利要求2的方法，其中作为反应气体的H2O的注入是以约600sccm的流量进行约2分钟。
6.权利要求2的方法，其中作为净化气体的H2O的抽运是进行约4分钟。
7.权利要求1的方法，其中ALD方法是在从约80℃到约200℃范围的温度进行。
8.权利要求1的方法，其中氧化物层在栅线和衬底上的形成进一步包括使用臭氧等离子体来移除氧化物层内的杂质的后续工艺。
9.权利要求4的方法，其中臭氧等离子体是根据氧化物层的厚度来实施不同范围的处理时间。
10.权利要求1的方法，其中栅线是由包括多晶硅层、硅化物层和硬掩模氮化物层的堆叠结构形成。
11.权利要求1的方法，其中氧化物层是以从约100埃到约200埃范围的厚度形成。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050048474 | 2005-06-07 | ||
| KR1020050048474A KR100648859B1 (ko) | 2005-06-07 | 2005-06-07 | 반도체 소자 제조 방법 |
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| CN1877815A true CN1877815A (zh) | 2006-12-13 |
| CN100481390C CN100481390C (zh) | 2009-04-22 |
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| US (1) | US7592268B2 (zh) |
| KR (1) | KR100648859B1 (zh) |
| CN (1) | CN100481390C (zh) |
| TW (1) | TWI287258B (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111211088A (zh) * | 2018-11-21 | 2020-05-29 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
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| KR100720481B1 (ko) * | 2005-11-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
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| US9583337B2 (en) * | 2014-03-26 | 2017-02-28 | Ultratech, Inc. | Oxygen radical enhanced atomic-layer deposition using ozone plasma |
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-
2005
- 2005-06-07 KR KR1020050048474A patent/KR100648859B1/ko not_active IP Right Cessation
- 2005-12-06 US US11/295,902 patent/US7592268B2/en not_active Expired - Fee Related
- 2005-12-15 TW TW094144449A patent/TWI287258B/zh not_active IP Right Cessation
- 2005-12-27 CN CNB2005101351684A patent/CN100481390C/zh not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211088A (zh) * | 2018-11-21 | 2020-05-29 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
| CN111211088B (zh) * | 2018-11-21 | 2023-04-25 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100648859B1 (ko) | 2006-11-24 |
| US7592268B2 (en) | 2009-09-22 |
| TWI287258B (en) | 2007-09-21 |
| US20060276018A1 (en) | 2006-12-07 |
| CN100481390C (zh) | 2009-04-22 |
| TW200644096A (en) | 2006-12-16 |
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