CN1877803A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1877803A
CN1877803A CNA2006100912385A CN200610091238A CN1877803A CN 1877803 A CN1877803 A CN 1877803A CN A2006100912385 A CNA2006100912385 A CN A2006100912385A CN 200610091238 A CN200610091238 A CN 200610091238A CN 1877803 A CN1877803 A CN 1877803A
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Prior art keywords
wiring
basal substrate
eutectic alloy
electrode
semiconductor device
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CN100499054C (zh
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漆户达大
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

半导体装置的制造方法，包括下述步骤：在具有基底基板(12)和在基底基板(12)上形成的布线(14)的布线基板(10)上，搭载具有电极(25)的半导体芯片(20)，使布线(14)与电极(25)接触，进一步通过对它们进行加热/加压，形成共晶合金(30)。在此，按照共晶合金(30)的一部分进入到布线(14)与基底基板(12)之间的方式形成共晶合金(30)。从而，本发明能提供一种可靠性高的半导体装置及其制造方法。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
在布线基板上搭载半导体芯片，使布线和电极接触而电连接的方法是公知的。此时，通过布线和电极而形成共晶合金的方法是公知的。如果能够控制形成该共晶合金的区域，则能够制造可靠性高的半导体装置。
发明内容
本发明的目的在于提供一种可靠性高的半导体装置及其制造方法。
(1)有关本发明的半导体装置的制造方法，包括下述步骤：在具有基底基板和在所述基底基板上形成的布线的布线基板上，搭载具有电极的半导体芯片，对所述布线与所述电极进行加热/加压，而形成共晶合金，
按照所述共晶合金的一部分进入所述布线与所述基底基板之间的方式，形成所述共晶合金。根据本发明，能够在布线基板(基底基板)上的狭小区域内形成共晶合金。因此，根据共晶合金，能够防止相邻的两个布线的绝缘电阻下降。即通过该半导体装置的制造方法，可制造电可靠性高的半导体装置。
(2)在该半导体装置的制造方法中，
也可在所述布线基板上搭载所述半导体芯片的工序中，从所述基底基板剥离所述布线的一部分，形成剥离部，
按照使所述共晶合金进入所述剥离部和所述基底基板之间的方式形成所述共晶合金。
(3)在该半导体装置的制造方法中，
也可避开在所述布线与所述基底基板之间与所述电极重叠的区域而形成所述共晶合金。
(4)有关本发明的半导体装置，包括：布线基板，其具有基底基板和形成在所述基底基板上的布线；半导体芯片，其具有电极，按照所述电极与所述布线相对的方式搭载在所述布线基板上；和共晶合金，其按照与所述电极接触的方式形成，
所述共晶合金的一部分配置在所述布线与所述基底基板之间。由此，能够使布线中的与基底基板相对的面与共晶合金接触。因此，能够扩大共晶合金与布线之间的接触面积。并且，共晶合金按照与电极接触的方式形成。因此，根据本发明，能够使布线与电极稳定地电连接。即根据本发明，能够提供电连接可靠性高的半导体装置。
(5)在该半导体装置中，
所述共晶合金，也可按照避开在所述布线与所述基底基板之间与所述电极重叠的区域而形成。
附图说明
图1是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图2是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图3(A)及图3(B)是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图4(A)及图4(C)是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图5是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图6是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图7是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
图8是用于对有关适用本发明的实施方式的半导体装置进行说明的图。
图9是用于对有关适用本发明的实施方式的变形例的半导体装置进行说明的图。
图中：10-布线基板；12-基底基板；14-布线；15-剥离部；16-芯层；18-电镀层；20-半导体芯片；21-集成电路；25-电极；30-共晶合金；40-密封树脂。
具体实施方式
下面，参照附图对适用本发明的实施方式进行说明。但是，本发明并不限于以下的实施方式。
图1～图7是用于对有关适用本发明的实施方式的半导体装置的制造方法进行说明的图。
有关本实施方式的半导体装置的制造方法，也可包括准备布线基板10的步骤。以下，利用图1以及图2，对布线基板10的结构进行说明。另外，图1是布线基板10的俯视图。图2是图1的II-II线剖面的一部分放大图。
布线基板10，具有基底基板12。基底基板12的材料或结构并不特别限定，也可利用已公知的任一个基板。基底基板12，也可是挠性基板，也可是刚性基板。或者，基底基板12也可是带状基板。基底基板12也可是层叠型的基板，或者也可是单层的基板。此外，并不特别限定基底基板12的外形。并且，对于基底基板12的材料也不特别限定。基底基板12，可由有机系列或无机系列的任一种材料形成，也可采用它们的复合结构。基底基板12，例如可以是树脂基板。作为基底基板12，可使用例如由聚乙烯对苯二酸酯(PET)构成的基板或薄膜。或者，作为基底基板12也可使用由聚酰亚胺树脂构成的挠性基板。也可使用在FPC(Flexible PrintedCircuit)或TAB(Tape Automated Bonding)技术中使用的带子(tape)作为挠性基板。此外，作为由无机系列的材料形成的基底基板12，例如可举出陶瓷基板或玻璃基板。作为有机系列和无机系列的材料的复合结构，例如可举出玻璃环氧基板。作为基底基板12，也可利用不具有贯通孔(所谓的器件孔)的基板。但是，基底基板12，也可是具有图中未示出的贯通孔(所谓的开口(device hole))的基板。
布线基板10具有布线14。布线14，形成在基底基板12上。布线14，也可形成在基底基板12的表面上。布线14，也可直接设置在基底基板12的表面上。或者，布线14也可经由图中未示出的粘接剂粘贴到基底基板12上。布线14的结构并没有特别限定。布线14也可由多层构成。例如，布线14，也可以呈在芯层(core pattern)16上形成电镀层18的结构。芯层16也可由单一的金属层形成。此时，芯层16也可由铜形成。或者，芯层16也可由多个金属层形成。此时，芯层16也可呈层叠例如铜(Cu)、铬(Cr)、钛(Ti)、镍(Ni)、钛钨(Ti-W)中的任一个的结构。此外，电镀层18也可是锡层。
形成布线14(芯层16)的方法并没有特别限定，也可适用已知的任一个方法。例如，也可通过溅射法在基底基板12上形成第1金属层，通过电镀工序，在第1金属层上形成第2金属层，之后，通过对第1以及第2金属层形成图案，形成芯层16。通过上述方式，形成两层的芯层。或者，在基底基板12上粘贴铜箔，之后，通过对其形成图案，而可以形成芯层16。也可通过在这些芯层16上形成电镀层18，而形成布线14。或者，也可在基底基板12上形成第1金属层，在第1金属层上形成图案形成的抗焊剂，通过电镀工序在第1金属层上形成一层或者多层的金属图案，之后通过对第1金属层形成图案，而形成布线14。
布线基板10，也可具有通过基底基板12的内部的内部布线(未图示)。此外，布线基板10，也可具有未图示的树脂层。也可将树脂层称作抗焊剂。树脂层也可按照部分地覆盖布线14的方式形成。
有关本实施方式的半导体装置的制造方法，也可包括准备半导体芯片20的步骤(参照图3(A))。在半导体芯片20上也可形成集成电路21。集成电路21的结构并没有特别限定，但也可包括例如晶体管等的有源元件或、电阻、线圈、电容器等的无源元件。半导体芯片20具有电极25。电极25，也可与半导体芯片20的内部电连接。或者，也可将包括不与半导体芯片20的内部电连接的电极，并称作电极25。电极25的表面，例如也可由金形成。电极25，例如也可包括焊盘和在该焊盘上形成的凸块。此时，凸块也可是金凸块。或者，凸块也可呈在镍凸块上镀金的结构。还有，半导体芯片20，也可具有未图示的钝化膜。钝化膜例如也可由SiO2、SiN、聚酰亚胺树脂等形成。
有关本实施方式的半导体装置的制造方法，如图3(A)及图3(B)所示，包括下述步骤：在布线基板10上搭载半导体芯片20，使布线14与电极25接触，进一步通过对它们进行加热/加压，而形成共晶合金30。本工序，例如也可包括下述步骤：将半导体芯片20配置在布线基板10的上方，按照布线14与电极25重叠的方式对位(参照图3(A))，将半导体芯片20朝向布线基板10按压，将半导体芯片20搭载在布线基板10上(参照图3(B))。
在本工序中，将共晶合金30形成为，其一部分进入到基底基板12和布线14之间。也可在将半导体芯片20搭载在布线基板10上时，将布线14的一部分从基底基板12剥离，形成剥离部15，将共晶合金30形成为进入到基底基板12和布线14(剥离部15)之间。以下，参照图4(A)～图4(C)，对形成共晶合金30的过程的一例进行说明。另外，共晶合金30，例如也可是金与锡的共晶合金。
首先，如图4(A)所示，使半导体芯片20的电极25与布线基板10的布线14相接触。然后，对布线基板10和半导体芯片20进行按压，如图4(B)所示，将布线14的一部分从基底基板12剥离。也可将布线14中的从基底基板12剥离的部分称作剥离部15。也可通过将电极25从布线14向基底基板12推压，使布线基板10变形(使基底基板12塑性变形)，剥离一部分布线14。详细地来说，也可将电极25向布线基板10推压，使布线基板10变形，而在基底基板12和布线14之间的边界产生力，剥离基底基板12和布线14。特别在基底基板12为树脂基板时，基底基板12比布线14延伸得更长。因此，能够容易地从基底基板12剥离布线14的一部分。
然后，通过布线14和电极25形成共晶合金30。有关本实施方式的半导体装置的制造方法，如图4(C)所示，将共晶合金30形成为进入到布线14(剥离部15)和基底基板12之间。此时，也可避开在基底基板12和布线14之间与电极25重叠的区域而形成共晶合金30。在将电极25朝向布线基板10按压的状态下，形成共晶合金30，从而能够按照不进入到基底基板12与布线14之间的与电极25重叠的区域的方式，形成共晶合金30。
另外，在本工序中，也可按照不从基底基板12剥离布线14中的与电极25重叠的区域的方式，搭载半导体芯片20。例如，也通过电极25，将布线14向基底基板12按压，从而在与电极25重叠的区域，压接基底基板12和布线14，防止剥离。并且，如图4(C)以及图5所示，也可避开在布线14与基底基板12之间与电极25重叠的区域而形成共晶合金30。另外，图5是图4(C)的V-V线剖面图。
本工序也可在加热环境下进行。此外，本工序，也可一边对布线基板10以及半导体芯片20的至少一方施加超声波振动，一边进行。由此，能够高效地形成共晶合金30，同时容易使基底基板12和布线14剥离。从而，能够将共晶合金30形成为确切地进入到基底基板12与布线14之间。
有关本实施方式的半导体装置的制造方法，如图6所示，也可包括形成密封树脂40的步骤。由此，能够防止在半导体芯片20的边缘和布线14(剥离部15)以及共晶合金30之间产生电短路。而且，也可如图7所示，进一步通过检查工序或冲孔工序，形成半导体装置1。
如先前所述，有关本实施方式的半导体装置的制造方法，按照使一部分共晶合金30进入到基底基板12与布线14之间的方式形成共晶合金30。通过这样，能够减小基底臂膀12的表面中的形成共晶合金30的区域。即由于共晶合金30的一部分进入到基底基板12与布线14之间，因此能够减少出现在基底基板12的表面上的共晶合金30的量。因此，能够防止共晶体合金30沿基底基板12的表面大大地扩散。由此，能够在相邻的布线间，确保绝缘电阻。即能够防止因共晶合金30引起的电可靠性的下降。此外，由于共晶合金30进入到布线14与基底基板12之间，因此能够使共晶合金30，与布线14中的与基底基板12相对的面接触。因此，共晶合金30与布线14之间的接触面积变大，能够制造电可靠性高的半导体装置。
有关适用本发明的实施方式的半导体装置1包括布线基板10。布线基板10，具有基底基板12和形成在基底基板12上的布线14。半导体装置1包括半导体芯片20。半导体芯片20具有电极25，电极25按照与布线14相对的方式搭载在布线基板10上。布线基板10，包括按照与电极25接触的方式形成的共晶合金30。共晶合金30的一部分配置在基底基板12和布线14之间。由此，能够使共晶合金30，与布线14中的与基底基板相对的面接触。因此，能够使形成共晶合金30的区域不增大，而增大共晶合金30与布线14之间的接触面积。如果将共晶合金30与布线14之间的接触面积增大，则提高共晶合金30与布线14之间的电连接可靠性。而且，共晶合金30，按照与电极25接触的方式形成。因此，通过共晶合金30，可提高布线14与电极25之间的电连接可靠性。即通过半导体装置1，能够提供一种增大相邻的布线14间的绝缘电阻，且提高布线14与电极25之间的电连接可靠性高的半导体装置。此外，由于共晶合金30部分地进入到布线14与基底基板12之间，因此难以使共晶合金30从布线14脱离。
另外，如图4(C)及图5所示，在半导体装置1中，也可避开在布线14和基底基板12之间与电极25重叠的区域而形成共晶合金30。
还有，如图8所示，在半导体装置1中，布线14的、由与布线14延伸的方向垂直的平面切断的剖面，也可具有与基底基板12非接触的部分。此时，共晶合金30也可按照包围布线14的一部分(剥离部15的至少一部分)的方式形成。即布线14，也可具有由共晶合金30包围的部分。另外，图8是图4(C)的VIII-VIII线剖面图。
但是，有关本实施方式的半导体装置并不限于此。如图9所示，布线14，也可按照由与布线14延伸的方向垂直的平面切断的剖面不具有与基底基板12非接触的部分的方式形成。换句话说，如图9所示，布线14的底边的至少一部分与基底基板12接触的剖面也可呈连续的形状。例如，由与布线14延伸的方向垂直的平面切断的剖面的底部的中央部，通常也可与基底基板12接触。而且，共晶合金30，也可形成为只进入到布线14的剖面的底边的端部和基底基板之间。
另外，本发明并不限于上述实施方式，可有各种变形。例如，本发明包括与实施方式中说明的结构实质相同的结构(例如功能，方法以及结果相同的结构或者目的以及效果相同的结构)。此外，本发明包括置换实施方式中说明的结构的非实质的部分的结构。此外，本发明包括达到与实施方式中说明的结构相同的作用效果的结构或者达到同一目的的结构。此外，本发明包括向实施方式中已说明的结构中添加公知技术的结构。

Claims (5)

1、一种半导体装置的制造方法，其中，
包括下述步骤：在具有基底基板和在所述基底基板上形成的布线的布线基板上，搭载具有电极的半导体芯片，使所述布线与所述电极接触，进行加热/加压，形成共晶合金，
按照所述共晶合金的一部分进入到所述布线与所述基底基板之间的方式，形成所述共晶合金。
2、根据权利要求1所述的半导体装置的制造方法，其中，
在所述布线基板上搭载所述半导体芯片的工序中，从所述基底基板剥离所述布线的一部分，形成剥离部，
按照使所述共晶合金进入到所述剥离部和所述基底基板之间的方式形成所述共晶合金。
3、根据权利要求1或2所述的半导体装置的制造方法，其中，
避开在所述布线与所述基底基板之间与所述电极重叠的区域而形成所述共晶合金。
4、一种半导体装置，其中，
包括：
布线基板，其具有基底基板和形成在所述基底基板上的布线；
半导体芯片，其具有电极，按照所述电极与所述布线相对的方式被搭载在所述布线基板上；和
共晶合金，其按照与所述电极接触的方式形成，
所述共晶合金，让其一部分配置在所述布线与所述基底基板之间而形成。
5、根据权利要求4所述的半导体装置，其中，
所述共晶合金，避开在所述布线与所述基底基板之间与所述电极重叠的区域而形成。
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CN108149292A (zh) * 2016-12-02 2018-06-12 臻鼎科技股份有限公司 铜箔基板及其制作方法

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JP3915546B2 (ja) 2002-02-26 2007-05-16 セイコーエプソン株式会社 Ｃｏｆ用テープ、その製造方法、半導体装置及びその製造方法
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CN104070294A (zh) * 2013-03-28 2014-10-01 Tdk株式会社 电子器件用的接合构造和电子器件
CN104070294B (zh) * 2013-03-28 2017-04-12 Tdk株式会社 电子器件用的接合构造和电子器件
CN108149292A (zh) * 2016-12-02 2018-06-12 臻鼎科技股份有限公司 铜箔基板及其制作方法

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