CN1870239A - 采用成像阻焊层的方法和电路结构 - Google Patents
采用成像阻焊层的方法和电路结构 Download PDFInfo
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- CN1870239A CN1870239A CNA200610066823XA CN200610066823A CN1870239A CN 1870239 A CN1870239 A CN 1870239A CN A200610066823X A CNA200610066823X A CN A200610066823XA CN 200610066823 A CN200610066823 A CN 200610066823A CN 1870239 A CN1870239 A CN 1870239A
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 52
- 230000005855 radiation Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 28
- 230000004907 flux Effects 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 17
- 239000000919 ceramic Substances 0.000 claims description 11
- 238000007650 screen-printing Methods 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 238000002386 leaching Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 5
- 230000000379 polymerizing effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 7
- 238000003466 welding Methods 0.000 description 6
- 230000008602 contraction Effects 0.000 description 3
- 208000034189 Sclerosis Diseases 0.000 description 2
- 238000010344 co-firing Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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Abstract
本发明公开了一种采用成像阻焊层的方法和电路结构。在一个实施例中,在电路结构上淀积可成像材料。然后使可成像材料曝光于辐射图案,从而使可成像材料的部分聚合。然后去除可成像材料的未聚合部分,以界定具有焊剂淀积区域的阻焊层。然后在焊剂淀积区域中淀积焊剂。本发明还公开了可以根据该方法产生的电路结构。
Description
技术领域
本发明涉及采用成像阻焊层(photo-imaged solder mask)的方法和电路结构。
背景技术
随着球栅阵列(BGA)技术的发展,在电路板上安装更密和更高性能的器件的压力越来越大。一种受欢迎的BGA封装件或器件是陶瓷BGA(CBGA)封装件,其中集成电路(IC)被安装在陶瓷电路板上,以利用陶瓷衬底所提供的优于传统塑料衬底的电和热方面的优点。
构造CBGA封装件的一个通常很关键的特征是小焊球的精确对准,所述小焊球作为封装件与其所安装于的电路板之间的互连。即,焊球与焊球所附接于的形成在封装件上的焊盘这两者的形状、位置和尺寸容差对于在封装件上产生精确界定和对准的球栅阵列常常是关键的。
大多数CBGA封装件是利用多层共烧陶瓷(MLCC)技术形成的,其中焊盘以其“未熟”(软)状态被淀积在陶瓷衬底上。随后,陶瓷衬底被烧制并硬化。然而,在烧制期间,对陶瓷衬底的收缩的控制是受限的,硬化后的陶瓷上焊盘的界定和对准可能与原来应用到“未熟”陶瓷上的焊盘图案不匹配。例如,参见图1和图2所示的烧制前后的焊盘图案,其中图2所示的图案示出了陶瓷衬底100的收缩所导致的焊盘(例如焊盘102、104、106)的偏斜。
用于在衬底上淀积焊盘的第二种工艺是在硬化后的衬底(陶瓷或其它材料)上进行丝网印刷(screen print)。此后,只有焊盘受到固化或烧制工艺的影响。然而,焊盘的相对位置准确度和尺寸控制受限于诸如丝网伸展(导致位置漂移)和丝网网孔干扰(导致焊盘形状不精确,或淀积后厚膜塌陷)之类的因素。例如,参见图3所示的焊盘图案,其中图1所示的焊盘图案未在衬底300上实现,这是焊盘(例如焊盘302、304、306)淀积期间的丝网伸展所导致的。
发明内容
在一个实施例中,一种方法包括:1)在电路结构上淀积可成像材料,2)使可成像材料曝光于辐射图案,从而使部分可成像材料聚合;3)去除可成像材料的未聚合部分,以界定出具有焊剂淀积区域的阻焊层;以及4)在焊剂淀积区域中淀积焊剂。
在另一实施例中,一种电路结构包括衬底,该衬底具有暴露在其表面上的一个或多个导体。成像阻焊层1)覆盖暴露出(一个或多个)导体的衬底表面的至少一部分,并且2)界定出至少一个焊剂淀积区域,所述焊剂淀积区域与所述暴露出的导体中的一个或多个导体相交。焊剂被淀积在(一个或多个)焊剂淀积区域中暴露出的导体上。
还公开了其它实施例。
附图说明
在附图中示出了本发明的说明性实施例,其中:
图1示出了其上淀积了焊盘图案的典型衬底的平面图;
图2示出了支撑衬底收缩后的图1的焊盘;
图3示出了淀积期间的丝网伸展所导致的图1的焊盘;
图4示出了采用成像阻焊层的典型方法;
图5A-5I示出了可以根据图4的方法构造的电路结构的各个阶段。
具体实施方式
图4示出了可用来在电路结构上形成焊盘的典型方法400。作为示例,所述电路结构可以是包括诸如多层共烧陶瓷(MLCC)衬底之类的陶瓷衬底的电路结构。
方法400包括:1)在电路结构上淀积(402)可成像材料;2)使可成像材料曝光(404)于辐射图案,从而使可成像材料的部分聚合;3)去除(406)可成像材料的未聚合部分,以界定具有焊剂淀积区域的阻焊层,以及随后4)在焊剂淀积区域中淀积(408)焊剂。
图5A-5I中示出了方法400的典型应用,这些附图示出了可根据方法400构造的电路结构500的各个阶段。
图5A示出的典型电路结构500包括衬底502。作为示例,衬底502被示出为在其中(例如通孔)或其上具有一个或多个导体,所述导体中的至少一部分位于(例如暴露于)衬底502的一个表面上。在某些情况下,导体504、506、508、510可以是形成在衬底502上的厚膜电路层512的一部分。作为示例,结构500的厚膜电路层512被示出为包括厚膜电阻器514,该电阻器例如是未修整的(untrimmed)厚膜电阻器。
在电路结构500上淀积可成像材料518之前,可以对结构500,或者至少是结构500的要淀积可成像材料的区域(例如表面)进行清洁。在一个实施例中,这是用氧气(O2)等离子体516来完成的。
现在参照图5B,可以利用丝网印刷工艺在电路结构500上淀积可成像材料518(例如通过细孔丝网520来淀积材料518)。或者,可以利用喷涂(spray coating)或帘式淋涂(curtain coating)工艺来淀积材料518。
淀积之后,可成像材料518可能看起来如图5C所示。虽然可能常常优选使材料518覆盖电路结构500的整个(或基本整个)表面,但也可以如此淀积材料518以致其仅覆盖电路结构500的部分。在一个实施例中,可成像材料518以液态形式淀积,然后在曝光于辐射之前被固化(例如通过空气干燥或加热)成固态形式。材料518的液化度可以根据其要应用到的电路结构而调节。优选地,材料518应当薄得足以渗入并涂覆形成在导体504-510、元件514和电路结构500的任何表面变化之间的更细小的腔。然而,材料518必须厚得足以使其能够淀积成所需厚度——该厚度应可被保持直到材料518被固化。
在可成像材料518被淀积之后,其随后可被曝光于辐射图案,从而使材料518的部分528聚合。参见图5D和图5E。使材料518曝光于辐射的一种方式是将紫外光522通过掩模元件524发送,所述掩模元件界定出辐射图案(例如通过掩模元件524中的孔)。使材料518曝光于辐射的其它方法在本领域中也是公知的。有时,可成像材料518的特性将会决定材料518需要曝光的辐射类型。
照射之后,去除材料518的未聚合部分530,以界定出具有焊剂淀积区域534的阻焊层532。参见图5F。材料518的未聚合部分530还可被去除以暴露未修整厚膜电阻器514的至少一部分。在去除了未聚合部分530之后,可以将阻焊层532固化(例如通过干燥或加热)。
如果阻焊层532暴露了厚膜电阻器514,则可以例如使用激光器536来根据需要修整电阻器。参见图5G。
最终,可在焊剂淀积区域534中淀积焊剂538(例如混有助焊剂的焊膏)以形成焊盘。参见图5H。然后可以将一个或多个焊球540、542、544或其它电路元件置于焊盘上,并且焊剂538可被回流(reflow)以使焊球540、542、544牢固地附接于电路结构500。参见图5I。然后可以清洗完成的组件以去除任何助焊剂残留。
方法400和电路结构500是有利的,这是因为它们使得焊盘可以比其它方法更精确地成形和定位。而且,用于界定阻焊层的方法不像使用丝网印刷工艺时可能发生的那样受机器磨损或变形的影响。淀积的焊盘也不受“未熟”陶瓷烧制等引起的收缩的影响。
方法400是基于减除技术(subtraction technology)的,其中材料是被去除而非被增加以形成焊盘形状。结果,阻焊层不受标准厚膜印刷操作中可能发生的焊膏塌陷或丝网网孔干扰的影响。因此,可以更接近理想情况地界定焊盘。
Claims (20)
1.一种方法,包括:
在电路结构上淀积可成像材料;
使所述可成像材料曝光于辐射图案,从而使所述可成像材料的部分聚合;
去除所述可成像材料的未聚合部分,以界定具有焊剂淀积区域的阻焊层;以及
在所述焊剂淀积区域中淀积焊剂。
2.如权利要求1所述的方法,其中所述可成像材料淀积在其上的所述电路结构包括陶瓷衬底。
3.如权利要求1所述的方法,其中所述可成像材料淀积在其上的所述电路结构是厚膜电路层。
4.如权利要求3所述的方法,其中所述厚膜电路层包括至少一个未修整厚膜电阻器。
5.如权利要求4所述的方法,其中所述可成像材料的未聚合部分还被去除以暴露出所述至少一个未修整厚膜电阻器的至少一部分。
6.如权利要求5所述的方法,还包括在去除所述可成像材料的未聚合部分之后和淀积所述焊剂之前,固化所述阻焊层的已聚合部分,并对已通过所述阻焊层露出的至少一个厚膜电阻器进行修整。
7.如权利要求1所述的方法,还包括在淀积所述可成像材料之前,使用氧气等离子体至少对电路结构的要在其上淀积所述可成像材料的区域进行清洁。
8.如权利要求1所述的方法,其中利用丝网印刷工艺来淀积所述可成像材料。
9.如权利要求1所述的方法,其中利用喷涂工艺来淀积所述可成像材料。
10.如权利要求1所述的方法,其中利用帘式淋涂工艺来淀积所述可成像材料。
11.如权利要求1所述的方法,其中以液态形式淀积所述可成像材料,然后在将所述可成像材料曝光于辐射之前将其固化成固态形式。
12.如权利要求1所述的方法,其中通过界定出所述辐射图案的掩模元件,使所述可成像材料曝光于所述辐射图案。
13.如权利要求1所述的方法,其中对所述可成像材料进行曝光的辐射是紫外光。
14.如权利要求1所述的方法,还包括在去除所述可成像材料的未聚合部分之后和淀积所述焊剂之前,固化所述阻焊层的已聚合部分。
15.如权利要求1所述的方法,还包括:
将焊球置于所述焊剂上;以及
对所述焊剂进行回流。
16.一种电路结构,包括:
衬底,该衬底具有暴露在其表面上的一个或多个导体;
成像阻焊层,该成像阻焊层覆盖暴露出导体的衬底表面的至少一部分,并且所述成像阻焊层界定出至少一个焊剂淀积区域,所述焊剂淀积区域与暴露出的导体中的一个或多个导体相交;以及
焊剂,其淀积在焊剂淀积区域中暴露出的导体上。
17.如权利要求16所述的电路结构,其中一个或多个焊球经由所述焊剂附接到所述焊剂淀积区域中暴露出的导体上。
18.如权利要求16所述的电路结构,其中所述衬底是陶瓷衬底。
19.如权利要求16所述的电路结构,其中暴露在衬底的表面上的导体是厚膜导体。
20.如权利要求16所述的电路结构,其中所述成像阻焊层暴露出所述衬底表面上的至少一个厚膜电阻器的至少一部分。
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US11/135,967 | 2005-05-24 | ||
US11/135,967 US7326636B2 (en) | 2005-05-24 | 2005-05-24 | Method and circuit structure employing a photo-imaged solder mask |
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JP (1) | JP2006332652A (zh) |
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Cited By (3)
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CN104425291A (zh) * | 2013-08-30 | 2015-03-18 | 吴勇军 | 微米级半导体器件的封装方法及形成的封装结构 |
CN107809854A (zh) * | 2013-06-14 | 2018-03-16 | 三菱制纸株式会社 | 布线基板的制造方法 |
WO2023003821A1 (en) * | 2021-07-20 | 2023-01-26 | Entegris, Inc. | Methods for applying a blanket polymer coating to a substrate |
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US20070111500A1 (en) * | 2005-11-01 | 2007-05-17 | Cowens Marvin W | Method and apparatus for attaching solder balls to substrate |
JP5201983B2 (ja) * | 2007-12-28 | 2013-06-05 | 富士通株式会社 | 電子部品 |
US9601517B2 (en) * | 2014-10-01 | 2017-03-21 | Apple Inc. | Hybrid pixel control circuits for light-emitting diode display |
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US4971895A (en) * | 1981-10-20 | 1990-11-20 | Sullivan Donald F | Double exposure method of photoprinting with liquid photopolymers |
US4582778A (en) * | 1983-10-25 | 1986-04-15 | Sullivan Donald F | Multi-function photopolymer for efficiently producing high resolution images on printed wiring boards, and the like |
US5587342A (en) * | 1995-04-03 | 1996-12-24 | Motorola, Inc. | Method of forming an electrical interconnect |
US6228678B1 (en) * | 1998-04-27 | 2001-05-08 | Fry's Metals, Inc. | Flip chip with integrated mask and underfill |
US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
US6780673B2 (en) * | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
JP2004140313A (ja) * | 2002-08-22 | 2004-05-13 | Jsr Corp | 二層積層膜を用いた電極パッド上へのバンプ形成方法 |
JP2005183904A (ja) * | 2003-12-22 | 2005-07-07 | Rohm & Haas Electronic Materials Llc | 電子部品にはんだ領域を形成する方法及びはんだ領域を有する電子部品 |
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2005
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- 2005-12-06 TW TW094142944A patent/TW200642557A/zh unknown
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2006
- 2006-02-02 DE DE102006004845A patent/DE102006004845A1/de not_active Withdrawn
- 2006-03-29 CN CNA200610066823XA patent/CN1870239A/zh active Pending
- 2006-05-19 JP JP2006139682A patent/JP2006332652A/ja not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107809854A (zh) * | 2013-06-14 | 2018-03-16 | 三菱制纸株式会社 | 布线基板的制造方法 |
CN104425291A (zh) * | 2013-08-30 | 2015-03-18 | 吴勇军 | 微米级半导体器件的封装方法及形成的封装结构 |
WO2023003821A1 (en) * | 2021-07-20 | 2023-01-26 | Entegris, Inc. | Methods for applying a blanket polymer coating to a substrate |
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TW200642557A (en) | 2006-12-01 |
US7326636B2 (en) | 2008-02-05 |
JP2006332652A (ja) | 2006-12-07 |
DE102006004845A1 (de) | 2006-12-07 |
US20060270079A1 (en) | 2006-11-30 |
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