CN1855431A - 制造半导体器件的方法 - Google Patents
制造半导体器件的方法 Download PDFInfo
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Abstract
一种用于制造包括双混合隔离层的半导体器件的方法，其中通过在刻蚀期间利用硬掩膜而不利用光刻胶作为图形，保护下层硅化物层免遭光刻胶去除剂的破坏。该硬掩膜防止硅化物层暴露于光刻胶去除剂，并且提供非常好的横向尺寸控制使得两个氮化物隔离层很好地对准。
Description
技术领域
本发明一般地涉及半导体制造，并且更具体地涉及在不将下层(underlying)硅化物层暴露于光刻胶去除剂的情况下形成双混合隔离层(dual-hybrid liner)。
背景技术
已知对场效应晶体管(FET)施加应力，会影响它们的性能。当沿纵向施加(即在电流流动的方向)时，在已知压应力会提高空穴迁移率(或p沟道FET(PFET)驱动电流)的同时，已知张应力会提高电子迁移率(或n沟道FET(NFET)驱动电流)。将这样的应力施加于FET的一种方法是利用具有固有加压的氮化硅阻挡隔离层。例如，具有张应力的氮化硅隔离层可以用于在NFET沟道中引起张力，而具有压应力的氮化硅层可以用于在PFET沟道中引起压力。但是，张应力可能使空穴迁移率下降，并因此降低PFET性能。同样地，压应力可能使电子迁移率下降，并因此使NFET性能变差。从而，需要一种双混合隔离层方案，以包括在相邻的NFET和PFET中所希望的应力。
在用于增强NFET/PFET器件的应力的双混合氮化硅隔离层的形成中，必须通过构图和刻蚀，去除两个FET区域之一中的第一淀积隔离层。在Shimizu等人的美国专利申请公开2004/0029323中，公开了一种用于形成类似结构的典型方法。在该公开中，形成了氮化硅膜13。此外，在该公开中，在氮化硅膜13上方形成了作为绝缘膜的氧化硅膜13A(图4)，例如P-TEOS或O3-TEOS。然后将氮化硅膜13和氧化硅膜13A暴露于光刻蚀技术，以从PFET(图4(b))上方去除它们。其次，淀积另一个氮化硅膜14(图4(c))作为绝缘膜，并且然后将层14暴露于光刻蚀技术以从NFET上方去除它。
Shimiz等人的方法的一个缺点在于，它需要将与PFET相邻的下层硅化物层12暴露于光刻胶去除剂，以便于从PFET区域完全地去除膜13(图4(b))。不幸的是，光刻胶去除剂典型地包括氧或臭氧，其会引起硅化物层12的氧化以及增加的电阻。例如，典型的硅化物层通常具有大约在6ohm/sq和20ohm/sq之间的电阻Rs。比较起来，轻微氧化的硅化物层会具有相应的大约在12ohm/sq和40ohm/sq之间的电阻Rs。当暴露对氧化敏感的硅化物时，会产生高得多的电阻或甚至开启失败。在超过90nm的技术中，其利用了超小栅极长度(例如，＜35nm)和扩散宽度(例如，＜100nm)，Rs的这种增加是不能接受的，因为它将影响器件的性能。除上述问题以外，硅化物层12暴露到光刻胶去除剂中，会导致硅化物层12中的开路。
考虑到前面所述，需要用于制造具有双混合隔离层的半导体器件的方法，其中要保护硅化物层免遭光刻胶去除剂的破坏。
发明内容
本发明包括用于制造包含双混合隔离层的半导体器件的方法，其中通过在刻蚀期间利用硬掩膜而不利用光刻胶作为图形，保护下层硅化物层免遭光刻胶去除剂的破坏。该硬掩膜防止了硅化物层暴露于光刻胶去除剂，并且提供了非常好的横向尺寸控制使得两个氮化物隔离层很好地对准。
本发明的第一方面针对一种制造半导体器件的方法，该半导体器件包括在PFET和NFET上方的双混合隔离层，该方法包括以下步骤：在PFET和NFET上方淀积拉伸的氮化硅层；在拉伸的氮化硅层上方淀积硬掩膜，该硬掩膜包括原硅酸四乙酯(TEOS)、等离子体增强化学汽相淀积(PECVD)的二氧化硅、碳掺杂的二氧化硅和碳化硅(SiC)中的一种；利用第一光刻胶掩膜，去除在PFET上方的硬掩膜，直至拉伸的氮化硅层；去除第一光刻胶掩膜；利用硬掩膜作为图形，刻蚀以去除在PFET上方的拉伸的氮化硅层；在PFET和NFET上方淀积压缩的氮化硅层；利用第二光刻胶掩膜，去除在NFET上方的压缩的氮化硅层；去除第二光刻胶掩膜；以及在PFET和NFET上方淀积层间电介质。
本发明的第二方面包括一种用于在PFET和NFET的晶体管沟道中引入应力的方法，该方法包括以下步骤：在PFET和NFET上方淀积第一氮化硅层；在第一氮化硅层上方淀积硬掩膜；去除在PFET上方的硬掩膜，直至第一氮化硅层；利用在NFET上方的硬掩膜作为图形，刻蚀在PFET上方的第一氮化硅层，直至与PFET相邻的硅化物层；以及在PFET上方形成第二氮化硅层。
本发明的第三方面涉及一种在双混合隔离层的形成期间用于防止与晶体管邻接的硅化物层暴露于光刻胶去除剂的方法，该方法包括以下步骤：在第一FET和第二FET上方淀积第一氮化硅层；在第一FET上方的第一氮化硅层上方形成硬掩膜；利用硬掩膜作为图形，刻蚀在第二FET上方的第一氮化硅层；以及在第二FET上方形成第二氮化硅层。
从以下对本发明的实施例的更具体描述，本发明的以上及其它特征将变得显而易见。
附图说明
参照下列附图，将详细描述本发明的实施例，其中相同的标记指示相同的元件，并且其中：
图1至图9表示根据本发明形成半导体器件的方法的一个实施例。
具体实施方式
参照附图，图1表示了用于制造包括双混合隔离层的半导体器件的方法的初始结构50。初始结构50包括p型场效应晶体管(PFET)52和n型场效应晶体管(NFET)54。PFET52和NFET54的每一个都包括具有硅化物帽58的栅极体56、二氧化硅(SiO2)间隔层60和氮化硅(Si3N4)间隔层62，它们形成于衬底64上方。浅槽隔离(STI)66隔开了FET52和54。在衬底64的上部区域中提供下层硅化物层68。应该认识到，本发明的教导不限于该初始结构。例如，虽然将衬底64作为块硅来说明，但还可以将它以绝缘体硅(SOI)的形式提供。
转到图2，本方法的第一步骤包括在PFET52和NFET54上方淀积第一氮化硅层100(下文中为“第一SiN层”)。在一个实施例中，第一SiN层100包括一种张力材料，即，具有固有张应力的材料。本实施例利用了氮化硅在退火时如何倾向于变为拉伸的优势，例如，甚至压缩的氮化硅材料在高温下退火时也会变得不易压缩或拉伸。在这点上，拉伸的氮化硅可以比压缩的氮化硅耐受更多的退火工序。因此，首先形成拉伸的氮化硅层是有利的。
同样如图2所示，第二步骤包括在拉伸的SiN层100上方淀积硬掩膜110。在一个实施例中，硬掩膜110包括氧化物，诸如原硅酸四乙酯(TEOS)(Si(OC2H5)4)、等离子体增强化学汽相淀积(PECVD)的二氧化硅、碳掺杂的二氧化硅或者碳化硅(SiC)。
图3至图4表示了下一步骤，利用第一光刻胶掩膜114，去除在PFET52上方的硬掩膜直至第一SiN层100(图3)，并且然后去除第一光刻胶掩膜114(图4)。光刻胶掩膜114覆盖NFET54，并且光刻胶掩膜114可以是任何常规的或者将来开发的光刻胶材料。在一个实施例中，利用氧基反应离子刻蚀116，去除硬掩膜110(图3)。但是，还可以使用其它刻蚀技术。这些步骤的结果是，在NFET54上方保留有硬掩膜110和第一SiN层100，而在PFET52上方只保留有第一SiN层100。但是下层硅化物层68并不暴露于光刻胶去除剂，因为它保持被第一SiN层100所覆盖。
接下来，如图5所示，利用NFET54上方的硬掩膜110作为图形，去除在PFET52上方的第一SiN层100。在一个实施例中，通过刻蚀120，去除第一SiN层100直至与PFET52相邻的下层硅化物层68。在刻蚀步骤期间，至少部分地消耗硬掩膜110。该步骤使得去除了PFET52上方的第一SiN层100，并且防止了在双混合隔离层的形成期间，与晶体管邻接的硅化物层68暴露于光刻胶去除剂。在这一阶段，还可以执行退火以去除在PFET52上刻蚀第一SiN层100期间，对硅化物层68的任何损伤，以减小硅化物的电阻。该退火还可以提高第一SiN层100中的张应力。在惰性环境中，该退火温度可以从400℃到1000℃，该惰性环境诸如氩气(Ar)、氮气(N2)或氢气(H2)或者这些环境的混合。
转到图6，下一步骤包括在PFET52和NFET54上方淀积第二氮化硅层130(下文中为“第二SiN层”)。与其中第一SiN层100是拉伸的上述优选实施例相比，第二SiN层包括压缩的氮化硅材料，即，将对下层结构施加压应力的材料。
图7至图8表示接下来的步骤，利用第二光刻胶掩膜134，去除在NFET54上方的第二SiN层130(图7)，并且然后去除第二光刻胶掩膜134(图8)。光刻胶掩膜134覆盖PFET52，并且光刻胶掩膜134可以是任何常规的或者将来开发的光刻胶材料。在一个实施例中，利用任何现在已知的或将来开发的氮化物刻蚀技术136，去除第二SiN层130(图7)。但是，还可以利用其它刻蚀技术。在该处理期间，使用硬掩膜110作为刻蚀停止层，以防止减薄第一SiN层100。这些步骤的结果是形成了双混合隔离层200，其包括在NFET54上方的硬掩膜110和第一SiN层100，以及在PFET52上方的第二SiN层130。双混合隔离层200将如本领域中已知的那样，在PFET52和NFET54的晶体管沟道中引起(induce)应力。下层硅化物层68并不暴露于光刻胶去除剂，因为在整个处理过程中它保持被覆盖。硬掩膜110还提供了一种用于控制每个氮化硅层100，130的横向尺寸的机制。
图9表示了随后的常规结束步骤的结果，尤其包括，在PFET52和NFET54上方淀积层间电介质140，例如高密度等离子体淀积的二氧化硅SiO2，并且形成对栅极(例如NFET54栅极)以及/或者对下层硅化物层68的金属触点142。
虽然已结合以上概述的具体实施例描述了本发明，但很明显，许多选择、修改和变更对于本领域技术人员将是显而易见的。从而，上述的本发明的实施例意在说明，而不是限制。在不偏离以下权利要求中所限定的本发明的精神和范围的情况下，可以进行各种改变。
Claims (20)
1.一种制造半导体器件的方法，所述半导体器件包括在PFET和NFET上方的双混合隔离层，所述方法包括以下步骤：
在所述PFET和所述NFET上方淀积拉伸的氮化硅层；
在所述拉伸的氮化硅层上方淀积硬掩膜，所述硬掩膜包括原硅酸四乙酯(TEOS)、等离子体增强化学汽相淀积(PECVD)的二氧化硅、碳掺杂的二氧化硅以及碳化硅(SiC)中的一种；
利用第一光刻胶掩膜，去除在所述PFET上方的所述硬掩膜，直至所述拉伸的氮化硅层；
去除所述第一光刻胶掩膜；
利用所述硬掩膜作为图形，刻蚀以去除在所述PFET上方的所述拉伸的氮化硅层；
在所述PFET和所述NFET上方淀积压缩的氮化硅层；
利用第二光刻胶掩膜，去除在所述NFET上方的所述压缩的氮化硅层；
去除所述第二光刻胶掩膜；以及
在所述PFET和所述NFET上方淀积层间电介质。
2.根据权利要求1的方法，其中在所述刻蚀步骤期间，至少部分地消耗所述硬掩膜。
3.根据权利要求1的方法，其中去除所述压缩的氮化硅层的步骤包括利用所述硬掩膜作为刻蚀停止层。
4.一种在PFET和NFET的晶体管沟道中引入应力的方法，所述方法包括以下步骤：
在所述PFET和所述NFET上方淀积第一氮化硅层；
在所述第一氮化硅层上方淀积硬掩膜；
去除在所述PFET上方的所述硬掩膜，直至所述第一氮化硅层；
利用在所述NFET上方的所述硬掩膜作为图形，刻蚀在所述PFET上方的所述第一氮化硅层，直至与所述PFET相邻的硅化物层；以及
在所述PFET上方形成第二氮化硅层。
5.根据权利要求4的方法，其中所述硬掩膜包括原硅酸四乙酯(TEOS)、等离子体增强化学汽相淀积(PECVD)的二氧化硅、碳掺杂的二氧化硅以及碳化硅(SiC)中的一种。
6.根据权利要求4的方法，其中所述第一氮化硅层包括一种拉伸的氮化硅材料，并且所述第二氮化硅层包括一种压缩的氮化硅材料。
7.根据权利要求4的方法，还包括在所述刻蚀步骤之后进行退火的步骤。
8.根据权利要求4的方法，其中在所述刻蚀步骤期间，至少部分地消耗所述硬掩膜。
9.根据权利要求4的方法，其中形成所述压缩的氮化硅层的步骤包括：
在所述PFET和所述NFET上方淀积压缩的氮化硅层；
利用光刻胶掩膜，去除在所述NFET上方的所述压缩的氮化硅层；以及
去除所述光刻胶掩膜。
10.根据权利要求9的方法，其中去除所述压缩的氮化硅层的步骤包括利用所述硬掩膜作为刻蚀停止层。
11.根据权利要求4所述的方法，还包括在所述PFET和所述NFET上方淀积层间电介质的步骤。
12.一种在双混合隔离层的形成期间用于防止与晶体管相邻的硅化物层暴露于光刻胶去除剂的方法，所述方法包括以下步骤：
在第一FET和第二FET上方淀积第一氮化硅层；
在所述第一FET上方的所述第一氮化硅层上方形成硬掩膜；
利用所述硬掩膜作为图形，以刻蚀在所述第二FET上方的所述第一氮化硅层；以及
在所述第二FET上方形成第二氮化硅层。
13.根据权利要求12的方法，其中所述硬掩膜包括原硅酸四乙酯(TEOS)、等离子体增强化学汽相淀积(PECVD)的二氧化硅、碳掺杂的二氧化硅以及碳化硅(SiC)中的一种。
14.根据权利要求12的方法，其中所述第一氮化硅层包括拉伸的氮化硅材料，所述第一FET包括NFET，所述第二氮化硅层包括压缩的氮化硅材料，并且所述第二FET包括PFET。
15.根据权利要求12的方法，还包括在所述刻蚀步骤之后进行退火的步骤。
16.根据权利要求12的方法，其中在所述刻蚀步骤期间，至少部分地消耗所述硬掩膜。
17.根据权利要求12的方法，其中形成所述第二氮化硅层的步骤包括：
在所述第二FET上方淀积压缩的氮化硅层；
利用光刻胶掩膜，去除在所述第二FET上方的所述压缩的氮化硅层；以及
去除所述光刻胶掩膜。
18.根据权利要求17的方法，其中所述去除步骤包括利用所述硬掩膜作为刻蚀停止层进行刻蚀。
19.根据权利要求12的方法，其中所述刻蚀步骤包括：
利用光刻胶掩膜，构图所述硬掩膜；
刻蚀以去除在所述第二FET上方的所述硬掩膜；以及
去除所述光刻胶掩膜。
20.根据权利要求12的方法，其中所述刻蚀步骤在所述第二FET的下层硅化物层上停止。
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| CN102097380A (zh) * | 2009-12-10 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | 互补型金属氧化物半导体结构的形成方法 |
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| CN101226338B (zh) * | 2007-01-17 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | 扫描曝光机校准度检测方法 |
| CN101894799B (zh) * | 2009-05-22 | 2012-12-12 | 中芯国际集成电路制造(北京)有限公司 | 提高nmos晶体管电子迁移率的方法 |
| CN102097380A (zh) * | 2009-12-10 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | 互补型金属氧化物半导体结构的形成方法 |
| CN102097380B (zh) * | 2009-12-10 | 2013-05-29 | 中芯国际集成电路制造(上海)有限公司 | 互补型金属氧化物半导体结构的形成方法 |
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