CN1842248B - 球栅阵列偏栅去耦的设备及方法 - Google Patents

球栅阵列偏栅去耦的设备及方法 Download PDF

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CN1842248B
CN1842248B CN2006100089612A CN200610008961A CN1842248B CN 1842248 B CN1842248 B CN 1842248B CN 2006100089612 A CN2006100089612 A CN 2006100089612A CN 200610008961 A CN200610008961 A CN 200610008961A CN 1842248 B CN1842248 B CN 1842248B
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A·L·尚
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Abstract

一种具有球栅阵列(BGA)连接盘图形的多层印刷线路板,其中该图形中的每个连接盘通过连接器连接到相应的过孔,一种改变选择的相邻过孔对和相应连接对之间的间隔以容纳去耦电容焊盘的方法,包括旋转、延伸和/或截短选择的相邻连接对并旋转其各自对应的过孔对以改变BGA连接盘图形中选择的相邻过孔对之间的间隔并将电容焊盘应用到选择的过孔对。在互为相反的方向上旋转、延伸和/或截短选择的相邻的过孔对和其相应的连接器。

Description

球栅阵列偏栅去耦的设备及方法
技术领域
本发明涉及电子电路板的设计。具体地,涉及用表面安装电容对BGA设备进行电去耦,所述表面安装电容安装在相对于BGA设备的电路板的另一面并且位于用来对BGA设备布置信号走线的过孔和触点栅格内。该布局是通过将去耦电容尽可能地靠近附属设备的电源和接地焊球(引线)放置的实际操作来促成的,以优化电去耦性能。根据不同的技术这种布局在本领域是公知的。然而,每种现有技术都涉及到增加成本、减少可靠性或增加BGA栅格内对信号走线的布线限制中一个或多个缺点。因此,本发明提供减轻以下要讨论的现有技术缺点的新的去耦技术。
背景技术
现有技术解决方案1
参考图1和图4A、4B和4C,为了形成通过其可以对线路布线的布线通道(即在共用过孔的行及相邻行之间较大的间隔),LSI逻辑电路在排成列的电源和接地连线上使用共用过孔。这并不是去耦解决方案;然而,2004年1月22日,该申请的代理人在美国专利局提交了序号为10/761,343、题为“Shared Via Decoupling for Area Arrays Components”的专利申请,该申请的解决方案使用了共用过孔的概念。图4说明了“共用过孔”去耦技术的例子。“共用过孔”解决方案的主要缺点是即使有交替的电源和接地行,也不可能总是共用过孔。例如,在一些情况下,两个电源焊球的复合瞬态电流可能超过过孔的限度,在这种情况下,这两个焊球不能共用过孔,因此对于这些焊球不能使用共用过孔去耦技术。
现有技术解决方案2
参考图2A和2B,对于1.00mm间距的BGA元件,一个目前通用的解决方案包括在0850电容焊盘图形上用于在连接盘中过孔(ViP,via inpad)的镀通孔(PTH,plated through hole)。该解决方案的缺点是芯片需要具有以非常特殊的方式配置的电源和接地焊球。这种情况的前提是,过孔不能减少且电容必须尽可能近地连接到电源和接地焊球。图2显示了为了将0805电容安装到1.00mm栅格的背面中,需要去耦的电源和接地焊球有必要通过信号或未使用的焊球来隔离。在一些应用中并不存在这种隔离,原因在于BAG器件的引出脚可能已经由诸如信号布线限制、瞬态电流限制等其它限制的支配。
现有技术解决方案3
参考图3A和3B,在近来的设计中通常采用的另一种解决方案使用改进的印刷线路板(PWB)技术。该解决方案使用盲孔的和局部复合(sub-composite)过孔的组合以允许在BGA元件的背面接入。在这种情况下,元件栅距、引脚设置和电容尺寸不需要指定且对许多组合都可以工作。结果,可以在BGA元件的背面上形成类似“停车场”的设置以使得能够安装到可用空间中的去耦电容数量最大化。该选择提供了设计的最高自由度但是导致了较高的电路板成本。
现有技术解决方案4
另一种技术被称为填充孔。在这种情况下,两个以足够间距分开的导通孔(导通板)用导电的或不导电的材料填充之后进行电镀处理以使每个都可作为用于表面安装的去耦电容的底部的连接焊盘(landing pad)。接着通过将电容焊接到连接焊盘,该电容电气并机械地连接到电路板。该技术的缺点是由于薄铜过孔、用于填充过孔的材料和在电路板的铜层之间使用的FR4材料的热膨胀的差异,过孔可能从电路板剥离。在具有有限的纯源化的现代工业中,该处理被认为是高风险的。除了这一可靠性的风险,该技术还增加了大约30%到40%的电路板成本。
按照上述现有技术的顺序,将以上现有技术解决方案的主要缺点概括为主要包括以下方面:
1.共用过孔去耦解决方案(现有技术1)的主要缺点在于,在例如瞬态电流太大无法共用过孔的一些应用中不能使用过孔。
2.在连接盘中过孔(ViP)的镀通孔(PTH)解决方案(现有技术2)的主要缺点也是在一些应用中不能使用,所述应用例如当电源、接地和信号焊球(引脚)不能在所需图形即电源-信号-接地中排列时。而且,对于在去耦电容下的信号引脚该技术没有检测通路并且在电路板的x射线检测期间PTH ViP会导致一些问题。
3.“停车场”解决方案(现有技术3)的主要缺点在于,由于该技术使用盲孔的和部分复合的过孔,采用高密度互连(HDI)使制造电路板的成本较高。
4.“填充孔”解决方案(现有技术4)的缺点是最终增加的填充孔从电路板剥离的可靠性方面的风险以及增加的电路板成本。
发明内容
本发明的基本特征是将电源和接地过孔的两个临近行或部分行的位置彼此移开,从而偏离标准栅距在行之间产生足够大的间隔以在两个对角相对的过孔之间安装去耦电容,每个过孔位于相应的相邻行中。
本发明旨在提供在电路板另一面的球栅阵列焊盘的常规间隔的栅格内提供具有去耦电容焊盘的电路板的方法和装置,所述电路板的另一面作为去耦电容焊盘侧。通过沿着平行于所述焊盘的对角相对的轴对两个焊盘中的一个或两个的位置进行线性移动来获得在关于球栅阵列互相呈对角相对的一对去耦电容焊盘之间安装去耦电容的足够空间,该对焊盘中的每一个直接位于所述阵列的相应的相邻行和列中并且电连接到通板过孔,所述通板过孔连接到所述球栅阵列焊盘中的一个。CAD工具可以用于执行根据本发明的方法。
本发明的特征在于多层印刷线路板上的球栅阵列(BGA)设备和其相关的连接盘图形,所述图形中的每个连接盘通过连接器(link connector)连接到相应的过孔,以及一种修改选择的相邻过孔之间和相应连接对之间间隔以容纳去耦电容焊盘的方法,该方法包括:旋转、延伸和/或截短所述选择的相邻连接对并旋转其各自对应的过孔对以修改BGA连接盘图形中选择的相邻过孔对之间的间隔并将电容焊盘应用到选择的过孔对。此外,在互为相反的方向上旋转、延伸和/或截短选择的相邻过孔对及其相应的连接器。
本发明的特征还在于这样一种印刷线路板,其过孔和连接器图形根据上述方法进行了修改。
本发明的目的是提供具有去耦电容焊盘的电路板的方法和装置,所述去耦电容焊盘位于球栅格阵列焊盘常规间隔的栅距内。
附图说明
考虑下列说明和附图本发明的上述和其它目的、优点和特征会更清楚,附图中:
图1(参考图4A、4B和4C)示意了产生布线通道的共用过孔,这里称为现有技术1;
图2A和2B示意了使用镀通孔ViP解决方案的电容,这里称为现有技术2;
图3A和3B说明了HDI“停车场”解决方案,这里称为现有技术3;
图4A、4B和4C进一步说明了图1所示的共用过孔解决方案;以及
图5是结合本发明的偏栅(off-grid)去耦技术的印刷电路板示意图。
具体实施方式
参考图5,多层的印刷线路板10在安装BGA设备的传统BGA栅格图形中,具有圆形的连接盘或焊盘5-10(在设备侧或上部),所述连接盘或焊盘5-10如虚线所述。在图5中部分地示出了焊接掩膜(solder mask)5-13。穿过印刷线路板且在两侧呈现的每个过孔5-V1,5-V2...5-VN被示为具有表示过孔的穿通板孔的内部部分的内圆5-11和代表过孔的表面铜的外部部分5-12。安装到铜焊盘5-18、5-19的矩形电容5-15、5-16以轮廓示出,所述铜焊盘5-18、5-19相对于BGA栅格呈对角地安装到BGA设备另一面(或底部)并且位于过孔的两个相邻行之间。安装电容的过孔布局相对于BGA栅格呈对角地移开以容纳所述电容。接头(link)5-L将过孔5-V连接到其相应焊盘5-10。在选择用于去耦电容的过孔位置上,使过孔VS1、VS2处于彼此呈对角的状态并且其相应的接头SL1和SL2已经被缩短(SL1)和/或延长(SL2)。另外注意它们相对于彼此已经进行了旋转(顺时针和逆时针)。相同的处理适用于选择的过孔V5-3和V5-4以及接头SL3和SL4。这些过孔另外具有小过孔5-22、5-23,其内部通过焊接掩膜将其与焊料和焊接的电容分开。注意电路布线或走线通道仍保持在偏移的过孔和未偏移的过孔之间,所述未偏移的过孔保持着BGA栅距。
对不同栅距和电容尺寸(例如:0402)进行改变的准确数量的细节根据尺寸不同而变化。
本发明的优点在于:
-能够使用标准镀通孔(PTH)技术将高密度的去耦电容安装到电路板的背面;
-对在球栅阵列的行之间进行布线限制较少的低计数I/O器件(例如诸如CAM的存储设备)有益,并且也有益于一些高计数I/O设备;
-对于不能使用共用过孔技术的应用是可行的解决方案,且与共用过孔技术具有同样的成本和可靠性;以及
-与其它三种现有技术解决方案(PTH ViP、具有HDI的“停车场”、和填充过孔)相比,具有更小的成本和/或更高的可靠性。
虽然就本发明的优选实施例描述了本发明,应当认识到,本发明的其它实施例、修改和改变对于本领域的技术人员是显而易见的。

Claims (3)

1.一种在多层印刷线路板中的球栅阵列连接盘图形中改变第一、第二选择的相邻过孔之间的间隔和相应的第一、第二连接器之间的间隔以容纳去耦电容焊盘的方法,其中所述图形中的每个连接盘都通过连接器连接到相应的过孔,该方法包括:
旋转、延伸和/或截短所述第一、第二连接器并旋转其各自对应的所述第一、第二选择的相邻过孔以改变所述球栅阵列连接盘图形中所述第一、第二选择的相邻过孔之间的间隔,并将所述电容焊盘应用到所述第一、第二选择的相邻过孔。
2.根据权利要求1的方法,其中,在互为相反的方向上旋转所述第一、第二选择的相邻过孔,以及在互为相反的方向上旋转、延伸和/或截短所述第一、第二连接器。
3.一种印刷线路板,其中根据权利要求1描述的方法修改了过孔和连接器图形。
CN2006100089612A 2005-01-25 2006-01-25 球栅阵列偏栅去耦的设备及方法 Expired - Fee Related CN1842248B (zh)

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KR100725517B1 (ko) * 2005-08-08 2007-06-07 삼성전자주식회사 본딩 패드와 볼 랜드가 복수 층에 형성된 다층 배선 기판및 이를 이용한 반도체 패키지 구조
US7906734B2 (en) * 2007-01-30 2011-03-15 Mcdata Corporation Electrical terminal footprints for a printed circuit board
US7602615B2 (en) * 2007-02-23 2009-10-13 Alcatel Lucent In-grid decoupling for ball grid array (BGA) devices
CN201094168Y (zh) * 2007-09-13 2008-07-30 鸿富锦精密工业(深圳)有限公司 一种电路板
US8555230B2 (en) * 2008-09-19 2013-10-08 The Boeing Company Isolation method and package using a high isolation differential ball grid array (BGA) pattern
US8631706B2 (en) 2010-07-21 2014-01-21 International Business Machines Corporation Noise suppressor for semiconductor packages
US7942687B1 (en) 2010-09-14 2011-05-17 Lockheed Martin Corporation Hollow stem design for high density interconnects
US7997921B1 (en) 2010-10-15 2011-08-16 Lockheed Martin Corporation Connecting elements having a stub surrounded by a hollow stalk with a flange
US8152549B1 (en) 2010-11-01 2012-04-10 Lockheed Martin Corporation Multiple stem design for high density interconnects
US8759689B2 (en) * 2011-01-04 2014-06-24 Alcatel Lucent Land pattern for 0201 components on a 0.8 mm pitch array
US8664541B2 (en) 2011-07-25 2014-03-04 International Business Machines Corporation Modified 0402 footprint for a printed circuit board (‘PCB’)
US8863071B2 (en) 2011-09-13 2014-10-14 Alcatel Lucent De-pop on-device decoupling for BGA
US8806420B2 (en) 2011-09-13 2014-08-12 Alcatel Lucent In-grid on-device decoupling for BGA
US8633398B2 (en) 2011-10-25 2014-01-21 Hewlett-Packard Development Company, L.P. Circuit board contact pads
CN103929876A (zh) * 2013-01-11 2014-07-16 中兴通讯股份有限公司 一种印制电路板组合焊盘
JP6076874B2 (ja) * 2013-09-26 2017-02-08 ルネサスエレクトロニクス株式会社 電子装置、テストボードおよび半導体装置の製造方法
US9510448B2 (en) 2014-08-29 2016-11-29 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Maximizing surface area of surface mount contact pads of circuit board also having via contact pads
US9635760B1 (en) * 2016-01-19 2017-04-25 Alcatel-Lucent Usa Inc. 0204 shifted vias with merge pads
CN105704918B (zh) * 2016-02-01 2018-09-07 浪潮(北京)电子信息产业有限公司 一种高密度印制电路板
US10141277B2 (en) 2017-03-31 2018-11-27 International Business Machines Corporation Monolithic decoupling capacitor between solder bumps
US10729050B2 (en) * 2017-11-16 2020-07-28 Seagate Technology Llc Fine pitch component placement on printed circuit boards
JP7123692B2 (ja) * 2018-08-13 2022-08-23 株式会社日本マイクロニクス 配線基板設計支援装置、配線基板ビア配置方法及び配線基板ビア配置プログラム
US10624208B1 (en) * 2018-10-18 2020-04-14 Arista Networks, Inc. Landing pattern for ball grid array
US10892316B2 (en) 2018-11-15 2021-01-12 Google Llc High density ball grid array (BGA) package capacitor design
US10791627B1 (en) * 2020-02-24 2020-09-29 Panasonic Intellectual Property Management Co., Ltd. Pad and printed board
CN113133219B (zh) * 2021-04-25 2022-09-09 无锡江南计算技术研究所 一种基于交错阵列封装ddr4信号分配方法、芯片

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1201363A (zh) * 1997-05-19 1998-12-09 日本电气株式会社 降低由印刷电路板辐射的电磁噪音
US6417463B1 (en) * 2000-10-02 2002-07-09 Apple Computer, Inc. Depopulation of a ball grid array to allow via placement
CN1503355A (zh) * 2002-11-26 2004-06-09 �Ҵ���˾ 多层陶瓷封装件及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223861A (ja) 1996-02-19 1997-08-26 Canon Inc 半導体集積回路及びプリント配線基板
US7738259B2 (en) * 2004-01-22 2010-06-15 Alcatel Lucent Shared via decoupling for area arrays components
US7269813B2 (en) * 2004-11-19 2007-09-11 Alcatel Off-width pitch for improved circuit card routing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1201363A (zh) * 1997-05-19 1998-12-09 日本电气株式会社 降低由印刷电路板辐射的电磁噪音
US6417463B1 (en) * 2000-10-02 2002-07-09 Apple Computer, Inc. Depopulation of a ball grid array to allow via placement
CN1503355A (zh) * 2002-11-26 2004-06-09 �Ҵ���˾ 多层陶瓷封装件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平9-223861A 1997.08.26

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DE602006011801D1 (de) 2010-03-11
EP1705967A2 (en) 2006-09-27
CN1842248A (zh) 2006-10-04
US20060166398A1 (en) 2006-07-27
EP1705967B1 (en) 2010-01-20

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