CN1841661A

CN1841661A - Semiconductor manufacture method

Info

Publication number: CN1841661A
Application number: CN 200510097061
Authority: CN
Inventors: 丸山隆司
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Semiconductor Ltd
Priority date: 2005-03-31
Filing date: 2005-12-31
Publication date: 2006-10-04
Anticipated expiration: 2025-12-31
Also published as: CN100440434C

Abstract

A semiconductor device manufacture method has the steps of: (a) forming a semiconductor device structure in a chip and alignment marks, respectively in a semiconductor wafer; (b) forming a workpiece layer above the semiconductor wafer; (c) exposing the alignment marks; (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment marks with an electron beam to obtain plural position information on the alignment marks and obtaining differences between the plural position information; (f) removing abnormal values of position information in accordance with the difference between the plural position information; and (g) performing an electron beam exposure in accordance with plural position information of the alignment marks with the abnormal value being removed. An alignment mark detection precision can be improved in electron beam exposure.

Description

Semiconductor manufacturing method

Reference to related applications

This application is based on and claims priority from prior applications such as Japanese patent application No. 2005-100458, filed 3/31/2005, and application No. 2005-279561, filed 9/27/2005, both of which are incorporated herein by reference in their entirety.

Technical Field

The present invention relates to a semiconductor device manufacturing method, and more particularly, to a semiconductor manufacturing method by which a workpiece can be processed by electron beam exposure.

Background

In the process of manufacturing a semiconductor integrated circuit device, lithography is used to form a resist pattern by coating a resist layer on a workpiece layer and exposing and developing it. The accuracy of lithography is an important factor affecting the accuracy, integration degree, and the like of a semiconductor integrated circuit device.

Electron Beam (EB) exposure has very high resolution and is suitable for micromachining in the process of pattern formation. Electron beam exposure can draw very fine patterns per unit area, typically a few microns, e.g. up to 4 microns. Electron beam exposure allows alignment corrections to be made on a very small unit.

If electron beam exposure is performed on a chip unit as shown in fig. 9A, alignment marks at four corners of the chip are detected to correct electron beam deviation, etc., and exposure is performed. The correction contents include contraction factors Gx and Gy, rotation factors Rx and Ry, trapezoidal factors Hx and Hy, and translation factors Ox and Oy in the X and Y directions. The above items can be calculated from a matrix as shown in fig. 9B, where (x, y) and (Δ x, Δ y) are a position coordinate value and a distortion coordinate value of each of four corners of the chip, respectively.

The position of the alignment mark for the electron beam exposure alignment may be detected by detecting electrons reflected from the alignment mark. On this basis, japanese patent laid-open No. JP 9-36019 proposes a method of improving the detection accuracy of the alignment mark by using a plurality of reflection electron detectors and amplifiers, and setting the amplification factor of each amplifier so that the output intensity is constant.

In order to detect the position of the alignment mark with high accuracy and high speed, JP-a-8-17696 proposes to perform electron beam scanning for detecting the alignment mark formed by a step by first scanning that scans a width larger than the width of the mark and second scanning that scans only the edge of the mark.

A reflected electron detector and amplifier are used to detect the reflected electrons. It is not guaranteed that the reflected electronic signal has a sufficiently high intensity. If noise is superimposed on the detector, amplifier, and other such instruments, the signal waveform will be distorted, resulting in the possibility of false detection.

If false detection occurs, the alignment accuracy will be degraded without subsequent process correction.

Disclosure of Invention

The invention aims to improve the detection accuracy of an alignment mark in electron beam exposure.

According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of: (a) in a semiconductor wafer, forming an in-chip semiconductor device structure and a plurality of alignment marks respectively; (b) forming a workpiece layer on the semiconductor wafer; (c) exposing the alignment mark; (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment mark with an electron beam, thereby obtaining a plurality of position information on the alignment mark, and obtaining a difference between the plurality of position information; (f) removing an abnormal value in the position information according to a difference value between the plurality of position information; and (g) performing electron beam exposure in accordance with the plurality of position information of the alignment mark from which the abnormal value has been removed.

False detections may occur if noise is superimposed on the detector, amplifier or related instrumentation. By using the difference between the plurality of pieces of position information, an abnormal value in the position information can be removed. It is possible to prevent local position misalignment due to an alignment mark detection error. Local positional deviation can be avoided. It is possible to improve the exposure position accuracy and further improve the pattern position accuracy.

The position detection time can be shortened, and thus the number of manufacturing processes can be reduced.

By the method of the present invention, a semiconductor integrated circuit device can be manufactured very finely and highly reliably while yield and reliability are improved. By effectively using the function of the electron beam exposure method, a fine pattern can be formed with high accuracy, and the accuracy of the positional alignment between them can be improved. Thereby, the yield and reliability of the semiconductor integrated circuit device can be improved.

Drawings

FIG. 1A is a schematic diagram illustrating the detection principle of an electron beam exposure alignment signal; fig. 1B is a schematic diagram of an oscilloscope showing an example of a signal waveform.

Fig. 2 is a block diagram illustrating the structure of the exposure system.

Fig. 3A to 3D are sectional views illustrating a sample preparation process; fig. 3E is a graph showing the measurement results of the above sample.

Fig. 4A and 4B are a plan view and a graph illustrating electron beam exposure on a semiconductor wafer according to a first embodiment of the present invention, respectively.

Fig. 5A and 5B are a plan view and a graph illustrating a modified form of the first embodiment.

Fig. 6A and 6B are plan views illustrating a second embodiment of the present invention.

Fig. 7 is a plan view illustrating a third embodiment of the present invention.

Fig. 8 is a plan view illustrating a fourth embodiment of the present invention.

Fig. 9A is a schematic plan view illustrating an alignment process according to the prior art; fig. 9B illustrates the equations of the matrix calculation.

Fig. 10A to 10G are sectional views illustrating main processes of a semiconductor device manufacturing method according to an embodiment.

Fig. 11A to 11D are sectional views illustrating main processes of a semiconductor device manufacturing method according to an embodiment.

Detailed Description

In the electron beam exposure process, a common method for detecting an alignment signal is to analyze a reflected electron signal obtained by scanning an alignment mark, which is formed by a step in a layer formed before forming a workpiece layer, with an electron beam.

Fig. 1A and 1B illustrate the detection principle of an alignment signal in electron beam exposure.

As shown in fig. 1A, an alignment mark 2 is scanned with an electron beam 3, the alignment mark 2 is constituted by a groove (step, recessed portion) formed in a surface layer of a silicon substrate 1, and reflected electrons are detected with a detector 4. The output of the detector is amplified by an amplifier and sent to the outside. If an electron beam is focused on the surface of the silicon substrate, the intensity of the reflected electrons at the bottom of the grooves will be weak.

Fig. 1B shows the waveform of a signal on an oscilloscope. When the standard alignment mark having a step height difference of 500nm is detected, the lower signal waveform can be obtained. The difference between the high and low levels of the signals is 0.6V. The upper signal waveform is obtained by differentiating the lower signal waveform. The step corresponds to a portion where the waveform of the differential signal changes.

Fig. 2 is a block diagram illustrating the structure of an electron beam exposure system. A control Workstation (WS)11 composed of a Central Processing Unit (CPU) or the like is connected to the digital control unit (DCTL), the photoelectric control unit 18, and the mechanical unit MS via a Bus (BL), respectively. In a digital control unit (DCTL), an input signal is supplied via a buffer memory 13 to a pattern generation/correction circuit 14, which controls an Analog Circuit (AC) in cooperation with a correction memory 15. The Analog Circuit (AC) includes a digital-to-analog converter/amplifier (DAC/AMP)16 and generates an analog control signal 17 to adjust the deflection of the electron beam. The photoelectric control unit 18 controls the column 20.

The column 20 is connected to an exposure chamber 30, and irradiates an electron beam to a wafer placed on an XY stage 23 in the exposure chamber 30. The exposure chamber is mounted on a vibration isolator 24. A detector 25 for detecting electrons reflected from the wafer is provided in the exposure chamber 30, and supplies a detection signal to the mark detection unit 26. The output signal of the mark detection unit 26 is analyzed by an analog/digital (a/D) converter, i.e., a waveform analysis unit 27, and the analysis result in the form of a digital signal is supplied to a digital control unit (DCTL) and a control Workstation (WS) 11.

The control Workstation (WS)11 and the digital control unit (DCTL) control the deviation of the electron beam in the column and the position of the XY stage 23 in the exposure chamber 30 through the photoelectric control unit 18, the transmission control unit 31, and the stage control unit 32. External devices 12 such as a display, hard disk, and memory may be connected to the control Workstation (WS) 11.

In the alignment operation, the mark scanning signal is output from the pattern generation/correction circuit 14, converted into an analog signal, amplified by a digital-to-analog converter/amplifier (DAC/AMP)16, and applied to the deflection device. The reflected electrons generated during the electron beam scanning are captured by the detector 25 and amplified by the mark detector 26. The position coordinates of the reflected electrons are calculated by an analog/digital (a/D) converter, i.e. a waveform analyzing unit 27, and transmitted to a digital control unit (DCTL). In accordance with the coordinate values obtained in this way, the digital control unit (DCTL) determines the exposure position and performs pattern exposure.

In general, steps in an oxide film, a silicon body, or the like are used for alignment marks on a wafer. The step has a necessary height difference of at least 0.3 μm or more. However, due to process limitations, the required height difference cannot be obtained, and thus sufficient signal strength is not obtained, which may result in a decrease in the signal-to-noise ratio (S/N). There is also another case where erroneous detection occurs due to noise on the digital-to-analog converter/amplifier (DAC/AMP)16 and the detector 25 even if the height difference of the mark step is sufficient. In these cases, the mark coordinate values are erroneously read, and a local positional shift occurs. It is difficult to overcome the positional deviation because it is impossible to judge which mark coordinate value is correct from only the positional information obtained by the position detection.

In the manufacturing process of a semiconductor integrated circuit device, since the pattern rule becomes very fine, the pattern accuracy, particularly the alignment accuracy, becomes a great difficulty and a major factor that hinders fine patterning and high reliability of the semiconductor integrated circuit device. In this case, if the alignment accuracy is lowered, the manufacturing yield and reliability are also lowered. There is also a case where local false detection of the alignment signal is difficult to be excluded due to the influence of minute noise or the like. In the manufacturing process of semiconductor integrated circuit devices, a reduction in positional accuracy, particularly in the accuracy of local positions in a wafer, adversely affects manufacturing yield and reliability.

To explain the case where the positional accuracy is degraded, the present inventors analyzed the detection signal of the reflected electrons output from the detector 25.

Fig. 3A to 3D are sectional views illustrating a sample preparation process. An alignment mark groove (recessed portion) is formed at the same time as forming a shallow trench isolation region as an element isolation structure in a silicon substrate.

As shown in fig. 3A, a Resist Pattern (RP) is formed on a silicon substrate 1, and a groove 2 is formed by etching the silicon substrate. After the Resist Pattern (RP) is removed, an oxide film is deposited by High Density Plasma (HDP) Chemical Vapor Deposition (CVD) to bury the groove 2.

As shown in fig. 3B, an excess oxide film is removed on the silicon substrate 1 by Chemical Mechanical Polishing (CMP). The groove 2 is buried with an oxide film 6. Thereby forming shallow trench isolation regions. And the alignment mark 2 buried with the oxide film 6 is formed. In the fabrication of semiconductor integrated circuit devices, various processes such as ion implantation for forming a well, ion implantation for adjusting a threshold value, formation of a gate insulating film, formation of a gate electrode structure, and ion implantation for forming source/drain regions are performed thereafter.

As shown in fig. 3C, an interlayer insulating film 7 made of silicon dioxide or the like is formed on the silicon substrate 1. The buried oxide film 6 is also covered with an interlayer insulating film 7. The contact holes are aligned using alignment marks formed by the process of forming the shallow trench isolation regions. Preferably a step (step) capable of exposing the alignment mark.

As shown in fig. 3D, the resist pattern is formed to have an opening that exposes a region including the buried oxide film 6, and silicon oxide exposed in the opening is etched away. The interlayer insulating film 7 and the buried oxide film 6 are etched away, so that the grooves 2 formed as alignment marks are exposed.

When the alignment mark is detected, the detection of the opposite side of the groove is detected. The position of the mark is obtained as an average of the positions of the opposite ends of the groove. The groove width is designed to be, for example, 2 μm. If an abnormal value is detected due to noise, the resulting mark width is considered to be also an abnormal value. The mark width can be easily detected by detecting the mark.

Fig. 3E is a graph showing the amount of shift of the mark width obtained by detecting the alignment mark on the wafer compared to the design mark width of 2 μm. The offset in the X direction is represented by a rhomboid symbol and the offset in the Y direction is represented by a triangle symbol. Although most of the detection values are distributed in the vicinity of 0, the detection values having some large offset at the left end are far from the 0 point. If the alignment is performed using the far detection values of the large shift amounts or the detection values including the far detection values, the error becomes large. If there is a detection value that is significantly abnormal, normal alignment can be performed by using a detection value that does not include a detection value at a far distance.

The present invention provides a method of removing an abnormal value from a detection signal of a detector 25 and correcting the detection value with high accuracy using a simple program if it is difficult to remove noise, thereby improving productivity of manufacturing a semiconductor integrated circuit device using electron beam exposure.

The present inventors also found that the marker width information obtained from the position detection information is effective for removing the abnormal value, and by effectively utilizing the marker width information, the abnormal value can be removed very efficiently.

Before the product is exposed, the marks are detected at several points on the wafer, and the width of each mark is obtained. A reference dimension is determined based on these widths. When each chip is actually aligned, data far from the reference size is not used, or the mark is re-detected without using abnormal data. In this way, positional misalignment is avoided. For example, the average value is basically employed as the reference value.

In removing the abnormal value, it is important to correctly determine the mark width reference value in order to obtain high accuracy. It is effective to design the mark structure so that the width of the mark can be correctly determined. If rounded corners cause problems, a mark shape that is long in one direction may be used and the central portion unaffected by the corners is monitored.

First embodiment

Referring to fig. 4A and 4B, electron beam exposure of the first embodiment is explained. The process shown in fig. 3A is performed to form a resist pattern on the silicon substrate, the resist pattern having an opening for the element isolation groove pattern in the semiconductor integrated circuit device region and for the alignment mark pattern. By using the resist pattern as a mask, a trench is etched in the silicon substrate to form a step. The element isolation shallow trench and the alignment mark are formed simultaneously. The step height is generally about 0.3 μm, but it may vary depending on the semiconductor integrated circuit device to be manufactured. An oxide film burying the trench is formed and an unnecessary oxide film is removed using a Chemical Mechanical Polishing (CMP) process to form the structure shown in fig. 3B. By performing several processes, an insulating film as shown in fig. 3C is formed before forming the contact hole. In order to obtain the alignment signal, the step needs to be restored. Referring to fig. 3D, a resist pattern exposing the alignment mark and a peripheral region thereof is formed, and the step is exposed by etching the insulating film.

As shown in fig. 4A, alignment marks at the upper right portions of five chips located at the center, upper, lower, left, and right of the wafer are detected, thereby obtaining mark widths W1, W2, W3, W4, and W5. The average value Wref of these widths is set as a reference value of the wafer mark width. Wherein,

Wref＝AVERAGE(W1，W2，W3，W4，W5)。

the allowable range R is set in the following range:

ΔW＝|W-Wref|，

values beyond R are removed as outliers and are not referenced.

For example, the design value of the mark width is set to 2 μm. Assume that the following width data is obtained as the final groove width:

W1x＝2.16，W2x＝2.15，W3x＝2.14，W4x＝2.15，W5x＝2.15。

in this case Wxref of 2.15 μm was obtained as the final groove width. Similarly, Wyref was obtained at 2.15 μm. The allowable range R is set to, for example, 0.10 μm in consideration of process variations and allowable position detection variations, and values in the range of 2.05 μm to 2.25 μm are all allowed.

Fig. 4B is a view illustrating the mark widths detected in the order of exposing the chips after actually detecting the mark position of each chip, measuring the mark width, and removing the mark width outside the allowable range. Those abnormal detection values shown in fig. 3E can be avoided.

Electron beam exposure also requires focus adjustment. Before the first exposure position alignment is performed, the alignment mark is scanned with an electron beam, and the reflected electron signal is monitored. For example, by varying the focal length of the objective lens, the focus condition is selected where the differential waveform exhibits the greatest peak intensity. In this way the best focus can be determined. In this process, the mark width can be sampled and the preliminary sampling and mark width measurements can be shared.

In some cases, the width of the marks formed in the layer below the workpiece layer may have some distribution in the in-plane (in-plane) wafer due to, among other things, the distribution of etching and chemical mechanical polishing in the semiconductor process.

Fig. 5A and 5B illustrate the distribution of alignment mark widths in the wafer. Fig. 5A is a plan view, and fig. 5B illustrates a width distribution along a certain direction. In order to remove the abnormal value with high accuracy, it is necessary to correctly determine the mark width reference value. If the same reference values and tolerance ranges are used for the entire wafer or a wider area of the wafer, and if the tolerance ranges are narrow, many outliers will be detected and the number of samples allowed will be reduced. If the allowable range is expanded, even an abnormal sample is used as a normal sample. Both of these cases are not suitable for removing outliers with high accuracy.

If the distribution has a predetermined trend, an abnormal value can be detected with high accuracy by using a mark width reference value expressed as a function of position. Many of the distribution trends, as shown in FIG. 5A, have a width distribution that is concentric with respect to the center of the wafer.

In the case where the mark widths are distributed in the wafer within the plane due to some problems in the process of forming the marks in the layer below the workpiece layer, it is effective to remove the abnormal values with high accuracy by changing the reference values in the wafer using the plane, the curved surface, or the like including the polynomial based on the sampling result.

If the mark width distribution varies in a parabolic shape, it is useful to express this distribution by a quadratic equation, for example W ═ ar²+ br + c (r is the distance to the center, r²＝X²+y²). In the example shown in fig. 5B, the curve parameters are approximately a-0.001 and c-2.1. The reference width of each position of the wafer is determined by this equation, and the outlier can be removed with high accuracy.

The function of mark width versus mark position is not limited to this equation. Depending on the distribution, the in-plane distribution can be approximated as a linear equation including a polynomial, a quadratic equation different from the above quadratic equation, a cubic equation or higher.

In the electron beam exposure, the position of each alignment mark is detected, usually in a unit group including a chip unit, a chip column unit, or the like, and exposure is performed after alignment. In this case, after the positions of the alignment marks in one group are detected, a reference width such as an average width is calculated, and an abnormal value of a large shift amount is removed, or the width is measured again to exclude abnormal value data. In this way, positional misalignment can be avoided.

Second embodiment

Fig. 6A illustrates an example of alignment mark placement in a wafer. Alignment marks 9 are provided near the four corners of each chip 8 in the wafer, respectively.

Fig. 6B is an enlarged view of a chip area. The alignment mark 9 is provided at a position not overlapping with the scribe line 10. The alignment mark may also overlap the scribe line if inspection is not required after scribing with the scriber. As shown in fig. 6A, four alignment marks are provided near each edge of the chip except for the outermost edge. These labels are assigned to two adjacent chips.

In a unit group including a chip unit, a chip column unit, and the like, alignment mark detection, alignment, and exposure are repeatedly performed. In this case, the mark widths W1, W2, W3, W4 of each chip or the mark widths W1(i), W2(i), W3(i), W4(i) of each group obtained at a time are used to determine the reference mark width Wref, for example,

Wref＝AVERAGE(W1，W2，W3，W4)，

or Wref ═ AVERAGE Σ (W1(i), W2(i), W3(i), W4 (i)).

The allowable range R of Δ W is set

ΔW＝|W-Wref|，

And outliers outside of the tolerance are removed and not referenced. The other points are similar to those of the first embodiment. Similar to the first embodiment, erroneous detection can be avoided.

This embodiment does not require a preliminary process and can be used even if there is a large local variation in the mark width in the wafer within the plane. However, there is a disadvantage in that if the reference width is determined in the chip unit, the outlier removal accuracy cannot be high because the number of reference points used to obtain the average value is small. If it is necessary to remove the abnormal value with high accuracy, it is preferable to group several chips to increase the number of reference points used to obtain the reference width, and then perform alignment mark detection, alignment, and exposure.

At the position detection points in the X and Y directions, the same value can be used as the mark width. If the detected widths in the X and Y directions measured at each position detection point exceed a predetermined difference, these values are removed or the widths are measured again to avoid taking outlier data. In this way, positional misalignment can be avoided. Even in the mark formation layer, the mark size distributed in the wafer in the plane is large, and the influence on the mark distribution is small, and this embodiment is particularly effective for this case.

Third embodiment

As shown in fig. 7, the alignment mark at each position is constituted by a pair of an X-direction mark MX and a Y-direction mark MY. That is, each of the alignment marks 9 shown in fig. 6A is constituted by two marks MX and MY. The widths of the markers MX and MY in the X-direction and Y-direction are the same.

A pair of X-and Y-directional marks are placed in regions that are considered to have the same processing conditions, and the X-and Y-directional marks are alternately scanned. The abnormal value is determined by the difference Δ between the X-direction mark width Wx and the Y-direction mark width Wy being Wx-Wy.

For example, the design value of the mark width is set to 2 μm, and the allowable difference is set to 0.10 μm. If the mark width of the

mark

1, 2, … is detected as Wx1 ═ 2.10 μm, Wy1 ═ 2.11 μm, Wx2 ═ 2.40 μm, Wy2 ═ 2.10 μm, and … the XY difference of the second mark exceeds the allowable difference. This is thus judged to be an erroneous detection, and these values are removed from the position detection information. For example, if the width measured again is Wx2 ═ 2.10 μm, this mark width is used as position detection information. With this process, a large positional misalignment can be avoided. The alignment mark may also be a square and the difference in mark width in the X and Y directions is obtained.

The obtained width is taken as the first level difference between the positions. The difference between the widths in the X and Y directions is the second order difference between the positions. The second level of difference is not limited to differences between widths along different directions, and other differences may be used.

Fourth embodiment

As shown in fig. 8, at each measurement point, a plurality of alignment marks are arranged in the same direction. For example, the alignment marks MX1 and MX2, which are long in the Y direction, are juxtaposed along the X direction. The center portions of the markers MX1 and MX2 are obtained, and the marker width is set to the distance between the centers of the two alignment markers MX1 and MX2 in the width direction. By using the mark width, outliers can be effectively removed. Since the distance between the marks is hardly affected by the processing steps, a value close to the design value can be obtained. Therefore, even if the design value itself is used as the reference value, the abnormal value can be removed with high accuracy, and since it is not necessary to set the reference value for each wafer or region within the wafer, the abnormal value can be removed with high efficiency. It is effective that there is no difference between distances between the respective patterns if the plurality of mark widths are set to the same width.

Fig. 10A to 10G are sectional views illustrating main processes of a semiconductor device manufacturing method including the alignment process of any of the above embodiments. The left side of each figure shows the semiconductor region and the right side shows the alignment mark region.

As shown in fig. 10A, the surface of the silicon substrate 1 is thermally oxidized to form a buffer oxide film 1x, and thereafter, a silicon nitride film 55 is deposited on the buffer oxide film 1x by Low Pressure (LP) Chemical Vapor Deposition (CVD). The silicon nitride film 55 functions as a barrier layer in subsequent Chemical Mechanical Polishing (CMP). On the silicon nitride film 55, a resist pattern RP1 having openings for exposing the isolation trenches and the alignment marks is formed. The resist pattern RP1 is formed by optical exposure or electron beam exposure. The silicon nitride film 55 is subjected to Reactive Ion Etching (RIE) using a fluorine-containing etching gas by using the resist pattern RP1 as a mask, and then the silicon substrate 1 is subjected to Reactive Ion Etching (RIE) by replacing the gas with a chlorine-containing etching gas. The etching depth of the silicon substrate is, for example, about 300 nm. The resist pattern RP1 is subsequently removed. This process corresponds to the process shown in fig. 3A. An isolation trench (ST) is formed on each chip region, and a groove as an Alignment Mark (AM) is formed on each chip peripheral region. For example, the minimum width of the Shallow Trench (ST) is about 200nm, and the mark width of the alignment mark is about 1 to 5 μm, but the mark width may vary depending on the design of the semiconductor integrated circuit device.

As shown in fig. 10B, the silicon oxide film 6 is deposited by High Density Plasma (HDP) Chemical Vapor Deposition (CVD) to bury the Shallow Trench (ST). At the same time, the Alignment Mark (AM) is also buried by the silicon dioxide film 6. The excess portion of the silicon dioxide film is removed using Chemical Mechanical Polishing (CMP) to make the substrate surface flat. The exposed silicon nitride film 55 is removed with hot phosphoric acid, and the buffer oxide film 1x is etched and removed with diluted hydrofluoric acid. Thus, Shallow Trench Isolation (STI) and Alignment Mark (AM) buried by the oxide film are formed. This process corresponds to the process shown in fig. 3B.

As shown in fig. 10C, ions are implanted into the element region by using a resist mask to form a p-type well (PW) and an n-type well (NW). B and the like are used as P-type impurities, and P and the like are used as n-type impurities. A silicon oxide film on a surface of the silicon substrate is removed, and thermal oxidation is performed to grow a new gate oxide film (Gox) having a thickness of, for example, 2nm or less. Nitrogen is introduced into the gate oxide film, and/or a high dielectric constant layer is stacked on the gate oxide film, if necessary. On the gate oxide film (Gox), a polysilicon film is deposited by Chemical Vapor Deposition (CVD), and a resist pattern is formed on the polysilicon film. The resist pattern may be a trim optical resist pattern or an electron beam resist pattern. The polysilicon layer is etched to form a gate electrode (G) by using the resist pattern as a mask. The resist pattern is subsequently removed.

By using the region-separated resist pattern, n-type impurity ions, such as P ions, are implanted into the P-type well (PW) to dope the impurity into the gate electrode (G), and source/drain extension regions (EX) are formed on both sides of the gate electrode. For an n-type well (NW), p-type impurity ions such as B ions are implanted. An insulating film such as a silicon oxide film is deposited and Reactive Ion Etching (RIE) is performed to form a sidewall insulating film (SW) on the sidewall of the gate electrode (G). Then, n-type impurity ions are implanted into a p-type well (PW) and p-type impurity ions are implanted into an n-type well (NW) to form high-concentration source/drain regions (S/D). After the MOS transistor structure is formed in this manner, an interlayer insulating film 7 made of phosphosilicate glass (PSG) or the like is deposited by Chemical Vapor Deposition (CVD). The surface of the interlayer insulating film is planarized by Chemical Mechanical Polishing (CMP). This state corresponds to the state shown in fig. 3C. Although only the n-channel MOS transistor formed in the p-type well (PW) is shown, the p-channel MOS transistor is also formed in the n-type well (NW). Contact holes exposing high concentration source/drain regions (S/ds) in the MOS transistor are then formed by etching. The etching requires high accuracy, which is performed by electron beam exposure for position alignment using an alignment mark.

As shown in fig. 10D, the resist pattern RP2 is formed to have an opening that exposes a region including the Alignment Mark (AM). The entire element region is covered with the resist pattern. The resist pattern has an accuracy of, for example, about 0.5 μm, which does not require high accuracy. The resist pattern can be formed by optical exposure using an optical coarse alignment mechanism installed in the electron beam exposure system.

As shown in fig. 10E, Reactive Ion Etching (RIE) is performed on the interlayer insulating film 7 exposed at the opening using a fluorine-containing etching gas, and then Reactive Ion Etching (RIE) is performed on the silicon oxide film 6 buried in the Alignment Mark (AM) trench. The resist pattern RP2 is subsequently removed. A step of the silicon substrate is exposed in an Alignment Mark (AM).

As shown in fig. 10F, a resist film for electron beam exposure is applied, and an alignment mark is detected using an electron beam. The resist film is almost transparent to the electron beam, so that the alignment mark step can be easily detected. After establishing high-precision alignment using an electron beam, in order to form a contact hole, electron beam exposure and development are performed to form a resist pattern RP 3. By using the resist pattern RP3 as an etching mask, the interlayer insulating film 7 is subjected to Reactive Ion Etching (RIE) using a fluorine-containing etching gas. Contact holes are thus formed to reach the source/drain regions (S/D). The alignment mark region remains in a state of being covered with the resist pattern RP 3. The resist pattern RP is then removed.

Subsequently, as shown in fig. 10G, a barrier film such as a TiN film is formed, and then by using WF₆Performing Chemical Vapor Deposition (CVD) to deposit tungsten film to bury contact hole. An unnecessary metal film deposited on the interlayer insulating film 7 is removed by Chemical Mechanical Polishing (CMP), thereby forming a conductive Plug (PL) burying the contact hole.

Subsequently, a multilayer wiring is formed using a usual process. The alignment mark used in the multi-layer wiring forming process may be a step of an alignment mark formed in the substrate and exposed again, or a step of an alignment mark formed simultaneously with a new wiring.

Fig. 11A to 11D illustrate a forming process of a via hole for forming a multilayer wiring. An n-channel MOS transistor (NMOS), a p-channel MOS transistor (PMOS), a transistor covered with an interlayer insulating film 7, and a conductive Plug (PL) formed for the source/drain region S/D are formed as shown in the processes of fig. 10A to 10G.

As shown in fig. 11A, a metal wiring layer 51 made of aluminum or the like is deposited on a semiconductor wafer. A resist pattern RP4 is formed on the metal wiring layer 51 for patterning the wiring and the alignment mark. The resist pattern RP4 may be an optical resist or an electron beam resist. The alignment marks shown in fig. 10D and 10E can be restored if necessary. The metal wiring layer 51 is etched to form a metal wiring and an alignment mark by using the resist pattern RP4 as an etching mask. Inverter wiring is formed in the left region of the drawing. The metal pattern 51x shown in the right area of the figure is an alignment mark.

As shown in fig. 11B, an interlayer insulating film 53 made of silicon dioxide or the like is deposited by Chemical Vapor Deposition (CVD) to cover the patterned metal wiring layer. Similarly to the process shown in fig. 10D, the resist pattern is formed with an opening exposing the region 54 including the alignment mark, and the interlayer insulating film 53 is etched to expose the alignment mark 51 x.

As shown in fig. 11C, an electron beam resist RP5 is applied. The alignment mark 51x is detected by scanning the electron beam. As described previously, a plurality of position information is obtained to calculate the difference. By using the difference, the outlier is removed. The opening for forming the via reaching the wiring pattern 51 is exposed in accordance with the position information of the alignment mark from which the abnormal value is removed.

As shown in fig. 11D, the interlayer insulating film 53 is etched to form the via hole 57 by using the resist pattern RP5 having the opening 56 as an etching mask. The resist pattern RP5 is then removed, and a conductive layer to bury the via hole is formed. The conductive layer deposited on the interlayer insulating film 53 is removed to form a via conductor (via conductor). This process is similar to the process shown in fig. 10G.

The invention has been described in connection with the preferred embodiments described above. The present invention is not limited to the above-described embodiments. For example, the gate electrode may be made of a polycide, a metal, or the like. The conductive plug may be made of silicon, TiN, or the like, in addition to using tungsten. The MOS transistor may have a pocket region of opposite conductivity type around the extension region of the source/drain. The electron beam resist film may have a multilayer structure in addition to a single-layer structure. It is evident that those skilled in the art may now make numerous other modifications, improvements, combinations, and the like, of the present invention.

Claims

1. A semiconductor device manufacturing method comprising the steps of:

(a) in a semiconductor wafer, forming an in-chip semiconductor device structure and a plurality of alignment marks respectively;

(b) forming a workpiece layer on the semiconductor wafer;

(c) exposing the alignment mark;

(d) coating an electron beam resist film on the workpiece layer;

(e) scanning the alignment mark with an electron beam, thereby obtaining a plurality of position information on the alignment mark, and obtaining a difference between the plurality of position information;

(f) removing an abnormal value in the position information according to a difference value between the plurality of position information; and

(g) and performing electron beam exposure according to the plurality of position information of the alignment mark from which the abnormal value has been removed.

2. The manufacturing method of a semiconductor device according to claim 1, wherein

The difference between the plurality of position information in the step (e) is a width of each of the alignment marks, which is a first-level difference; and

the step (f) removes the outlier by comparing the width of each alignment mark with a reference value of the width of the alignment mark.

3. The semiconductor device manufacturing method according to claim 1, wherein the difference between the plurality of pieces of positional information in the step (e) is a second-level difference of the plurality of pieces of positional information.

4. The manufacturing method of a semiconductor device according to claim 3, wherein

Obtaining position information of each alignment mark in the X and Y directions in the step (e), a width of each alignment mark in the X and Y directions as a first level error value, and a difference value between the widths in the X and Y directions as a second level difference value; and

in the step (f), the abnormal value is removed by comparing a difference between the widths of each alignment mark in the X and Y directions with a specified value.

5. The manufacturing method of a semiconductor device according to claim 3, wherein

Setting a plurality of alignment marks on each sampling point along the same direction in the step (a);

scanning the plurality of alignment marks on each sampling point along the same direction in the step (e), obtaining a center position of each alignment mark as a first-level difference value, and obtaining a distance between the center positions as a second-level difference value; and

said step (f) removing said outliers by comparing said distance between said center positions to a specified value.

6. The manufacturing method of a semiconductor device according to claim 1, wherein

The step (e) comprises the steps of:

(e-1) pre-scanning the alignment mark at a plurality of points on the in-plane wafer with the electron beam, and determining a reference value according to a plurality of differences between a plurality of position information obtained by the pre-scanning;

(e-2) scanning each alignment mark on the wafer in the plane, and obtaining positional information on each alignment mark and a difference between the positional information;

the step (f) comprises the following steps:

(f-1) obtaining a difference between the reference value and the difference between the position information of each alignment mark, and comparing it with a specified value.

7. The semiconductor device manufacturing method according to claim 6, wherein the step (e-1) uses an average value of widths of the pre-scanned alignment marks as the reference value.

8. The semiconductor device manufacturing method according to claim 6, wherein the step (e-1) represents the reference value as a function of position on the in-plane wafer.

9. A semiconductor device manufacturing method according to claim 1, wherein the steps (e), (f) and (g) are repeatedly performed in a unit group consisting of one to several core pieces.

10. The manufacturing method of a semiconductor device according to claim 1, wherein the step (a) forms a shallow trench isolation region as the semiconductor device structure, and the alignment mark has a structure formed in such a manner that a concave portion is formed in the semiconductor wafer, and the concave portion is buried with an insulator while the shallow trench isolation region is formed, followed by removing the insulator.