CN1841661A - semiconductor manufacturing method - Google Patents

Abstract

A semiconductor manufacturing method, comprising the steps of: (a) forming an in-chip semiconductor device structure and a plurality of alignment marks in a semiconductor wafer; (b) forming a workpiece layer on the semiconductor wafer; (c) exposing the (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment mark with an electron beam, thereby obtaining a plurality of positional information about the alignment mark, and obtaining a plurality of positional information (f) removing abnormal values in the position information according to the differences between the plurality of position information; and (g) performing electron beam exposure according to the plurality of position information of the alignment marks from which the abnormal values have been removed. Alignment mark detection accuracy can be improved in electron beam exposure.

Description

semiconductor manufacturing method

References to related applications

This application is based on and claims priority from the earlier applications of Japanese Patent Application No. 2005-100458 filed on March 31, 2005, and application No. 2005-279561 filed on September 27, 2005, the entire contents of both applications Incorporated here by reference.

technical field

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor by which a workpiece can be processed by electron beam exposure.

Background technique

In the process of manufacturing semiconductor integrated circuit devices, lithography is used to form a resist pattern by coating a resist layer on a workpiece layer, exposing and developing it. The precision of lithography is an important factor affecting the precision, degree of integration, and the like of a semiconductor integrated circuit device.

Electron beam (EB) exposure has high resolution and is suitable for microfabrication during pattern formation. Electron beam exposure can draw very fine patterns on a unit area of typically a few micrometers, for example a maximum of 4 micrometers. Electron beam exposure allows alignment correction on very small units.

If electron beam exposure is performed on a chip unit, as shown in FIG. 9A, the alignment marks at the four corners of the chip are detected to correct electron beam deviation, etc., and exposure is performed. The correction content includes contraction factors Gx and Gy, rotation factors Rx and Ry, trapezoidal factors Hx and Hy, and translation factors Ox and Oy along the X and Y directions. The above items can be calculated from the matrix shown in FIG. 9B , where (x, y) and (Δx, Δy) are the position coordinates and distortion coordinates of each of the four corners of the chip, respectively.

The position of the alignment mark for electron beam exposure alignment can be detected by detecting electrons reflected from the alignment mark. On this basis, Japanese Patent Publication No. JP 9-36019 proposes a method for improving the detection accuracy of alignment marks, that is, by using multiple reflected electron detectors and amplifiers, and setting the amplification factor of each amplifier Make the output intensity a constant.

In order to detect the position of the alignment mark with high precision and high speed, JP Patent Laid-Open No. Hei 8-17696 proposes to perform electron beam scanning for detecting the alignment mark formed by the step by a first scan and a second scan, wherein the first scan is a scan For widths greater than the mark width, the second scan scans only the sides of the mark.

Reflected electron detectors and amplifiers are used to detect reflected electrons. There is no guarantee that the reflected electronic signal will have a sufficiently high intensity. If noise is superimposed on detectors, amplifiers, and other such instruments, the signal waveform will be distorted, resulting in the possibility of false detection.

If a false detection occurs, the alignment accuracy will be degraded without subsequent procedural correction.

Contents of the invention

An object of the present invention is to improve the accuracy of alignment mark detection in electron beam exposure.

According to one aspect of the present invention, a semiconductor device manufacturing method is provided, which includes the following steps: (a) forming an in-chip semiconductor device structure and a plurality of alignment marks in a semiconductor wafer; (c) exposing the alignment mark; (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment mark with an electron beam to obtain information about the aligning a plurality of position information of the mark, and obtaining a difference between the plurality of position information; (f) removing an abnormal value in the position information according to the difference between the plurality of position information; and (g) according to the obtained E-beam exposure is performed on a plurality of pieces of positional information of the alignment marks from which outliers have been removed.

False detections can occur if noise is superimposed on detectors, amplifiers, or related instruments. By using the difference between a plurality of pieces of location information, abnormal values in the location information can be removed. It is possible to prevent partial positional misalignment due to alignment mark detection errors. A local position shift can be avoided. It is possible to improve exposure position accuracy and further improve pattern position accuracy.

The position detection time can be shortened, whereby the number of manufacturing steps can be reduced.

By the method of the present invention, a semiconductor integrated circuit device can be manufactured very finely and highly reliably, while yield and reliability can be improved. By effectively using the function of the electron beam exposure method, fine patterns can be formed with high precision, and the positional alignment accuracy between them can be improved. Thus, the yield and reliability of the semiconductor integrated circuit device can be improved.

Description of drawings

1A is a schematic diagram illustrating the detection principle of an electron beam exposure alignment signal; FIG. 1B is a schematic diagram of an oscilloscope showing an example of a signal waveform.

Fig. 2 is a block diagram illustrating the structure of an exposure system.

3A to 3D are cross-sectional views illustrating the preparation process of samples; FIG. 3E is a graph showing measurement results of the above samples.

4A and 4B are respectively a plan view and a diagram illustrating electron beam exposure on a semiconductor wafer according to a first embodiment of the present invention.

5A and 5B are plan views and graphs illustrating modifications of the first embodiment.

6A and 6B are plan views illustrating a second embodiment of the present invention.

Fig. 7 is a plan view illustrating a third embodiment of the present invention.

Fig. 8 is a plan view illustrating a fourth embodiment of the present invention.

FIG. 9A is a schematic plan view illustrating an alignment process according to the prior art; FIG. 9B illustrates equations for matrix calculation.

10A to 10G are cross-sectional views illustrating main processes of the semiconductor device manufacturing method according to the embodiment.

11A to 11D are cross-sectional views illustrating main processes of the semiconductor device manufacturing method according to the embodiment.

Detailed ways

In the electron beam exposure process, a common method for detecting the alignment signal is to analyze the reflected electron signal obtained by scanning the alignment mark with the electron beam in a layer formed before forming the workpiece layer. formed by steps.

1A and 1B illustrate the detection principle of an alignment signal in electron beam exposure.

As shown in FIG. 1A , an alignment mark 2 composed of a groove (step, concave portion) formed in the surface layer of a silicon substrate 1 is scanned with an electron beam 3 and detected with a detector 4. reflected electrons. The output of this detector is amplified by an amplifier and sent to the outside. If an electron beam is focused onto the surface of the silicon substrate, the intensity of the reflected electrons at the bottom of the groove will be weakened.

Figure 1B shows the signal waveform on an oscilloscope. When a standard alignment mark having a step height difference of 500 nm is detected, the signal waveform below can be obtained. The high and low level difference of the signal is 0.6V. The upper signal waveform is calculated by differentiating the lower signal waveform. The step corresponds to a portion where the waveform of the differential signal changes.

Fig. 2 is a block diagram illustrating the structure of an electron beam exposure system. A control workstation (WS) 11 composed of a central processing unit (CPU) and the like is respectively connected to a digital control unit (DCTL), a photoelectric control unit 18 and a mechanical unit MS via a bus (BL). In the digital control unit (DCTL), an input signal is supplied via a buffer memory 13 to a pattern generation/correction circuit 14 which controls an analog circuit (AC) in conjunction with a correction memory 15 . The analog circuit (AC) includes a digital-to-analog converter/amplifier (DAC/AMP) 16 and generates an analog control signal 17 to adjust the deviation of the electron beam. The photoelectric control unit 18 controls the columns 20 .

The column 20 is connected to an exposure chamber 30 , and irradiates electron beams to a wafer placed on the XY table 23 in the exposure chamber 30 . The exposure chamber is mounted on an anti-vibration device 24 . A detector 25 for detecting electrons reflected from the wafer is provided in the exposure chamber 30 and supplies a detection signal to the mark detection unit 26 . The output signal of the mark detection unit 26 is analyzed by an analog/digital (A/D) converter, namely a waveform analysis unit 27 , and the analysis result in the form of a digital signal is provided to the digital control unit (DCTL) and the control workstation (WS) 11 .

The control workstation (WS) 11 and the digital control unit (DCTL) control the deviation of the electron beam in the column and the position of the XY table 23 in the exposure chamber 30 through the photoelectric control unit 18, the transmission control unit 31 and the table control unit 32. External devices 12 such as a display, a hard disk, and a memory may be connected to the control workstation (WS) 11 .

In the alignment operation, the mark scanning signal is output from the pattern generation/correction circuit 14, converted into an analog signal, amplified by a digital-to-analog converter/amplifier (DAC/AMP) 16, and applied to a deflection device. Reflected electrons generated during electron beam scanning are captured by detector 25 and amplified by mark detector 26 . The position coordinates of the reflected electrons are calculated by an analog/digital (A/D) converter, that is, the waveform analysis unit 27, and sent to the digital control unit (DCTL). According to the coordinate values obtained in this way, the digital control unit (DCTL) determines the exposure position and performs pattern exposure.

Typically, alignment marks on a wafer use steps in oxide films, silicon bodies, and the like. The necessary height difference of the steps is at least 0.3 μm or deeper. However, due to the limitation of the process, there are cases where the above-mentioned necessary height difference cannot be obtained, and therefore there is not enough signal strength, resulting in a decrease in the signal/noise ratio (S/N). There is another case where false detection occurs due to noise on the digital-to-analog converter/amplifier (DAC/AMP) 16 and detector 25 even if the height difference of the marked steps is sufficient. In these cases, marker coordinate values are read incorrectly and local position shifts occur. It is difficult to overcome the position offset because it is impossible to judge which marker coordinate value is correct only from the position information obtained through position detection.

In the manufacturing process of semiconductor integrated circuit devices, since pattern rules become very fine, pattern accuracy, especially alignment accuracy, becomes a big problem and a major factor hindering fine patterning and high reliability of semiconductor integrated circuit devices. In this case, if alignment accuracy is lowered, manufacturing yield and reliability are also lowered. There are also cases where local erroneous detection of the alignment signal is difficult to exclude due to the influence of fine noise or the like. During the manufacture of semiconductor integrated circuit devices, reductions in positional accuracy, particularly locally within a wafer, can adversely affect manufacturing yield and reliability.

The present inventors analyzed the detection signal of reflected electrons output from the detector 25 in order to explain the reduction in positional accuracy.

3A to 3D are cross-sectional views illustrating a sample preparation process. While forming shallow trench isolation regions as element isolation structures in the silicon substrate, alignment mark grooves (recessed portions) are formed.

As shown in FIG. 3A, a resist pattern (RP) is formed on a silicon substrate 1, and grooves 2 are formed by etching the silicon substrate. After the resist pattern (RP) is removed, an oxide film is deposited by high density plasma (HDP) chemical vapor deposition (CVD) to bury the groove 2 .

As shown in FIG. 3B , chemical mechanical polishing (CMP) is used to remove excess oxide film on the silicon substrate 1 . An oxide film 6 is buried inside the groove 2 . Shallow trench isolation regions are thus formed. And the alignment mark 2 buried with the oxide film 6 is formed. In the manufacturing process of a semiconductor integrated circuit device, various processes such as ion implantation for forming a well, ion implantation for adjusting a threshold value, formation of a gate insulating film, formation of a gate electrode structure, and formation of a gate electrode structure are performed thereafter. Ion implantation to form source/drain regions.

As shown in FIG. 3C , an interlayer insulating film 7 made of silicon dioxide or the like is formed on a silicon substrate 1 . The buried oxide film 6 is also covered with an interlayer insulating film 7 . The contact holes are aligned using alignment marks formed by the process of forming shallow trench isolation regions. A step capable of exposing the alignment mark is preferred.

As shown in FIG. 3D, a resist pattern is formed to have an opening exposing a region including the buried oxide film 6, and silicon dioxide exposed in the opening is etched away. The interlayer insulating film 7 and the buried oxide film 6 are etched away so that the groove 2 formed as an alignment mark is exposed.

When the alignment mark is detected, the opposite edge of the groove is detected. Obtain the position of the marker as the average of the positions of the opposite ends of the groove. The groove width is designed to be, for example, 2 μm. If an abnormal value is detected due to noise, the resulting mark width is considered to be also an abnormal value. The mark width can be easily detected by detecting the mark.

FIG. 3E is a graph showing a shift amount of a mark width obtained by detecting an alignment mark on a wafer compared to a design mark width of 2 μm. The offset in the X direction is represented by a rhombus symbol, and the offset in the Y direction by a triangle symbol. Although most detections are distributed around 0, there are some detections with large offsets on the left end far away from 0. If these distant detection values with large offsets or detection values including these distant detection values are used for alignment in the alignment process, errors will become large. If there are obviously abnormal detection values, normal alignment can be performed by using detection values that do not include distant detection values.

The present invention provides a method of removing abnormal values from the detection signal of the detector 25 and correcting the detection value with a simple procedure if it is difficult to remove noise, thereby improving the efficiency of manufacturing semiconductors by electron beam exposure. Productivity of integrated circuit devices.

The present inventors also found that mark width information obtained from position detection information is effective for removing outliers, and by effectively using the mark width information, outliers can be removed very efficiently.

Before the product is exposed, the marks are inspected at several points on the wafer and the width of each mark is obtained. Determine reference dimensions based on these widths. When each chip is actually aligned, data far from the reference size is not used, or marks are re-detected without using abnormal data. In this way positional misalignments are avoided. For example, an average value is basically adopted as a reference value.

In order to obtain high precision in the process of removing outliers, it is important to correctly determine the mark width reference value. Effectively, the marker structure is designed to correctly determine the width of the marker. If rounded corners are a problem, take a marker shape that is longer in one direction and monitor the center portion that is not affected by the corners.

first embodiment

Referring to Figs. 4A and 4B, the electron beam exposure of the first embodiment will be described. The process shown in FIG. 3A is carried out to form a resist pattern on the silicon substrate, the resist pattern having an opening for the element isolation groove pattern in the semiconductor integrated circuit device region and for the alignment mark pattern. By using the resist pattern as a mask, trenches are etched in the silicon substrate to form steps. Element isolation shallow trenches and alignment marks are formed simultaneously. The step height is generally about 0.3 μm, but it may vary depending on the semiconductor integrated circuit device to be manufactured. An oxide film for burying the trench is formed, and unnecessary oxide film is removed by a chemical mechanical polishing (CMP) process to form a structure as shown in FIG. 3B . By performing several processes, an insulating film as shown in FIG. 3C is formed before forming a contact hole. In order to obtain the alignment signal, the steps need to be restored. Referring to FIG. 3D, a resist pattern exposing the alignment mark and its peripheral region is formed, and the step is exposed by etching the insulating film.

As shown in FIG. 4A , the alignment marks at the upper right portion of five chips located at the center, top, bottom, left and right of the wafer are detected, thereby obtaining mark widths W1, W2, W3, W4 and W5. The average value Wref of these widths is set as a reference value of the wafer mark width. in,

Wref=AVERAGE(W1, W2, W3, W4, W5).

The allowable range R is set in the following range:

ΔW=|W-Wref|,

Values outside R were removed as outliers and not quoted.

For example, the design value of the mark width is set to 2 μm. Assume that the following width data is obtained as the final groove width:

W1x=2.16, W2x=2.15, W3x=2.14, W4x=2.15, W5x=2.15.

In this case a Wxref of 2.15 μm was obtained as the final groove width. Similarly, a Wyref of 2.15 μm is obtained. The allowable range R is set to, for example, 0.10 μm in consideration of process variations and allowable position detection variations, and values ranging from 2.05 μm to 2.25 μm are allowed.

4B is a diagram illustrating the detected mark widths in the order of exposing chips after actually detecting the mark position of each chip, measuring the mark width, and removing the mark width outside the allowable range. Those abnormal detection values as shown in Fig. 3E can be avoided.

Electron beam exposure also requires focus adjustment. Before the first exposure position alignment is performed, the alignment mark is scanned with the electron beam and the reflected electron signal is monitored. For example, by changing the focal length of the objective lens, the focusing condition where the maximum peak intensity of the differential waveform appears is selected. In this way the best focal length can be determined. During this process, mark widths can be sampled, and preliminary sampling and mark width measurements can be shared.

In some cases, due to the distribution of etching and chemical mechanical polishing in semiconductor processing, etc., the width of marks formed in layers below the workpiece layer will have some distribution in the in-plane wafer.

The distribution of alignment mark widths in a wafer is illustrated in Figures 5A and 5B. Fig. 5A is a plan view, and Fig. 5B illustrates width distribution along a certain direction. In order to remove abnormal values with high precision, it is necessary to correctly determine the mark width reference value. If the same reference value and tolerance range are used for the entire wafer or a wider area of the wafer, and if the tolerance range is narrow, many outliers will be detected and the number of samples allowed will be reduced. If the allowable range is expanded, even abnormal samples are used as normal samples. Both of these situations are inappropriate for high-precision outlier removal.

If the distribution has a predetermined tendency, by using the reference value of the mark width expressed as a function of position, outliers can be detected with high accuracy. Many distribution trends, as shown in Figure 5A, have a width distribution that is concentric with respect to the center of the wafer.

In the case where the mark width is distributed in the in-plane wafer due to some problems in the process of forming the mark in the layer below the workpiece layer, it is effective to change the Reference values in the wafer to remove outliers with high precision.

If the mark width distribution varies in the shape of a parabola, it is useful to express this distribution by a quadratic equation, for example W=ar ² +br+c (r is the distance from the center, r ² =X ² +y ² ) . In the example shown in FIG. 5B, the curve parameters are approximately a=0.001, c=2.1. The reference width for each position of the wafer is determined by this equation, and outliers can be removed with high precision.

The function of mark width with respect to mark position is not limited to this equation. Depending on the distribution, the in-plane distribution can be approximated as a linear equation involving polynomials, a quadratic equation other than the quadratic equation described above, a cubic or higher order equation.

In electron beam exposure, generally in a unit group including a chip unit, a chip pillar unit, or the like, the position of each alignment mark is detected, and exposure is performed after alignment. In this case, after detecting the positions of the alignment marks in one group, calculate a reference width such as an average width, and remove outliers with a large offset, or measure the width again to exclude outlier data. In this way, positional misalignment can be avoided.

second embodiment

Figure 6A illustrates an example of an alignment mark layout in a wafer. Alignment marks 9 are respectively provided near the four corners of each chip 8 in the wafer.

Fig. 6B is an enlarged view of a chip area. Alignment mark 9 is provided at a position not overlapping scribe line 10 . Alignment marks can also overlap the scribed line if no inspection is required after scribing with the scriber. As shown in FIG. 6A, four alignment marks are provided near each side of the chip except the outermost side. These labels are assigned to two adjacent chips.

In a unit group including a chip unit, a chip pillar unit, and the like, alignment mark detection, alignment, and exposure are repeatedly performed. In this case, the mark widths W1, W2, W3, W4 of each chip or the mark widths of each group W1(i), W2(i), W3(i), W4(i) obtained at one time are used for Determine the reference mark width Wref, for example,

Wref=AVERAGE(W1, W2, W3, W4),

Or Wref=AVERAGEΣ(W1(i), W2(i), W3(i), W4(i)).

The allowable range R of ΔW is set as

ΔW=|W-Wref|,

And outliers outside the tolerance range are removed and not referenced. Other points are similar to the first embodiment. Similar to the first embodiment, false detection can be avoided.

This embodiment requires no preprocessing and can be used even with large local variations in mark width in the in-plane wafer. However, there is a disadvantage that if the reference width is determined in chip units, the outlier removal accuracy cannot be too high due to the small number of reference points used to obtain the average value. If outliers need to be removed with high precision, it is preferable to group several chips to increase the number of reference points used to obtain a reference width, and then perform alignment mark detection, alignment, and exposure.

At position detection points along the X and Y directions, the same value can be used as the marker width. If the detection widths in the X and Y directions measured at each position detection point exceed a predetermined difference, these values are removed, or the width is measured again to avoid using outlier data. In this way positional misalignment can be avoided. Even in the mark forming layer, the size of the marks distributed in the in-plane wafer is large, and the effect on the mark distribution is small, and this embodiment is particularly effective for such a case.

third embodiment

As shown in FIG. 7, the alignment mark at each position is composed of a pair of X-direction mark MX and Y-direction mark MY. That is, each alignment mark 9 as shown in FIG. 6A is composed of two marks MX and MY. The widths of the marks MX and MY in the X direction and the Y direction are the same.

A pair of marks in the X and Y directions are placed in an area considered to have the same processing conditions, and the marks in the X and Y directions are scanned alternately. The abnormal value is judged by the difference Δ=Wx−Wy between the X-direction mark width Wx and the Y-direction mark width Wy.

For example, the design value of the mark width is set to 2 μm, and the tolerance value is set to 0.10 μm. If the mark width detection results of marks 1, 2, . From this, it is judged that this is an erroneous detection, and these values are removed from the position detection information. For example, if the remeasured width is Wx2 = 2.10 μm, this mark width is used as position detection information. With this process, large positional misalignments can be avoided. The alignment mark can also be a square, and the difference in the width of the mark in the X and Y directions is obtained.

The obtained width is used as the first level difference between positions. The difference between the widths in the X and Y directions is the second level difference between positions. The second-level difference is not limited to the difference between widths along different directions, and other differences can also be used.

Fourth embodiment

As shown in FIG. 8, at each measurement point, a plurality of alignment marks are arranged in the same direction. For example, alignment marks MX1 and MX2 that are long in the Y direction are juxtaposed along the X direction. The center portions of the marks MX1 and MX2 are obtained, and the mark width is set as the distance between the centers of the two alignment marks MX1 and MX2 along the width direction. By using the marker width, outliers can be effectively removed. The distance between marks is hardly affected by the processing steps, so a value close to the design value can be obtained. Therefore, even if the design value itself is used as a reference value, outliers can be removed with high precision, and since there is no need to set a reference value for each wafer or an area within a wafer, outliers can be removed with high efficiency. Effectively, if a plurality of mark widths are set to the same width, there will be no difference in the distance between the respective patterns.

10A to 10G are cross-sectional views illustrating main processes of a semiconductor device manufacturing method including the alignment process of any of the above-described embodiments. The left side of each figure shows the semiconductor area and the right side shows the alignment mark area.

As shown in FIG. 10A, the surface of the silicon substrate 1 is thermally oxidized to form a buffer oxide film 1x, and thereafter, a silicon nitride film 55 is deposited on the buffer oxide film 1x by low pressure (LP) chemical vapor deposition (CVD). . The silicon nitride film 55 functions as a barrier layer at the time of subsequent chemical mechanical polishing (CMP). On the silicon nitride film 55, a resist pattern RP1 having openings for exposing isolation trenches and alignment marks is formed. The resist pattern RP1 is formed by optical exposure or electron beam exposure. By using the resist pattern RP1 as a mask, the silicon nitride film 55 is subjected to reactive ion etching (RIE) using an etching gas containing fluorine, and then the silicon substrate 1 is subjected to reactive ion etching (RIE) by replacing the gas with an etching gas containing chlorine. ). The etching depth of the silicon substrate is, for example, about 300 nm. The resist pattern RP1 is then removed. This process corresponds to the process shown in Fig. 3A. Isolation trenches (ST) are formed on each chip area, and grooves as alignment marks (AM) are formed on each chip peripheral area. For example, the minimum width of a shallow trench (ST) is about 200 nm, and the mark width of an alignment mark is about 1 to 5 μm, but the mark width may vary depending on the design of a semiconductor integrated circuit device.

As shown in FIG. 10B , a silicon dioxide film 6 is deposited by high-density plasma (HDP) chemical vapor deposition (CVD) to bury the shallow trench (ST). At the same time, the alignment marks (AM) are also buried by the silicon dioxide film 6 . The excess portion of the silicon dioxide film is removed by chemical mechanical polishing (CMP), so that the surface of the substrate is flattened. The exposed silicon nitride film 55 is removed with hot phosphoric acid, and the buffer oxide film 1x is etched and removed with diluted hydrofluoric acid. Shallow trench isolation (STI) and alignment mark (AM) buried by the oxide film are thus formed. This process corresponds to the process shown in Fig. 3B.

As shown in FIG. 10C, by using a resist mask, ions are implanted into the element region to form a p-type well (PW) and an n-type well (NW). B and the like are used for p-type impurities, and P and the like are used for n-type impurities. The silicon dioxide film on the surface of the silicon substrate is removed, and thermal oxidation is performed to grow a new gate oxide film (Gox) having a thickness of, for example, 2 nm or less. If necessary, nitrogen is introduced into the gate oxide film, and/or a high dielectric constant layer is stacked on the gate oxide film. On the gate oxide film (Gox), a polysilicon film is deposited by chemical vapor deposition (CVD), and a resist pattern is formed on the polysilicon film. The resist pattern can be a pitched optical resist pattern or an e-beam resist pattern. By using the resist pattern as a mask, the polysilicon layer is etched to form a gate electrode (G). The resist pattern is subsequently removed.

By using a region-separated resist pattern, n-type impurity ions, such as P ions, are implanted into the p-type well (PW) to dope impurities into the gate electrode (G), and form source/drain on both sides of the gate electrode pole extension (EX). For an n-type well (NW), p-type impurity ions such as B ions are implanted. An insulating film such as a silicon dioxide film is deposited, and reactive ion etching (RIE) is performed to form a sidewall insulating film (SW) on the sidewall of the gate electrode (G). Then, n-type impurity ions are implanted into the p-type well (PW), and p-type impurity ions are implanted into the n-type well (NW) to form high-concentration source/drain regions (S/D). After forming the MOS transistor structure in this way, an interlayer insulating film 7 made of phosphosilicate glass (PSG) or the like is deposited by chemical vapor deposition (CVD). The surface of the interlayer insulating film is flattened by chemical mechanical polishing (CMP). This state corresponds to the state shown in Fig. 3C. Although only n-channel MOS transistors formed in the p-type well (PW) are shown, p-channel MOS transistors are also formed in the n-type well (NW). A contact hole exposing a high-concentration source/drain region (S/D) in the MOS transistor is then formed by etching. This etching requires high precision and is performed by electron beam exposure for positional alignment using alignment marks.

As shown in FIG. 10D , a resist pattern RP2 is formed to have an opening exposing a region including an alignment mark (AM). The entire element area is covered with a resist pattern. The resist pattern has, for example, an accuracy of about 0.5 μm, which does not require high precision. The resist pattern can thus be formed by performing optical exposure using an optical coarse alignment mechanism installed in an electron beam exposure system.

As shown in FIG. 10E, the interlayer insulating film 7 exposed at the opening is subjected to reactive ion etching (RIE) using an etching gas containing fluorine, and then the silicon dioxide film 6 buried in the alignment mark (AM) trench is subjected to reactive ion etching (RIE). Reactive ion etching (RIE) is performed. The resist pattern RP2 is then removed. The steps of the silicon substrate are exposed in the alignment marks (AM).

As shown in FIG. 10F , a resist film for electron beam exposure is coated, and an alignment mark is detected using an electron beam. The resist film is almost transparent to the electron beam, so alignment mark steps can be easily detected. After establishing high-precision alignment using an electron beam, in order to form a contact hole, electron beam exposure and development are performed to form a resist pattern RP3. By using the resist pattern RP3 as an etching mask, the interlayer insulating film 7 is subjected to reactive ion etching (RIE) using a fluorine-containing etching gas. Contact holes reaching the source/drain regions (S/D) are thus formed. The alignment mark region remains covered with the resist pattern RP3. The resist pattern RP is then removed.

Subsequently, as shown in FIG. 10G , a barrier film such as a TiN film is formed, and then a tungsten film is deposited by chemical vapor deposition (CVD) using WF ₆ to bury the contact hole. The unnecessary metal film deposited on the interlayer insulating film 7 is removed by chemical mechanical polishing (CMP), thereby forming a conductive plug (PL) that buries the contact hole.

Subsequently, multilayer wiring is formed using a usual process. The alignment mark used in the multilayer wiring forming process may be a step of an alignment mark formed in a substrate and exposed again, or a step of an alignment mark formed simultaneously with a new wiring.

11A to 11D illustrate the formation process of via holes for forming multilayer wiring. The process shown in FIGS. 10A to 10G forms an n-channel MOS transistor (NMOS), a p-channel MOS transistor (PMOS), covers the transistors with an interlayer insulating film 7, and forms conductive plugs for source/drain regions S/D (PL).

As shown in FIG. 11A, a metal wiring layer 51 made of aluminum or the like is deposited on the semiconductor wafer. A resist pattern RP4 is formed on the metal wiring layer 51 for patterning wiring and alignment marks. The resist pattern RP4 may be an optical resist, or an electron beam resist. If necessary, the alignment marks as shown in Figures 10D and 10E can be restored. By using the resist pattern RP4 as an etching mask, the metal wiring layer 51 is etched to form metal wiring and alignment marks. Inverter wiring is formed in the left area of the figure. Metal patterns 51x shown in the right area of the figure are alignment marks.

As shown in FIG. 11B, an interlayer insulating film 53 made of silicon dioxide or the like is deposited by chemical vapor deposition (CVD) so as to cover the patterned metal wiring layer. Similar to the process shown in FIG. 10D, the resist pattern is formed with an opening exposing the region 54 including the alignment mark, and the interlayer insulating film 53 is etched to expose the alignment mark 51x.

As shown in Fig. 11C, an electron beam resist RP5 is applied. By scanning the electron beam, the alignment mark 51x is detected. As mentioned earlier, a plurality of position information is obtained to calculate the difference. By using the difference, outliers are removed. In accordance with the position information of the alignment mark from which outliers are removed, an opening for forming a via hole reaching the wiring pattern 51 is exposed.

As shown in FIG. 11D , by using the resist pattern RP5 having the opening 56 as an etching mask, the interlayer insulating film 53 is etched to form a via hole 57 . The resist pattern RP5 is then removed, and a conductive layer to bury the via hole is formed. The conductive layer deposited on the interlayer insulating film 53 is removed to form via conductors. This process is similar to the process shown in Fig. 10G.

The present invention has been described in conjunction with the above preferred embodiments. However, the present invention is not limited to the above-mentioned embodiments. For example, the gate electrode may be made of polycide, metal or similar material. Instead of using tungsten, the conductive plugs can also be made of silicon, TiN, and similar materials. Around the extended regions of the source/drain, the MOS transistor may have a pocket region of opposite conductivity type. In addition to having a single-layer structure, the electron beam resist film may also have a multi-layer structure. Obviously, those skilled in the art can also make other various modifications, improvements, combinations and such changes to the present invention.

Claims (10)

1. A semiconductor device manufacturing method comprising the steps of:

(a) in a semiconductor wafer, forming an in-chip semiconductor device structure and a plurality of alignment marks respectively;

(b) forming a workpiece layer on the semiconductor wafer;

(c) exposing the alignment mark;

(d) coating an electron beam resist film on the workpiece layer;

(e) scanning the alignment mark with an electron beam, thereby obtaining a plurality of position information on the alignment mark, and obtaining a difference between the plurality of position information;

(f) removing an abnormal value in the position information according to a difference value between the plurality of position information; and

(g) and performing electron beam exposure according to the plurality of position information of the alignment mark from which the abnormal value has been removed.

2. The manufacturing method of a semiconductor device according to claim 1, wherein

The difference between the plurality of position information in the step (e) is a width of each of the alignment marks, which is a first-level difference; and

the step (f) removes the outlier by comparing the width of each alignment mark with a reference value of the width of the alignment mark.

3. The semiconductor device manufacturing method according to claim 1, wherein the difference between the plurality of pieces of positional information in the step (e) is a second-level difference of the plurality of pieces of positional information.

4. The manufacturing method of a semiconductor device according to claim 3, wherein

Obtaining position information of each alignment mark in the X and Y directions in the step (e), a width of each alignment mark in the X and Y directions as a first level error value, and a difference value between the widths in the X and Y directions as a second level difference value; and

in the step (f), the abnormal value is removed by comparing a difference between the widths of each alignment mark in the X and Y directions with a specified value.

5. The manufacturing method of a semiconductor device according to claim 3, wherein

Setting a plurality of alignment marks on each sampling point along the same direction in the step (a);

scanning the plurality of alignment marks on each sampling point along the same direction in the step (e), obtaining a center position of each alignment mark as a first-level difference value, and obtaining a distance between the center positions as a second-level difference value; and

said step (f) removing said outliers by comparing said distance between said center positions to a specified value.

6. The manufacturing method of a semiconductor device according to claim 1, wherein

The step (e) comprises the steps of:

(e-1) pre-scanning the alignment mark at a plurality of points on the in-plane wafer with the electron beam, and determining a reference value according to a plurality of differences between a plurality of position information obtained by the pre-scanning;

(e-2) scanning each alignment mark on the wafer in the plane, and obtaining positional information on each alignment mark and a difference between the positional information;

the step (f) comprises the following steps:

(f-1) obtaining a difference between the reference value and the difference between the position information of each alignment mark, and comparing it with a specified value.

7. The semiconductor device manufacturing method according to claim 6, wherein the step (e-1) uses an average value of widths of the pre-scanned alignment marks as the reference value.

8. The semiconductor device manufacturing method according to claim 6, wherein the step (e-1) represents the reference value as a function of position on the in-plane wafer.

9. A semiconductor device manufacturing method according to claim 1, wherein the steps (e), (f) and (g) are repeatedly performed in a unit group consisting of one to several core pieces.

10. The manufacturing method of a semiconductor device according to claim 1, wherein the step (a) forms a shallow trench isolation region as the semiconductor device structure, and the alignment mark has a structure formed in such a manner that a concave portion is formed in the semiconductor wafer, and the concave portion is buried with an insulator while the shallow trench isolation region is formed, followed by removing the insulator.

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