CN1841661A - Semiconductor manufacture method - Google Patents
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- CN1841661A CN1841661A CN 200510097061 CN200510097061A CN1841661A CN 1841661 A CN1841661 A CN 1841661A CN 200510097061 CN200510097061 CN 200510097061 CN 200510097061 A CN200510097061 A CN 200510097061A CN 1841661 A CN1841661 A CN 1841661A
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Abstract
A semiconductor device manufacture method has the steps of: (a) forming a semiconductor device structure in a chip and alignment marks, respectively in a semiconductor wafer; (b) forming a workpiece layer above the semiconductor wafer; (c) exposing the alignment marks; (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment marks with an electron beam to obtain plural position information on the alignment marks and obtaining differences between the plural position information; (f) removing abnormal values of position information in accordance with the difference between the plural position information; and (g) performing an electron beam exposure in accordance with plural position information of the alignment marks with the abnormal value being removed. An alignment mark detection precision can be improved in electron beam exposure.
Description
The reference of related application
The application based on and require the priority in first to file of Japanese patent application No. 2005-100458 that submitted on March 31st, 2005 and the application number 2005-279561 that submitted on September 27th, 2005, the full content of above-mentioned two applications is incorporated in this as a reference.
Technical field
The present invention relates to a kind of manufacturing method for semiconductor device, particularly a kind of semiconductor making method can utilize electron beam exposure to come processing work by this method.
Background technology
In making the process of conductor integrated circuit device, lithography is used to form a corrosion-resisting pattern by applying a resist layer and it is exposed and develop on workpiece layer.The precision of lithography is the key factor of the precision that influences conductor integrated circuit device, integrated level etc.
Electron beam (EB) exposure has very high resolution, is applicable to the micro-manufactured in the pattern forming process.Electron beam exposure can for example be drawn out very thin pattern on maximum 4 microns the unit are at common several microns.Electron beam exposure allows to carry out alignment correction on very little unit.
If on a chip unit, carry out electron beam exposure, shown in Fig. 9 A, want the alignment mark at place, four angles of detection chip so, with correcting electronic bundle deviation etc., and implement exposure.Calibration substance comprises along the contraction factor Gx on X and the Y direction and Gy, twiddle factor Rx and Ry, trapezoidal factor Hx and Hy and shift factor Ox and Oy.Above-mentioned every can both obtaining by the matrix computations shown in Fig. 9 B, wherein (x, y) and (Δ x, Δ y) be respectively the position coordinate value and distortion (distortion) coordinate figure at each angle in four jiaos of the chips.
Can be by detecting from the electronics that alignment mark reflected, detect the position of the alignment mark that is used for the electron beam exposure aligning.On this basis, Japanese patent application publication No. is that the flat 9-36019 of TOHKEMY has proposed a kind of method that improves alignment mark detection precision, that is, by using a plurality of reflection electronic detectors and amplifier, and the amplification factor that each amplifier is set makes that output intensity is a constant.
Detect the position of alignment mark for high-precision high-speed degree ground, the flat 8-17696 of TOHKEMY proposes to scan the electron beam scanning that is used to detect the alignment mark that is formed by step by first scanning and second, wherein first scanning is the width of scanning greater than this mark width, and second scanning is the limit of only scanning this mark.
Reflection electronic detector and amplifier are used for the detection of reflected electronics.Can not guarantee that the reflection electronic signal has sufficiently high intensity.If noise is superimposed upon on detector, amplifier and other the suchlike instruments, signal waveform will be out of shape so, cause error detection occurring.
If error detection, if no follow-up correction to program, alignment precision will be lowered.
Summary of the invention
The objective of the invention is to improve the precision of alignment mark detection in electron beam exposure.
According to a scheme of the present invention, a kind of manufacturing method for semiconductor device is provided, it comprises following steps: (a) in semiconductor wafer, form semiconductor device structure and a plurality of alignment mark in the chip respectively; (b) on described semiconductor wafer, form workpiece layer; (c) expose described alignment mark; (d) on described workpiece layer, apply the electron beam etchant resist; (e) use the described alignment mark of electron beam scanning, thereby obtain a plurality of positional informations, and obtain the difference between described a plurality of positional information about described alignment mark; (f) according to the exceptional value in the removal of the difference between the described a plurality of positional informations positional information; And, implement electron beam exposure (g) according to a plurality of positional informations of removing exceptional value of described alignment mark.
If noise has been superimposed upon on detector, amplifier or the pertinent instruments, just error detection may appear.By using the difference between a plurality of positional informations, can remove the exceptional value in the positional information.Can prevent the local location mis-alignment that occurs owing to the alignment mark detection mistake.Can avoid the local location skew.Can improve the exposure position precision and further improve the pattern position precision.
The position probing time can be shortened, the quantity of manufacturing process can be reduced thus.
By method of the present invention, it is very fine and highly reliable that conductor integrated circuit device can be made, and output and unfailing performance are enhanced simultaneously.By using the function of electron beam exposure method effectively, can form fine pattern with high accuracy, and can improve the position alignment precision between them.Can improve the output and the reliability of conductor integrated circuit device thus.
Description of drawings
Figure 1A is the schematic diagram of the detection principle of explanation electron beam exposure registration signal; Figure 1B is the oscilloscope schematic diagram that the signal waveform example is shown.
Fig. 2 is the structured flowchart of explanation exposure system.
Fig. 3 A to 3D is the sectional view of the preparatory process of interpret sample; Fig. 3 E is the chart of the measurement result of the above-mentioned sample of demonstration.
Fig. 4 A and 4B are respectively plane graph and the chart of explanation according to the electron beam exposure of the first embodiment of the present invention on semiconductor wafer.
Fig. 5 A and 5B are the plane graph and the curve chart of the improved form of explanation first embodiment.
Fig. 6 A and 6B are the plane graph of the explanation second embodiment of the present invention.
Fig. 7 is the plane graph of the explanation third embodiment of the present invention.
Fig. 8 is the plane graph of the explanation fourth embodiment of the present invention.
Fig. 9 A is the floor map of explanation according to the alignment process of prior art; The equation of Fig. 9 B explanation matrix computations.
Figure 10 A to 10G is the sectional view of explanation according to the master operation of the method, semi-conductor device manufacturing method of embodiment.
Figure 11 A to 11D is the sectional view of explanation according to the master operation of the method, semi-conductor device manufacturing method of embodiment.
Embodiment
In the electron beam exposure operation, the common method that is used to detect registration signal is, analyzes the reflection electronic signal by using the electron beam scanning alignment mark to obtain, and described alignment mark is to be formed by step in the one deck that formed before forming workpiece layer.
The detection principle of registration signal in Figure 1A and the 1B explanation electron beam exposure.
Shown in Figure 1A, utilize electron beam 3 scanning alignment marks 2, this alignment mark 2 is made of the groove in the superficial layer that is formed at silicon substrate 1 (step, recessed part), and with detector 4 detection of reflected electronics.The output of this detector is amplified by an amplifier, and sends to the outside.If an electron beam is focused on the surface of silicon substrate, will die down in the reflection electronic intensity of bottom portion of groove.
Figure 1B is presented at the signal waveform on the oscilloscope.When detecting standard alignment mark, can obtain the signal waveform of below with 500nm shoulder height difference.The high-low level difference of signal is 0.6V.The signal waveform of top is to obtain by the signal waveform of below is done differential calculation.The part that described step changes corresponding to this differential signal waveform.
Fig. 2 is the block diagram of an explanation electron beam exposure system structure.Control work station (WS) 11 by central processing unit formations such as (CPU) is connected to digital control unit (DCTL), photo-electric control unit 18 and machine assembly MS via bus (BL).In digital control unit (DCTL), input signal offers pattern generating/correcting circuit 14 via buffer storage 13, and the collaborative patch memory 15 of this circuit is controlled an analog circuit (AC) together.Described analog circuit (AC) comprises digital to analog converter/amplifier (DAC/AMP) 16, and produces the deviation that analog control signal 17 is adjusted electron beam.These photo-electric control unit 18 control columns 20.
This column 20 is connected to exposure room 30, and in being placed on this exposure room 30 the wafer illumination electron beam on the XY table top 23.This exposure room is assemblied on the antihunting device 24.Be used for detecting from the detector 25 of the electronics of wafer reflection and be arranged on exposure room 30, and provide detection signal to mark detecting unit 26.The output signal of mark detecting unit 26 is that waveform analysis unit 27 is analyzed by mould/number (A/D) transducer, and the analysis result of digital signal form is offered digital control unit (DCTL) and Control work station (WS) 11.
Control work station (WS) 11 and digital control unit (DCTL) pass through photo-electric control unit 18, transmission control unit 31 and table top control unit 32, the position of XY table top 23 in the deviation of electron beam and the exposure room 30 in the control column.External equipment 12 for example display, hard disk and memory can be connected to Control work station (WS) 11.
In alignment function, the mark scan signal is converted to analog signal from 14 outputs of pattern generating/correcting circuit, after being amplified by digital to analog converter/amplifier (DAC/AMP) 16, is applied to arrangement for deflecting.The reflection electronic that produces during electron beam scanning is caught by detector 25, and is labeled detector 26 amplifications.The position coordinates of reflection electronic is that waveform analysis unit 27 calculates by mould/number (A/D) transducer, and is sent to digital control unit (DCTL).According to the coordinate figure that is obtained by this mode, digital control unit (DCTL) is determined exposure position and is implemented pattern exposure.
Generally, the alignment mark on the wafer uses the step in oxide-film, the silicon body etc.The difference in height minimum of this step necessity is 0.3 μ m or darker.Yet, because there is following situation in the restriction of operation, promptly can not obtain the difference in height of above-mentioned necessity, therefore there are not enough signal strength signal intensities, cause letter/make an uproar and reduce than (S/N).Also there is another situation, that is, even the difference in height of mark step is enough, because the detection of mistake still can appear in the noise on digital to analog converter/amplifier (DAC/AMP) 16 and detector 25.Under these situations, the mark coordinate figure is read mistakenly, and the local location skew occurs.Be difficult to overcome offset, because, can not judge which mark coordinate figure is correct only from positional information by the position probing acquisition.
In the conductor integrated circuit device manufacture process, because the pattern rule becomes very fine, the pattern precision is alignment precision particularly, becomes the principal element of a big difficult problem and obstruction conductor integrated circuit device fine patternization and high reliability.In this case, if alignment precision reduces, make output and reliability and also be lowered.Also have following situation, that is, because the influence of trickle noise etc., the local error of registration signal detects and is difficult to be excluded.In the conductor integrated circuit device manufacture process, the reduction of positional precision, the particularly reduction of local location precision in wafer can produce adverse influence to making output and reliability.
For the situation that illustrates that positional precision reduces, the inventor has analyzed from the detection signal of the reflection electronic of detector 25 outputs.
Fig. 3 A to 3D is the sectional view of the preparatory process of interpret sample.In silicon substrate, form shallow channel isolation area as component isolation structure in, form alignment mark groove (recessed part).
As shown in Figure 3A, corrosion-resisting pattern (RP) is formed on the silicon substrate 1, and forms groove 2 by this silicon substrate of etching.After corrosion-resisting pattern (RP) is removed, come deposited oxide film by high-density plasma (HDP) chemical vapor deposition (CVD), in order to bury this groove 2.
Shown in Fig. 3 B, on silicon substrate 1, utilize chemico-mechanical polishing (CMP) to remove unnecessary oxide-film.Oxide-film 6 has been buried in groove 2 inside.Form shallow channel isolation area thus.And formed the alignment mark 2 of burying oxide-film 6.In the conductor integrated circuit device manufacture process, carry out a plurality of different operations thereafter, for example inject in order to the ion that forms trap, inject in order to the ion of adjusting threshold value, the formation of gate insulating film, the formation of gate electrode structure is injected in order to the ion that forms source/drain regions.
Shown in Fig. 3 C, the interlayer dielectric of being made by silicon dioxide etc. 7 is formed on the silicon substrate 1.Also utilize interlayer dielectric 7 to cover buried oxide-film 6.Use alignment mark that contact hole is aimed at, these alignment marks are formed by the operation that forms shallow channel isolation area.Preferably can expose the step (step) of described alignment mark.
Shown in Fig. 3 D, corrosion-resisting pattern is formed has an opening, and this opening exposes the zone that comprises buried oxide-film 6, and the silicon dioxide that is exposed in the opening is etched.Interlayer dielectric 7 and buried oxide-film 6 are etched, thereby the groove 2 that forms as alignment mark is exposed.
When detecting alignment mark, just detect the relative frontier inspection of groove and survey.Obtain the position of mark, as the mean value of the position of groove opposite end.Recess width is designed to for example 2 μ m.If because noise measuring thinks then that to unusual value the mark width of gained also is unusual value.Can easily detect mark width by certification mark.
Fig. 3 E is for showing the chart of the side-play amount that the mark width that obtains by the alignment mark that detects on the wafer is compared with design mark width 2 μ m.Side-play amount on the directions X is by the rhomboid symbolic representation, and the side-play amount on the Y direction is represented by triangle symbol.Though most of detected values are distributed near 0, the detected value that some big side-play amounts are arranged at left end is away from 0 point.If in implementing alignment process, use the distant place detected value of these big side-play amounts or comprise these at a distance the detected value of detected values aim at, it is big that error will become.If obviously unusual detected value is arranged, do not comprise the detected value of detected value at a distance by using so, can aim at normally.
The invention provides a kind of method, promptly, if it is very difficult eliminating noise, then from the detection signal of detector 25, removes exceptional value and correct detection value with high accuracy, thereby improve the productivity of utilizing electron beam exposure to make conductor integrated circuit device with a simple program.
The inventor finds that also the mark width information that obtains from position probing information is effectively to removing exceptional value, and by effectively utilizing mark width information, exceptional value can be removed very efficiently.
Before product exposes, certification mark on the several points on the wafer, and obtain the width of each mark.Determine reference dimension based on these width.When each chip by reality on time, be not used away from the data of reference dimension, perhaps do not adopt abnormal data and certification mark again.In this mode, avoided the position mis-alignment.For example, adopt mean value as the reference value substantially.
In the process of removing exceptional value,, determine that correctly the mark width reference value is very important in order to obtain high accuracy.Effectively, mark structure is designed to correctly to determine the width of mark.If round angle can cause problem, can adopt long in one direction mark shape so, and monitor the core that not influenced by the turning.
First embodiment
With reference to Fig. 4 A and 4B, the electron beam exposure of first embodiment is described.The operation of implementing as shown in Figure 3A forms corrosion-resisting pattern on silicon substrate, this corrosion-resisting pattern has an opening, is used for the element separation groove pattern in conductor integrated circuit device zone and is used for alignment key pattern.By using corrosion-resisting pattern as mask, etched trench is to form step in silicon substrate.Element separation shallow trench and alignment mark are formed simultaneously.Shoulder height is typically about 0.3 μ m, wants manufactured conductor integrated circuit device and changes but it can depend on.The oxide-film of groove is buried in formation, and utilizes chemico-mechanical polishing (CMP) technology to remove unnecessary oxide-film, to form the structure shown in Fig. 3 B.By implementing several operations, before forming contact hole, form the dielectric film as shown in Fig. 3 C.In order to obtain registration signal, need to recover step.Shown in Fig. 3 D, form the corrosion-resisting pattern that exposes this alignment mark and outer peripheral areas thereof, and expose this step by the etching dielectric film.
Shown in Fig. 4 A, detect the alignment mark of five chip upper right portion that are positioned at center wafer, upper and lower, left and right, thereby obtain mark width W1, W2, W3, W4 and W5.The mean value Wref of these width is set to the reference value of wafer mark width.Wherein,
Wref＝AVERAGE(W1，W2，W3，W4，W5)。
Permissible range R is set in following ranges:
ΔW＝|W-Wref|，
What exceed R worthwhilely is removed and is not cited as exceptional value.
For example, the design load of mark width is set at 2 μ m.Suppose to obtain the final recess width of following width data conduct:
W1x＝2.16，W2x＝2.15，W3x＝2.14，W4x＝2.15，W5x＝2.15。
Obtaining Wxref in this case is that 2.15 μ m are as final recess width.Similarly, obtaining Wyref is 2.15 μ m.The position probing of considering process variations and permission changes, and permissible range R is set to for example 0.10 μ m, and scope to be 2.05 μ m all be allowed to the value of 2.25 μ m.
Fig. 4 B for explanation at mark position, the measurement markers width of each chip of actual detected and after removing mark width beyond the permissible range, press the figure of mark width of the sequence detection of exposure chip.Those abnormality detection values shown in Fig. 3 E can be avoided.
Electron beam exposure also needs to focus on to be adjusted.Before carrying out the exposure position aligning first time, use the electron beam scanning alignment mark, and the electronic signal of monitoring reflection.For example, by changing the focal length of object lens, select differentiated waveform the focused condition of peak-peak intensity to occur.Can determine pinpointed focus in this way.In this process, mark width can be sampled, and preliminary sampling and mark width measurement result can be shared.
Under certain situation, because the distribution of etching and chemico-mechanical polishing etc. in the semiconductor technology, the mark width that forms in the layer below workpiece layer planar has some distributions in (in-plane) wafer.
The distribution of alignment mark width in wafer as Fig. 5 A and 5B explanation.Fig. 5 A is a plane graph, and Fig. 5 B explanation is along the width distribution of a certain direction.In order to remove unusual value accurately, need the correct mark width reference value of determining.If the wide region of entire wafer or wafer is used identical reference value and permissible range, and if permissible range very narrow, will detect many exceptional values so and the sample size of allowing will reduce.If permissible range is extended, so in addition unusual sample also be used as normal specimens and use.It all is inappropriate that these two kinds of situations are removed exceptional value for high accuracy.
Have a predetermined trend if distribute, be expressed as the mark width reference value of position function so by use, just can detect exceptional value accurately.Many distribution trends shown in Fig. 5 A, have the width distribution concentric with respect to center wafer.
Planar be distributed with under the situation of mark width in the wafer owing to form some problems in the operation of mark in the layer below workpiece layer, effectively, the polynomial plane, the curved surface that comprise based on sampled result by use wait the reference value that changes in the wafer, to remove exceptional value accurately.
Be the parabolic shape variation if mark width distributes, effectively, represent this distribution, for example W=ar by a quadratic equation
2(r is the distance to the center to+br+c, r
2=X
2+ y
2).In the example shown in Fig. 5 B, this parameter of curve is close to a=0.001, c=2.1.The reference width of each position of wafer is determined by this equation, and exceptional value can be removed accurately.
Mark width is not limited to this equation with respect to the function of mark position.According to different distribution, distribution can be approximately the quadratic equation that comprises polynomial linear equation, be different from above-mentioned quadratic equation, three times or the equation of higher degree more in the plane.
In electron beam exposure, in comprising chip unit, chip column unit or suchlike unit group, detect the position of each alignment mark usually, and after aiming at, implement exposure.In this case, after the position of the alignment mark in detecting a group, calculate for example mean breadth of reference width, and remove the exceptional value of big side-play amount, perhaps measure width once more to get rid of the exceptional value data.In this way, can avoid the position mis-alignment.
Second embodiment
The example of alignment mark layout in Fig. 6 A explanation wafer.Alignment mark 9 is separately positioned near four angles of each chip 8 in the wafer.
Fig. 6 B is the enlarged drawing of a chip area.The alignment mark 9 10 nonoverlapping positions that are set at and rule.If with not needing to check after the scriber line, then alignment mark also can be overlapping with line.As shown in Figure 6A, except outmost limit, four alignment marks are set up near each limit of chip.These marks are assigned to two adjacent chips.
In the unit group that comprises chip unit, chip column unit etc., repeat alignment mark detection, aligning and exposure.In this case, the mark width W1 of each chip that once obtains, W2, W3, the mark width W1 of W4 or each group (i), W2 (i), W3 (i), W4 (i) are used for determining reference marker width W ref, for example,
Wref＝AVERAGE(W1，W2，W3，W4)，
Perhaps Wref=AVERAGE ∑ (W1 (i), W2 (i), W3 (i), W4 (i)).
The permissible range R of Δ W is set to
ΔW＝|W-Wref|，
And the exceptional value that exceeds permissible range is removed and is not cited.Other main points are similar with first embodiment.Be similar to first embodiment, can avoid wrong detection.
Present embodiment does not need preliminary treatment, even the mark width in the plane in the wafer exists very big localized variation also can use.Yet have a shortcoming, if in chip unit, determine reference width since be used for obtaining mean value reference point quantity seldom, exceptional value is removed precision can not be too high.Remove exceptional value if desired accurately, then preferably, several chips are formed a group, be used for obtaining the quantity of the reference point of reference width, carry out alignment mark detection, aligning and exposure then with raising.
At the position detection point on X and Y direction, can use the identical value width that serves as a mark.If exceed predetermined difference at X that each position detection point records and the detection width on the Y direction, then these values are removed, perhaps measure width once more to avoid adopting the exceptional value data.In this mode, can avoid the position mis-alignment.Even in the mark cambium layer, planar the label size that distributes in the wafer is very big, also is very little to the influence of indicia distribution, and present embodiment is effective especially for this situation.
The 3rd embodiment
As shown in Figure 7, the alignment mark in each position is made of a pair of directions X mark MX and Y bearing mark MY.That is to say that each alignment mark 9 as shown in Figure 6A is made of two mark MX and MY.The mark MX of directions X and Y direction and the width of MY are identical.
The mark of a pair of X and Y direction is placed in the zone that is considered to have same process conditions, and the mark of X and Y direction is by mixed sweep.Exceptional value is judged by the difference DELTA=Wx-Wy between directions X mark width Wx and the Y bearing mark width W y.
For example, the design load of mark width is set at 2 μ m, will allows that difference is set at 0.10 μ m.If mark 1,2 ... mark width detection result be Wx1=2.10 μ m, Wy1=2.11 μ m, Wx2=2.40 μ m, Wy2=2.10 μ m ... the XY difference of second mark exceeds allows difference.Judging this thus is an error detection, and these values are removed from position probing information.For example, if the width of Ce Lianging is Wx2=2.10 μ m once more, then this mark width is used as position probing information.Utilize this to handle, can avoid bigger position mis-alignment.Alignment mark also can be a square, and obtains the difference at X and Y bearing mark width.
The width that is obtained is used as the first order difference between the position.In the difference between the width on X and the Y direction is second level difference between the position.Second level difference is not limited to also can use other difference along the difference between the width of different directions.
The 4th embodiment
As shown in Figure 8, at each measurement point, a plurality of alignment marks are disposed on the same direction.For example, place side by side along directions X at Y direction long alignment mark MX1 and MX2.Obtain the core of mark MX1 and MX2, and, mark width is set on the Width distance between the center of two alignment mark MX1 and MX2.By the usage flag width, exceptional value can be removed effectively.Distance between mark is difficult to processed operation influence, therefore can obtain the value near design load.Therefore, even design load itself is used as reference value, exceptional value also can be removed accurately, and because do not need reference value is set in the zone in each wafer or the wafer, so can remove exceptional value expeditiously.Effectively, if a plurality of mark width are set to identical width, then do not have difference between the distance between each pattern.
Figure 10 A is the sectional view of the master operation of explanation method, semi-conductor device manufacturing method to 10G, and it comprises the alignment process of above-mentioned arbitrary embodiment.The left side of each figure shows semiconductor regions, and the right side shows the alignment mark zone.
Shown in Figure 10 A, the surface of silicon substrate 1, thereafter, is deposited on silicon nitride film 55 on this buffer oxide film 1x by low pressure (LP) chemical vapor deposition (CVD) to form buffer oxide film 1x by thermal oxidation.Silicon nitride film 55 plays the effect on barrier layer when chemico-mechanical polishing (CMP) afterwards.On silicon nitride film 55, form corrosion-resisting pattern RP1 with opening, these openings are used to expose isolated groove and alignment mark.Corrosion-resisting pattern RP1 forms by optical exposure or electron beam exposure.By using corrosion-resisting pattern RP1 as mask, use fluorine containing etchant gas that silicon nitride film 55 is carried out reactive ion etching (RIE), then gas is replaced by chloride etching gas, silicon substrate 1 is carried out reactive ion etching (RIE).The etch depth of silicon substrate for example is approximately 300nm.Corrosion-resisting pattern RP1 is removed subsequently.This operation is corresponding with the operation shown in Fig. 3 A.Isolated groove (ST) is formed on each chip area, and is formed on each chip periphery zone as the groove of alignment mark (AM).For example, the minimum widith of shallow trench (ST) is approximately 200nm, and the mark width of alignment mark is approximately 1 to 5 μ m, but mark width can be dependent on the design of conductor integrated circuit device and changes.
Shown in Figure 10 B, come deposition of silica film 6 by high-density plasma (HDP) chemical vapor deposition (CVD), to bury shallow trench (ST).Meanwhile, alignment mark (AM) is also buried by silicon dioxide film 6.Utilize chemico-mechanical polishing (CMP) to remove the redundance of silicon dioxide film, make substrate surface smooth.Utilize hot phosphoric acid to remove the silicon nitride film 55 that exposes, and utilize the hydrofluoric acid etch of dilution and remove buffer oxide film 1x.Therefore formed shallow channel isolation area (STI) and the alignment mark (AM) that oxidized film is buried.This operation is corresponding with operation shown in Fig. 3 B.
Shown in Figure 10 C, by using mask against corrosion, with ion injection element zone, to form p type trap (PW) and n type trap (NW).B etc. are used as p type impurity, and P etc. are used as n type impurity.Silicon dioxide film on the surface of silicon is removed, and carries out thermal oxidation has 2nm for example or littler thickness with growth new grid oxidation film (Gox).If necessary, nitrogen is introduced grid oxidation film, and/or high dielectric constant layer is stacked on the grid oxidation film.On grid oxidation film (Gox), deposit a polysilicon film by chemical vapor deposition (CVD), on this polysilicon film, form corrosion-resisting pattern.Corrosion-resisting pattern can be the optics corrosion-resisting pattern or the electron beam corrosion-resisting pattern of a trim.By using corrosion-resisting pattern as mask, polysilicon layer is etched to form gate electrode (G).Remove corrosion-resisting pattern subsequently.
By the corrosion-resisting pattern that uses the zone to separate, n type foreign ion is the P ion for example, is injected into p type trap (PW), arrives in the gate electrode (G) with impurity, and forms the elongated area (EX) of source/drain in the gate electrode both sides.For n type trap (NW), inject for example B ion of p type foreign ion.Deposit for example dielectric film of silicon dioxide film, and implement reactive ion etching (RIE) on the side wall of gate electrode (G), to form side wall dielectric film (SW).Then, n type foreign ion is injected into p type trap (PW), and p type foreign ion is injected into n type trap (NW), to form high concentration regions and source (S/D).After forming mos transistor structure in this way, deposit the interlayer dielectric of making by phosphosilicate glass (PSG) or materials similar 7 by chemical vapor deposition (CVD).Make the surface of interlayer dielectric become smooth by chemico-mechanical polishing (CMP).This state is corresponding to the state shown in the accompanying drawing 3C.Though only shown the n channel MOS transistor that in p type trap (PW), forms, in n type trap (NW), also formed the p channel MOS transistor.Form the contact hole that exposes MOS transistor middle and high concentration source/drain regions (S/D) by etching subsequently.This etching needs high accuracy, and it is implemented by the electron beam exposure that utilizes alignment mark to carry out position alignment.
Shown in Figure 10 D, corrosion-resisting pattern RP2 forms has an opening, and this opening exposes the zone that comprises alignment mark (AM).Whole element area is covered by corrosion-resisting pattern.This corrosion-resisting pattern has the precision of for example about 0.5 μ m, and it does not need high accuracy.Therefore can be installed in optics coarse alignment mechanism in the electron beam exposure system by use carries out optical exposure and forms this corrosion-resisting pattern.
Shown in Figure 10 E, use fluorine containing etchant gas, the interlayer dielectric 7 that exposes at opening part is carried out reactive ion etching (RIE), then the silicon dioxide film 6 of burying in alignment mark (AM) groove is carried out reactive ion etching (RIE).Corrosion-resisting pattern RP2 is removed subsequently.The step that in alignment mark (AM), exposes silicon substrate.
Shown in Figure 10 F, apply the etchant resist that is used for electron beam exposure, and use electron beam to detect alignment mark.Etchant resist almost is transparent for electron beam, so the alignment mark step can be detected at an easy rate.After the use electron beam is set up high precision alignment,, implement electron beam exposure and development to form corrosion-resisting pattern RP3 in order to form contact hole.By using corrosion-resisting pattern RP3, use fluorine containing etchant gas that interlayer dielectric 7 is carried out reactive ion etching (RIE) as etching mask.Therefore form the contact hole that arrives source/drain regions (S/D).The state that the maintenance of alignment mark zone is covered by corrosion-resisting pattern RP3.Corrosion-resisting pattern RP is removed subsequently.
Subsequently, shown in Figure 10 G, form for example barrier film of TiN film, then by using WF
6Carry out chemical vapor deposition (CVD) and deposit tungsten film to bury contact hole.The unnecessary metal film that is deposited on the interlayer dielectric 7 is removed by chemico-mechanical polishing (CMP), thereby forms the conductive plug (PL) of burying contact hole.
Subsequently, use common operation to form multilayer wiring.Being used for the alignment mark that multilayer wiring forms operation can be, in substrate, form and the step of the alignment mark of exposure once more, or the step of the alignment mark that forms simultaneously with new route.
Figure 11 A to 11D explanation is in order to the formation operation of the through hole of formation multilayer wiring.Operation forms n channel MOS transistor (NMOS) shown in Figure 10 A to 10G, and p channel MOS transistor (PMOS) with interlayer dielectric 7 covering transistors, and is source/drain regions S/D formation conductive plug (PL).
Shown in Figure 11 A, the metal wiring layer of being made by aluminium or similar material 51 is deposited on the semiconductor wafer.Corrosion-resisting pattern RP4 is formed on the metal wiring layer 51, to be used for wiring and alignment key patternization.Corrosion-resisting pattern RP4 can be that optics is against corrosion, or electron beam is against corrosion.If necessary, the alignment mark shown in Figure 10 D and 10E can be resumed.By using corrosion-resisting pattern RP4 as etching mask, metal wiring layer 51 is etched into and forms metal line and alignment mark.Left field at figure forms the inverter wiring.The metal pattern 51x that is presented at the figure right side area is an alignment mark.
Shown in Figure 11 B, the interlayer dielectric of being made by silicon dioxide etc. by chemical vapor deposition (CVD) deposition 53 is on the metal wiring layer that is patterned with covering.Be similar to the operation shown in Figure 10 D, corrosion-resisting pattern is formed with an opening, exposes the zone 54 comprise alignment mark, and interlayer dielectric 53 is etched into and exposes alignment mark 51x.
Shown in Figure 11 C, apply electron beam resist layer RP5.By scanning beam, detect alignment mark 51x.As previously mentioned, obtain a plurality of positional informations and come calculated difference.By using difference, exceptional value is removed.According to the positional information of the alignment mark that is removed exceptional value, the opening that is used to form the through hole that arrives wiring pattern 51 is exposed.
Shown in Figure 11 D, the corrosion-resisting pattern RP5 that has opening 56 by use is as etching mask, and etching interlayer dielectric 53 is to form through hole 57.Corrosion-resisting pattern RP5 is removed subsequently, and forms in order to bury the conductive layer of through hole.The conductive layer that is deposited on the interlayer dielectric 53 is removed, to form via conductor (via conductor).This operation is similar to the operation shown in Figure 10 G.
The present invention has been described in conjunction with above-mentioned preferred embodiment.But the present invention is not limited to the foregoing description.For example, gate electrode can be made by polycrystalline metal silicide, metal or similar material.Except using tungsten, conductive plug can also be by silicon, and similar materials such as TiN are made.Around the elongated area of source/drain, MOS transistor can have the bag district of films of opposite conductivity.Except can having single layer structure, the electron beam etchant resist can also have sandwich construction.Clearly, those skilled in the art can also carry out other various remodeling, improvement, combination and suchlike variation to the present invention.
Claims (10)
1. a method, semi-conductor device manufacturing method comprises the steps:
(a) in semiconductor wafer, form semiconductor device structure and a plurality of alignment mark in the chip respectively;
(b) on described semiconductor wafer, form workpiece layer;
(c) expose described alignment mark;
(d) on described workpiece layer, apply the electron beam etchant resist;
(e) utilize the described alignment mark of electron beam scanning, thereby obtain a plurality of positional informations, and obtain the difference between described a plurality of positional information about described alignment mark;
(f) according to the exceptional value in the removal of the difference between the described a plurality of positional informations positional information; And
(g) according to a plurality of positional informations of removing exceptional value of described alignment mark, implement electron beam exposure.
2. method, semi-conductor device manufacturing method according to claim 1, wherein
Difference described in the described step (e) between a plurality of positional informations is the width of each described alignment mark, and this width is a first order difference; And
Pass through in the described step (f) to compare the width of each alignment mark and the reference value of described alignment mark width, remove described exceptional value.
3. method, semi-conductor device manufacturing method according to claim 1, the difference described in the wherein said step (e) between a plurality of positional informations are the second level difference of described a plurality of positional informations.
4. method, semi-conductor device manufacturing method according to claim 3, wherein
Obtain the positional information of each alignment mark on X and Y direction in the described step (e), the width of each alignment mark is as first order error amount on X and Y direction, and the difference between the width of X and Y direction is as second level difference; And
In the described step (f), difference and designated value between the X by each alignment mark relatively and the width of Y direction are removed described exceptional value.
5. method, semi-conductor device manufacturing method according to claim 3, wherein
On unidirectional each sampled point, a plurality of alignment marks are being set in the described step (a);
The described a plurality of alignment marks of scanning on described unidirectional each sampled point in the described step (e), the center that obtains each alignment mark are as first order difference, and obtain distance between the center as second level difference; And
By described distance and designated value between more described center, remove described exceptional value in the described step (f).
6. method, semi-conductor device manufacturing method according to claim 1, wherein
Described step (e) comprises following steps:
(e-1) utilize electron beam that the alignment mark at a plurality of somes place on the wafer in the plane is carried out prescan, and determine reference value according to a plurality of differences between a plurality of positional informations that obtain by prescan;
(e-2) each alignment mark on the wafer in the plane of scanning motion, and obtain about the positional information of each alignment mark and the difference between positional information;
Described step (f) comprises following steps:
(f-1) obtain difference between the difference between the positional information of reference value and each alignment mark, and itself and designated value are compared.
7. method, semi-conductor device manufacturing method according to claim 6, the width mean value of the alignment mark of the described prescan of wherein said step (e-1) use is as described reference value.
8. method, semi-conductor device manufacturing method according to claim 6, wherein said step (e-1) is expressed as the position function on the wafer in the plane with described reference value.
9. method, semi-conductor device manufacturing method according to claim 1, wherein said step (e) is to repeat in the unit group that is made of one to several chip (f) and (g).
10. method, semi-conductor device manufacturing method according to claim 1, wherein said step (a) forms shallow channel isolation area as described semiconductor device structure, and described alignment mark has the structure that following mode forms, promptly, in described semiconductor wafer, form recessed portion, and when forming described shallow ridges shape isolated area, utilize insulator to bury the female part, remove this insulator subsequently.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102338988A (en) * | 2010-07-19 | 2012-02-01 | 无锡职业技术学院 | Method for improving overlay test accuracy |
| CN101900946B (en) * | 2009-05-27 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Detection method and system of zero mark exposure |
| CN102856164A (en) * | 2012-09-07 | 2013-01-02 | 无锡华润上华科技有限公司 | Method for improving clearness of alignment marks |
| CN103325748A (en) * | 2012-03-21 | 2013-09-25 | 株式会社东芝 | Semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000114150A (en) * | 1998-10-08 | 2000-04-21 | Sony Corp | Alignment method and overlay measuring method in lithography process, aligner, and overlay measuring instrument |
| US6194287B1 (en) * | 1999-04-02 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Shallow trench isolation (STI) method with reproducible alignment registration |
| JP2001052991A (en) * | 1999-08-13 | 2001-02-23 | Nec Corp | Electron beam exposure method and manufacture of semiconductor device |
| JP2003224057A (en) * | 2002-01-30 | 2003-08-08 | Hitachi Ltd | Method of manufacturing semiconductor device |
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2005
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101900946B (en) * | 2009-05-27 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Detection method and system of zero mark exposure |
| CN102338988A (en) * | 2010-07-19 | 2012-02-01 | 无锡职业技术学院 | Method for improving overlay test accuracy |
| CN103325748A (en) * | 2012-03-21 | 2013-09-25 | 株式会社东芝 | Semiconductor device |
| CN102856164A (en) * | 2012-09-07 | 2013-01-02 | 无锡华润上华科技有限公司 | Method for improving clearness of alignment marks |
| CN102856164B (en) * | 2012-09-07 | 2016-04-13 | 无锡华润上华科技有限公司 | A kind of method improving alignment mark definition |
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