JP6362827B2 - Alignment measuring apparatus and alignment measuring method - Google Patents

Description

  The present invention relates to an alignment measuring apparatus and an alignment measuring method for measuring alignment between patterns on a plurality of layers formed on a substrate.

  In recent years, semiconductor devices have been miniaturized year by year to meet Moore's Law, and the device size has come to fall below 20 nm. This tendency is said to continue up to about 6 nm. A semiconductor device has a structure in which after forming a transistor as an active device on a silicon substrate, an insulator thin film and a conductor thin film are repeatedly sandwiched in order to form wiring for operating the transistor. Some state-of-the-art semiconductor devices have dozens of layers with different thicknesses and materials. Since each layer is a wiring, it can function as a semiconductor device only when the positional relationship between the layers is properly maintained and electrically connected. In the state-of-the-art device, the relative positional relationship between layers needs to be maintained with an accuracy of several nanometers.

  The lowermost layer is a silicon substrate, and transistors are formed by ion implantation and diffusion processes. Since the transistor is a three-terminal element, it has a gate for applying a control voltage to the transistor, a source for draining current, and a drain, which are connected to the first wiring layer through contact holes. The contact hole is filled with a conductive material called a plug. In general, the plug is made of a high melting point metal material so that it can withstand a subsequent high-temperature heat treatment, and is made of tungsten, WSi, polysilicon, aluminum, or copper.

  Individual transistors are completed in the first wiring layer. In the second wiring layer, short wiring is performed so that each transistor terminal is connected to form an inverter, a simple amplifier, or the like. In the third wiring layer, a unit logic circuit is configured by connecting the above elements. In the fourth wiring layer, functional circuit blocks are configured by connecting unit logic circuits. As the wiring layer goes up in this way, a more complicated logic circuit or the like is configured, and a semiconductor device is finally formed.

  State-of-the-art semiconductor devices perform ultra-high speed operation on the order of GHz. The operation speed is determined by a speed that satisfies the gate capacitance of the transistor. Since high speed requires a large current supply, there are many wiring layers only for supplying power.

  Recently, copper wiring is often used in place of conventional aluminum wiring because of its high resistance to electromigration. These wiring layers made of different materials are produced by a damascene process using plating or CMP. In a flash memory, a CCD, or the like, there are cases where transistors having different operating voltages exist on the same chip, and therefore there may be a wiring layer for each power supply voltage.

  Since the new layer is a wiring having a different pattern, there is a patterning process such as photolithography every time a new layer is formed.

  Conventionally, in order to align patterns (wiring, etc.) between layers, a scribe line is provided with a box-in-box pattern for alignment that is unrelated to the circuit. Alignment has been done.

  However, the above-described method of performing image alignment using a conventional CCD camera or the like has a problem that the pattern size for alignment takes a very large area of 10 microns or more.

  In addition, since the minimum feature size of the device has become very small, such as 20 nm or less, the conventional optical method such as the asymmetry error of the target pattern has too much error in alignment, and the semiconductor device cannot be made accurately. The problem that came to be reported has been reported.

  The present invention provides an apparatus and method for solving the above problems and realizing accurate inter-layer alignment of semiconductor devices that have been miniaturized.

  Therefore, the present invention provides an alignment measuring apparatus that measures alignment between patterns on a plurality of layers formed on a substrate, and places the substrate at the position of a pattern to be aligned among the plurality of layers formed on the substrate. A moving means for moving and positioning, a scanning means for scanning while irradiating a finely focused electron beam in the positioned state, and a scanning means for irradiating the electron beam with the scanning means and formed on the substrate An upper layer image acquisition unit that acquires an image of an upper layer pattern of a plurality of layers, and an image of a lower layer pattern of the plurality of layers formed on the substrate while being scanned while being irradiated with an electron beam by the scanning unit A lower layer image acquisition means for acquiring the image and a measurement means for measuring the amount of positional deviation between the acquired upper layer pattern and the lower layer pattern. It is configured.

  At this time, as an image of the lower layer pattern, a substrate current flowing in the substrate when scanning is performed while irradiating a finely focused electron beam, and an image of the lower layer pattern is acquired.

  Also, as an image of the upper layer pattern, secondary electrons emitted from the upper layer pattern or reflected electrons reflected by the upper layer pattern are detected when scanning while irradiating a narrowly focused electron beam, and the upper layer pattern is detected. I try to get an image.

  In addition, the amount of displacement between the acquired upper layer pattern and lower layer pattern is measured, and compared with a preset tolerance value, the alignment is good when it is within the tolerance value, and the alignment is judged as bad when it is outside the tolerance value Like to do.

  Further, when it is determined that the alignment is defective, the exposed / developed resist on the substrate is peeled off, and the resist coating, exposure, and development are instructed again.

  Also, measure the size of the upper layer pattern and the lower layer pattern and compare each with the design value to calculate the reduction rate of the exposure device between the upper layer pattern and the lower layer pattern, or calculate the error of the reduction rate of both Like to do.

  Also, the position of the lower layer image of the bottom of the contact or via hole acquired from the bottom of the contact or via hole pattern as the lower layer pattern and the upper layer image of the pattern arranged so as to be in contact with the contact or via hole as the upper layer pattern The relationship is measured, and the quality of the contact hole or via hole process is determined based on a preset allowable value.

  Further, the amount of displacement between the upper layer pattern and the lower layer pattern is measured in each shot area exposed on the substrate by the exposure apparatus.

  Further, the acceleration voltage of the electron beam is varied to acquire an image of the lower layer pattern having the best contrast.

  The present invention relates to an alignment measuring apparatus that measures alignment between patterns on a plurality of layers formed on a substrate, and positions of an upper layer pattern and a lower layer pattern to be aligned among the plurality of layers formed on the substrate. By measuring the deviation, it is possible to quickly and reliably measure the amount of positional deviation between patterns on a plurality of layers.

  For example, the size and direction of positional deviation between the resist structure and the lower wiring buried under the resist structure (pattern) immediately after development can be quantitatively grasped in a non-destructive manner. Since the electron energy used is low and the current is small, the transistor is not damaged.

  By providing the output data of the measuring apparatus of the present invention for adjusting the alignment amount of the exposure apparatus during re-exposure, it becomes possible to obtain a correctly aligned exposure result on the entire wafer surface. By such rework, the number of discarded wafers is reduced, the yield of semiconductor devices is increased, the efficiency of the semiconductor factory is increased, and more profits can be made.

  In the SAC process, it can be used for optimizing process conditions so that the cause of leakage can be identified and prevented. It leads to yield improvement and has the effect of improving profits.

  In the multilayer wiring process, the above-described effects can be obtained. The wiring layout margin can be accurately grasped, and the manufacturing yield of semiconductor devices can be improved through process improvement and circuit wiring design improvement.

  Since it is not necessary to place a large pattern for measurement as in the conventional optical apparatus, it is possible to increase the device manufacturing area. Since it is possible to directly measure the alignment state of the actually operating semiconductor element, it is easy to correlate with the finally obtained device electrical characteristics, and the process improvement can be performed efficiently. This is particularly effective for leak detection in SAC.

  The present invention relates to an alignment measuring apparatus that measures alignment between patterns on a plurality of layers formed on a substrate, and positions of an upper layer pattern and a lower layer pattern to be aligned among the plurality of layers formed on the substrate. By measuring the deviation, we realized that the amount of positional deviation between patterns on multiple layers can be measured quickly and reliably.

  FIG. 1 shows a block diagram of an embodiment of the present invention. FIG. 1 discloses a means for realizing interlayer alignment using a substrate current generated by irradiating a sample 9 with an electron beam.

  In FIG. 1, an electron gun 1 generates an electron beam 3, which is a so-called thermal emitter in which a cathode made of, for example, W or LaB6 is heated, a ZrO / W TFE emitter, or a cold cathode such as W or CNT. Various emitters such as cathode emitters known in the world are used. There is a high voltage power source 12 for applying a high voltage to the electron gun 1, and an electron beam 3 having a desired energy (energy corresponding to an acceleration voltage) can be taken out.

  The high-voltage power supply 12 is a known one that generates and applies a high voltage for accelerating electrons emitted from the electron gun 1.

  The electron beam column 2 focuses the electron beam 3 emitted from the electron gun 1 with a focusing lens, and further scans the focused electron beam 3 with a scanning coil in a state where the electron beam 3 is narrowed with the objective lens on the surface of the sample 9. It is a publicly known thing.

  The electron beam 3 is an electron beam emitted from the electron gun 1.

  The electron detector 4 detects and amplifies secondary electrons and reflected backscattered electrons that are emitted while scanning the surface of the sample 9 while scanning the surface with a narrowly focused electron beam 3. An electronic detection device such as MCP.

  The vacuum chamber 5 is a container for holding the sample 9, the XY stage 6 and the like in a vacuum, and is evacuated to a vacuum by a vacuum pump 11.

  The XY stage 6 precisely moves the sample 9 (for example, a wafer) in the X and Y directions, and is precisely controlled by the laser distance measuring device 10.

  The stage controller 7 controls the movement of the XY stage 6.

  The plate 8 is for holding the sample 9 in an insulated state on the XY stage 6 and for measuring the current (substrate current) when the electron beam 3 flows through the sample 9. This is for amplifying a minute current by connecting to the current amplifier 22.

  A sample 9 is a sample to be subjected to plane scanning with a finely focused electron beam 3 to acquire an image of an upper layer pattern and an image of a lower layer pattern in a plurality of layers and measure the positioning of the pattern. For example, a wafer 91 or the like It is.

  The laser distance measuring device 10 is a known device that accurately measures the movement of the XY stage 6.

  The vacuum pump 11 exhausts the vacuum chamber (sample chamber) 5 to a vacuum.

  The current amplifiers 21 and 22 are amplifiers (preamplifiers) that amplify a minute current.

  The AD 23 AD-converts the image signals (upper and lower pattern image signals) amplified by the current amplifiers 21 and 22 into dental signals.

  The PC 24 is a personal computer that performs various types of control and processing according to a program. Here, the PC 24 includes a moving unit 25, a scanning unit 26, an image acquiring unit 27, a measuring unit 28, an evaluating unit 29, and the like. is there.

  The moving means 25 controls the stage control device 7 to control the movement of the XY stage 6 to a predetermined position on the basis of a signal from the laser distance measuring device 10, and is to be measured based on CAD data. The movement of the sample (wafer) 8 is controlled so that the electron beam 3 narrowly focused at a predetermined position is scanned.

  The scanning unit 26 controls the plane scanning of the predetermined area with the electron beam 3 in a state where the electron beam 3 narrowed to a predetermined position of the sample (wafer) 9 is positioned by the moving unit 25.

  The image acquisition unit 27 detects a secondary electron emitted when a predetermined region of the sample 9 is planarly scanned by the scanning unit 26 and a secondary current based on a current flowing through the plate 8 (substrate). An electronic image (upper layer image), a reflected electronic image (upper layer image), a substrate current image (lower layer image), and the like are acquired and stored (described later).

  The measuring unit 28 compares the upper layer image (secondary electron image, reflected electron image) acquired by the image acquiring unit 27 with the lower layer image (substrate current image), and a positional deviation between patterns, a pattern reduction rate, etc. Is measured (described later).

  The evaluation means 29 evaluates good or bad based on the difference from a preset value based on the position between patterns measured by the measuring means 28, the reduction rate of the pattern, etc. ( Will be described later).

  The measurement data accumulating unit 30 accumulates the measurement values (measurement data such as a position between patterns and a pattern reduction ratio) measured by the measurement unit 28 (described later).

  The CAD data storage means 31 stores CAD data that is design data.

  The exposure device 32 is a device that sequentially exposes a pattern on a wafer (sample 9). A plurality of patterns each having a pattern on the substrate by repeatedly performing film formation (forming a conductive or insulating film) on the substrate (or an already formed pattern) using an exposure apparatus, resist coating, exposure, development, etching, etc. It is the exposure apparatus for forming the layer (layer).

  The operation of the above configuration will be briefly described.

  (1) The electron beam 3 generated by the electron gun 1 is accelerated to the set energy, adjusted to a desired current amount by a condenser lens or the like, and converged to a desired spot size by the objective lens and then sample 9 Is irradiated. When the sample 9 is irradiated with the electron beam 3, secondary electrons and reflected electrons depending on the structure and material of the sample 9 are generated. In the present invention, the secondary electrons and reflected electrons generated on the surface of the sample 9 are detected and converted into electric signals, and the substrate current flowing in the plate 8 on which the sample 9 is generated is measured at the same time. Since there are various delays in the actual measurement system, the time delay is synchronized using the time shift function.

  (2) The secondary electron signal or the reflected electron signal is amplified by an electron detection device 4 which is an MCP, an electron multiplier, a scintillator photomultiplier or a semiconductor electron amplifier to be an electric signal.

  (3) On the other hand, when the sample 9 is a conductor sample, a substrate current is formed by bringing the plate 8 into contact with the conductive sample 9 to form a circuit for guiding the substrate current. 23) and converted into an electric signal. When the sample 9 is not conductive, the plate 8 that is a large electrode is brought into contact with the back surface, side surface, and the like of the sample 9 to form a capacitance as large as possible, and the substrate current is guided to the current amplifier 22. Since the substrate current amount measured in the present invention is a signal from pA to nA level, the substrate current can be measured substantially without loss by providing an electric capacity between the sample 9 and the sample 9. If necessary, the electron beam 3 to be irradiated may be modulated during one pixel irradiation period, for example, alternating current, intermittent, or pulsed. In this way, a signal can be sufficiently guided to the current amplifier 22 by forming a very small electric capacity. In this case, the obtained substrate current signal is rectified or subjected to absolute value processing and then converted to a luminance signal by performing appropriate offset processing. The substrate current is very small and wide, so it is vulnerable to noise. It is desirable to provide a minute current-voltage conversion amplifier (current amplifier 22) that also serves as impedance conversion in the vacuum chamber 5 having a shielding effect. Fully shield when placed in air. Cooling the current amplifier 22 has the effect of reducing noise.

  (4) Secondary electrons, reflected electrons, and substrate current signals are converted into digital signals by a high-speed analog-digital converter (AD23) and then input to the PC 23. Of course, an AD converter built in the PC 23 may be used. It has a function of shifting the time axis of the acquired signal by hardware or software so that each signal timing satisfies simultaneity.

  (5) On the other hand, at the position of the sample 9 or the electron beam landing point when the scanning amplitude of the electron beam 3 is 0, laser distance measurement is performed by the laser distance measuring device 10 using a reflecting mirror fixed to the XY stage 6. Is called. Both X and Y axes are measured in real time on the order of MHz, and the absolute position can be known with an accuracy of 0.03 nm, for example. These data are also input to the PC 24 for processing the aforementioned image data.

  (6) The absolute position of the landing point of the electron beam 4 on the sample 9 is expressed as a value obtained by adding the amplitude of the electron beam 3 to the value of the laser distance measuring device 10. The position in the image obtained through the above means can always be converted to the absolute position of the sample 9. The sample 9 is placed on the XY stage 6 and can be accurately controlled to be moved to an arbitrary position by inputting movement information to the stage controller 7.

  FIG. 2 is a block diagram showing another embodiment of the present invention. FIG. 2 shows an example in which the sample 9 is arranged in the atmosphere (or in a pressure close to the atmosphere). Here, since it is the same as FIG. 1 except that the diaphragm 90 is provided in FIG. 2 and the inside of the vacuum chamber 5 in FIG.

  In FIG. 2, since the substrate current is used for image formation in the present invention, secondary electrons and reflected electrons generated by the electron beam 3 irradiated to the sample 9 reach a column where the electron detector 41 is located as in a normal SEM. You don't have to. Since the substrate current image can be obtained if the electron beam 3 can be applied to the sample 9, the measurement can be performed even in the air.

  Such a purpose can be realized by providing a diaphragm 90 at the outlet of the electron beam column 2 through which the electron beam 3 passes and air does not flow. Since it is necessary to withstand the differential pressure between the vacuum in the electron beam column 2 and the atmospheric pressure, a thin and strong film is required. Since the visual field may be small, it is sufficient that a thin film (diaphragm 90) is formed with respect to an opening of at most 10 microns. For example, a very thin aluminum thin film or titanium thin film of several tens to several hundreds of nanometers, a carbon thin film such as graphene, an organic thin film such as polyimide, or the like can be used. The electron beam 3 that has passed through this film irradiates the sample 9 and generates secondary electrons. The generated secondary electrons are neutralized by the surrounding air. On the other hand, since a substrate current corresponding to the neutralized amount of secondary electrons is generated, an image can be formed using the current. Although depending on the type of the diaphragm 90, an acceleration voltage of about several kilos to several tens of kilovolts is desirable. When it is not desirable to directly irradiate the sample 9 with 10 KV, a desired landing voltage can be obtained by applying a bias voltage to the sample 9. When the bias voltage is increased, the secondary electrons and the reflected electrons are accelerated and have a large energy, so that the secondary electrons and the reflected electrons may reach the electron beam column 2 even in the air. In such a case, secondary electrons and reflected electrons may be used simultaneously as in the configuration diagram of the embodiment of FIG.

  Next, the operation of the configuration of FIGS. 1 and 2 will be described in detail according to the order of the flowchart of FIG.

  FIG. 3 shows a flowchart for explaining the operation of the present invention.

  In FIG. 3, S1 performs global alignment. For example, as shown in FIG. 4 to be described later, an image of a global alignment mark formed in advance at a predetermined position on a wafer 91 as a sample 9 is acquired, and the acquired position (on the image of the global alignment mark) is acquired. ) (Position coordinates from the laser distance measuring device 10)) and the association (correspondence between both coordinate systems) with the position of the global alignment mark on the CAD data (position coordinates on the CAD data). Do. Thereafter, movement control of the irradiation position of the electron beam 3 on the wafer which is the sample 9 is performed using coordinates on the CAD data.

  As described above, the position on the wafer and the position on the CAD data are associated with each other based on the plurality of global alignment marks in FIG. 4 on the wafer. Thereafter, the position (coordinates) on the CAD data. Based on the above, it becomes possible to control movement to a predetermined pattern position.

  In S2, the position coordinates of the wafer measurement point are acquired from the CAD data. As a result, the position coordinates of the measurement target in the pattern on the plurality of layers (position coordinates consisting of the distance and direction from the origin in FIG. 4) can be acquired, and preparation for moving to the measurement point and measuring is completed.

  In S3, the stage is moved to the measurement point. This is based on the position coordinates (distance and direction from the origin in FIG. 4) of the measurement point acquired in S2, and the stage 6 is sampled precisely at the measurement point based on the information from the laser distance measuring device 10. (Wafer) 9 is positioned.

  In S4, the electron beam 3 is scanned. In this state, the surface is scanned with the electron beam 3 in a predetermined area range in a state where the measurement point is positioned in S3.

  In S5, a secondary electron image, a reflected electron image, and a substrate current image are acquired. This corresponds to the scanning of the predetermined area in a state where the electron beam 3 is positioned at the measurement point in S4, and the emitted secondary electrons and reflected electrons are detected by the electron detection devices 4 and 41, The substrate current flowing toward the wafer is detected by the plate 8, and a secondary electron image, a reflected electron image, and a substrate current image are acquired and temporarily accumulated.

  In S6, it is determined whether a substrate current image is visible. This determines whether or not the substrate current image (the substrate current image formed based on the current flowing through the sample 9 (or the current flowing through the plate 8)) acquired in S5 is visible. In the case of YES, since the substrate current image of the lower layer pattern to be measured is seen in the predetermined area centered on the measurement point, the determination becomes YES and the process proceeds to S10. On the other hand, when not seeing, it becomes NO and progresses to S7.

  In S7, it was found that the substrate current image could not be seen with NO in S6. Therefore, the acceleration voltage was increased, and the transmission voltage was increased by increasing the acceleration voltage of the electron beam 3 so that the electron beam 3 reaches the lower layer pattern on a plurality of layers. Increase

  S8 determines whether the maximum value. The acceleration voltage in S7 is increased by a predetermined value to determine whether the acceleration voltage of the electron beam 3 can no longer be increased even when it reaches the maximum value. In the case of YES, since it has been found that the acceleration voltage is too high and the electron beam 3 cannot be seen through the lower layer pattern on the plurality of layers, the acceleration voltage is decreased in S9 and S5 and subsequent steps are repeated. When S9 is repeated and the minimum acceleration voltage of the electron beam 3 is reached, the process ends as an error. On the other hand, in the case of NO, S5 and subsequent steps are repeated.

  By repeating the above steps S5 to S9, when the substrate current image of the wafer is not visible, the acceleration voltage of the electron beam 3 can be increased or decreased to automatically control the substrate current image with the optimum contrast. It becomes possible.

  In S10, since it is determined that the substrate current image is seen in S6 YES, distance measurement and alignment information are obtained. This obtains alignment information such as distance information and position information of the secondary electron image (or reflected electron image) of the pattern to be measured on the upper layer of the plurality of layers and the substrate current image of the lower layer pattern.

  In step S11, interlayer alignment information is obtained (see FIG. 8).

  S12 displays the result on the display. This displays the interlayer alignment information obtained in S11 on the display, for example, on the display as shown in FIG.

  In step S <b> 13, the result is transferred to the exposure device 32. This is because interlayer alignment information (see, for example, FIG. 14) is transferred to the exposure apparatus 32 as correction data, and the positional shift between the upper layer pattern and the lower layer pattern indicated by the interlayer alignment information is adjusted for each shot. Correct the position by correcting the position when the layer is exposed to zero. This automatically corrects the position of the inter-layer pattern of the pattern on multiple layers due to some cause, and automatically corrects the position of the inter-layer pattern (zero or within tolerance) It becomes possible to.

  FIG. 4 shows an explanatory diagram (part 1) of the present invention. FIG. 4 shows an example of the global alignment mark of the present invention.

  In FIG. 4, a wafer 91 is an example of the sample 9 in FIGS. 1 and 2, in which a plurality of global alignment marks 92 for matching the coordinate system are provided in advance at predetermined coordinates, and a plurality of layers are formed on the surface. (Pattern for measurement of displacement) is formed.

  A plurality of global alignment marks 92 are formed in advance at predetermined coordinates, and here, three points are formed in the periphery as shown in the figure (more may be formed).

  The origin A and origin B are examples of origins for determining the position of each pattern on the wafer 91. For example, as shown in the figure, substantially the center of the wafer 91 (origin B) or a point outside the wafer 91 (origin A , Etc., which are the origins determined in advance in association with the wafer 91. When the origin is determined, the position of the pattern or the like on the wafer 91 is represented by the distance and direction from the origin.

  As described above, the coordinate system on the wafer 91 can be determined based on the plurality of global alignment marks 92 on the wafer 91. At this time, the origins A, B, etc. on the wafer 91 are determined in advance and are represented by the positions (coordinates) of the pattern, etc., on the wafer 91 in the distance and direction from the origins A, B. As a result, the coordinate system on the wafer 91 and the coordinate system of CAD data as design data are associated with each other, and thereafter, it is possible to align with the pattern to be measured in the coordinate system of CAD data.

FIG. 5 shows an explanatory diagram (part 2) of the present invention. FIG. 5 shows a wafer 91 with a first insulating layer as a first layer, a second insulating layer and wiring as a second layer, a third insulating layer as a third layer and a contact hole (conductor).
FIG. 5A shows a cross-sectional view, and FIG. 5B shows a top view. For simplicity, only the wiring portion is taken out and shown.

  In FIG. 5, the lowermost layer (first layer) is an insulating layer such as an oxide film. On the second layer thereabove, metal or polysilicon wiring is provided. Further, a contact hole (or via hole) is formed in the third layer thereon.

  FIG. 6 shows an explanatory diagram (part 3) of the present invention. FIG. 6 shows an example of an image acquired with the apparatus of FIG. 1 or 2 for the wafer 91 of FIG. The electron beam 3 is surface-scanned sequentially or randomly in the XY direction on the surface of FIG. 5B at a certain speed, and a signal in which secondary electrons (or backscattered electrons) are detected in synchronization therewith, and a substrate current. Get the signal. The magnitude of the signal corresponds to the luminance signal on the image and is expressed in light and dark, the secondary electron image (reflected electron image) is the image of FIG. 6A, and the substrate current image is FIG. The image of (c) is obtained simultaneously.

  The accuracy of the electron beam irradiation point on the wafer 91 is controlled to 0.1 nm or more. An image (substrate current image) generated from an image (secondary electron image, reflected electron image) generated from a signal detected from the upper surface of the wafer 91 by electron beam scanning and a signal acquired from the wafer 91 (or through the plate 8). There is. Since each image is a signal from the irradiation point of the same electron beam 3, both obtained images are represented by different signals at the same location, and it is guaranteed that the positional relationship is 1: 1. . In other words, signals generated at the same time can be regarded as information at the same point, and by comparing the images from each signal, the positional relationship between the patterns represented by both signals (images) can be accurately compared. It becomes possible to do.

  The secondary electron image (or reflected electron image) obtained from the upper surface of the wafer 91 constitutes an image reflecting the geometric shape when the wafer 91 is viewed from above. On the other hand, the substrate current image obtained from the lower surface of the wafer 91 provides information on the geometric shape reflecting the shape of the conductive material existing at the depth where the electron beam 3 is transmitted, like an X-ray image. Further, since the material constituting the state-of-the-art semiconductor device is very thin, the electron beam 3 penetrates easily. By changing the energy of the electron beam 3 in various ways, the reachable distance or depth of the electron beam 3 can be continuously changed, and the energy of the electron beam 3 as a function of the distance can be varied. The geometric shape of the conductor can be obtained. Furthermore, if an image irradiated with the electron beam 3 is used at a different angle, 3D information can be reconstructed based on the principle of CT.

  FIG. 6A shows a secondary electron image composed of signals obtained from the upper surface of the wafer 91. FIG. 6A shows an example in which a contact hole is observed, and an image of the opening of the contact hole is obtained. Since the contact hole has a very large aspect ratio, the secondary electron signal does not rise from the bottom of the hole, so that the bottom of the hole becomes a dark image as shown in the figure.

  FIG. 6B shows a substrate current image acquired with the energy of the electron beam 3 adjusted so as not to penetrate the insulator. In the case of FIG. 6B, the electron beam 3 is just focused on the bottom of the hole. Since the substrate current flows when the electron beam 3 reaches the conductor, the bottom shape of the contact hole having a large aspect ratio can be observed. For example, by comparing the image of FIG. 6A and the image of FIG. 6B, the positional relationship between the hole bottom and the lower layer wiring can be accurately known.

  FIG. 6C shows a substrate current image obtained by setting the energy of the electron beam 3 to be scanned to such a magnitude that it passes through the second insulating layer. As is apparent from the substrate current image in FIG. 6C, in this substrate current image, two layers of structures (conductive patterns) at different depths are reproduced simultaneously in one image. From this substrate current image, it is possible to directly measure the relative positional relationship between the position of the bottom of the contact hole and the wiring (conductor pattern) buried in the insulator and not visible from the outside.

  FIG. 7 shows an explanatory diagram (part 4) of the present invention. FIG. 7 shows a method of measuring the alignment state from the image obtained in FIG.

  FIG. 7A shows an example of a method for evaluating a position using an edge or contour of a structure (pattern) constituting an image. In the method of FIG. 7A, a boundary line is calculated by finding a portion where the contrast of the image changes suddenly, and the distance between the boundary line and the boundary line is measured. The bottom shape of the high aspect contact hole is distorted and is not necessarily a perfect circle. It may be oval or jagged. In particular, if the contact hole is stepped on the lower layer wiring, it causes current leakage. Therefore, it is very important to manage the edge position by the method of the present invention. As the boundary detection method of FIG. 7A, any known method such as a method of taking a luminance peak, a method of using a differential value of luminance, Laplacian, Sobel, Roberts, Prewitt, or the like can be applied.

  FIG. 7B shows a method for evaluating the positional relationship of each layer using the center of gravity of the contact hole. One of the causes that the relative position of each layer changes is an etching process. For example, very deep etching is performed in the contact hole formation process, but since etching is a synthesis of physical and chemical reactions, the reaction does not always progress uniformly, and vertical holes are not always formed. In general, since the way of chemical reaction differs between the peripheral portion and the central portion of the wafer 91, the contact hole is asymmetrical or slightly tilted with respect to the plane of the wafer 91. In particular, it is known that the hole formation state varies greatly with changes in process conditions when the target is nm-order position control as in recent years. In such a case, the process bias can be detected by statistically processing the center of gravity of the hole formed as shown in FIG. 7B together with the edge information shown in FIG. By using this, it becomes possible to increase the process yield of semiconductor devices such as correction of semiconductor process conditions and correction of semiconductor layout.

  It is also important to know the process result after etching, but it is more convenient if the positional deviation is found at the photolithography process stage. At the lithography process stage, if a desired structure cannot be formed at the design position, after removing the resist, it is possible to apply the resist again and perform a relithographic process to remove the defects ( This will be described in detail with reference to FIG.

  FIG. 8 shows an example of an interlayer shift table of the present invention. The illustrated interlayer shift table registers and manages measured data such as the displacement of the interlayer pattern measured in FIG. 7B described above. Here, for example, the following information illustrated in FIG. Measure, register and manage.

・ ID:
-X direction shift:
・ Y direction shift:
・ Direction (vector difference):
・ Shift amount:
-Allowable value:
・ Other:
Here, ID is given to the measurement data of the amount of positional deviation between the wiring pattern in FIG. 7B (vertical band-shaped wiring pattern in the dotted line direction) and the bottom pattern of the contact hole (circular pattern). Unique ID. The X-direction shift and the Y-direction shift are the X-direction shift amount and the Y-direction shift amount between, for example, the wiring patterns shown in FIGS. 7A and 7B and the bottom pattern of the contact hole specified by the ID. The direction (vector difference) is a direction (vector difference) that can be shifted in the X direction and the Y direction. The shift amount is a shift amount from a position (optimal position) where the two patterns coincide. The allowable amount is an allowable amount even if there is a shift amount.

  FIG. 9 is an explanatory view (No. 5) of the present invention. FIG. 9A shows a cross-sectional view of the wafer 91 immediately after the resist pattern is formed by the photolithography process, and FIG. 9B shows a top view. The lowermost layer (first layer) is an insulating layer, in which a wiring layer is formed on the second layer, an insulating layer is formed on the third layer, and a resist having a pattern formed by development on the fourth layer is laminated in order. .

  Since the fourth layer resist (photoresist) is a carbon compound having a low density, it can transmit a low-energy electron beam. However, if the energy is too low, scattering occurs in the middle of the resist layer and the energy is attenuated, so that it accumulates as charges in the resist. If the insulating film such as a dense thermal oxide film or a nitride film is very thick, it is difficult for the electron beam 3 to pass therethrough. However, if the film is about 200 nm as used in a state-of-the-art device, it is about 5 KV. It can be transmitted with energy.

  Under such conditions, the scanned electron beam 3 passes through the resist and the oxide film or nitride film and reaches the second wiring layer. Since the wiring layer is generally very long and is connected to a substrate on which a transistor is formed somewhere, the electron beam 3 reaching the wiring layer eventually flows to the substrate (wafer 91). Even when the wiring is not in direct contact with the substrate, since the wiring is long, a relatively large capacitance is formed between the substrate (wafer 91). Therefore, electrons that reach the wiring also generate a substrate current. When an image is formed using this substrate current, substrate current images as shown in FIGS. 10A and 10B are obtained. In the substrate current image, in the fourth layer in FIG. 9, the hole opening formed in the resist and the lower layer wiring are reproduced in the same image. From this image, the alignment information of the pattern between each layer can be obtained.

  FIG. 10A shows an example in which alignment is evaluated using edges, and FIG. 10B shows an example in which alignment is evaluated using hole center-of-gravity positions.

  FIG. 11 shows an explanatory diagram (No. 7) of the present invention. FIG. 11 shows an example used for managing a self-aligned contact hole forming process called SAC.

  FIG. 11A is a cross-sectional view of a SAC device. This process is to create a contact hole in a self-aligned manner by using the fact that a thin oxide film and nitride film are provided around the gate by CVD or the like after the gate electrode is formed, and the thickness can be easily and accurately controlled. . In this process, it is important to accurately leave the side walls provided on both sides of the gate.

  The alignment of the resist pattern for forming contact holes are misaligned with respect to the gate electrode position, it is either the side wall not etched symmetrically extra etched leakage current occurs. Since leakage causes a transistor failure, it is necessary to control the holes so that they are accurately symmetric with respect to the side walls.

  If the present invention is used, the positional relationship between the resist structure and the gate wiring can be known before the etching is performed. Therefore, if a deviation occurs, the resist process can be repeated to prevent the occurrence of defects (FIG. 15). reference).

  Since the gate is capacitively grounded to the silicon substrate (wafer 91) via a very thin insulating film called a gate oxide film, a gate capacitance is formed and there is a leakage current. Current of about nA flows. FIG. 11B shows this current imaged.

  The energy of the electron beam 3 is set to an energy that penetrates the insulating film on the gate. When the substrate current image is acquired under such conditions, both the opening shape of the resist hole and the gate wiring embedded in the oxide film can be seen on the same screen.

  By extracting an edge from FIG. 11B, the positional relationship between the resist pattern position and the gate wiring layer can be known by measuring the length and width of each geometrical figure. Further, since the absolute position of the scanning position of the electron beam 3 is always monitored by a laser interferometer (laser distance measuring device 10), the absolute position coordinates of the structure (pattern) on the wafer 91 are in the order of sub nm. You can know with accuracy. Thereby, the quality of alignment of the produced structure (pattern) can be determined also from the viewpoint of absolute position.

  If the desired position is not achieved, the process condition, CAD data, or alignment data at the time of exposure is corrected, and the exposure process is repeated to increase the yield (see FIG. 15).

  FIG. 12 shows an explanatory diagram (No. 8) of the present invention. FIG. 12 shows an example of measurement points for each shot. As shown in FIG. 12, four measurement points are provided for each shot in FIG. 12, one for each corner of the rectangular shot region, and the position of the interlayer pattern at these four measurement points is determined. The respective amounts are measured, the average of these is calculated, and the amount of displacement of the interlayer pattern of the shot is calculated (in addition, more or fewer measurement points may be used). Then, when the position shift of the interlayer pattern is calculated for all shots, and the calculated position shift amount is schematically represented by the direction and the size, the interlayer position for each shot on the wafer 91 as shown in FIG. It is possible to display the amount of slip.

  FIG. 13 shows an example of an alignment pattern of the present invention. In the illustrated alignment pattern, lines are provided in the vertical direction and the horizontal direction, respectively, and four groups form one group. By using these alignment patterns, it is possible to detect vertical and horizontal misalignments, rotations, reductions in reduction ratio, and the like by measuring one alignment pattern. For this reason, sufficient measurement accuracy can be realized only by allocating a size of 1/10 or less on the wafer 91 as compared with the conventional pattern.

  Here, the positional deviation amount of the alignment of the interlayer pattern can be calculated by the following (Equation 1). The shift amount is calculated by subtracting the X and Y coordinates of the reference alignment pattern and the X and Y coordinates of the alignment pattern of the wafer 91, respectively. Any number of measurement points may be used as long as the coordinates correspond to the same coordinates on the design drawing. The direction of deviation is given by the vector sum of the respective shift amounts. If the X-axis shift and the Y-axis shift are the same amount, it is calculated that the shift is in the 45 degree direction. The reduction ratio is obtained by measuring the length of the coordinates of two points whose lengths are known in design and obtaining the difference. For example, the ratio of the difference between the x1 coordinate and the X2 coordinate on the wafer 91 and the length between two points on the design is obtained.

X shift amount = reference pattern position coordinate x1−wafer 91 pattern position coordinate x2
Y shift amount = standard pattern position coordinate y1-wafer 91 pattern position coordinate y2
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (Formula 1)
FIG. 14 shows a display example of the position shift amount of the present invention. FIG. 14 schematically shows the measurement result of the amount of displacement of the interlayer pattern. The arrows in the figure indicate the displacement direction and the size of the alignment (interlayer pattern) obtained by (Equation 1) in FIG. In this way, by indicating the alignment direction for each shot, which is the minimum process unit of the exposure apparatus, it is possible to confirm at a glance how much positional deviation occurs in which direction for each shot. In order to know an accurate deviation value, it is displayed (recorded) numerically as shown in the interlayer shift table of FIG. The measured interlayer shift data is converted into a format that can be read by the exposure apparatus, and then sent to the exposure apparatus. These amounts of misalignment indicate the magnitude and direction of misalignment between shots of the exposure apparatus. By using these pieces of information to correct the alignment information so that the deviation amount becomes zero, and then returning to the exposure apparatus and performing exposure again, exposure with normal alignment can be obtained on the entire wafer 91 ( FIG. 15).

  FIG. 15 is a flowchart for explaining another operation of the present invention.

  In FIG. 15, a wafer surface treatment is performed in S21. This cleans the surface of the wafer 91 and makes it easier to apply the resist.

  In S22, a resist is applied. In this method, the resist is uniformly applied to the surface of the wafer by an applicator such as spin coat or bubble jet (registered trademark). At the same time, the wafer is heated uniformly to remove the solvent contained in the resist and fix it on the surface of the wafer.

  In step S23, the alignment data is corrected. This is based on the design data, and the second and subsequent times are based on the amount of displacement of the interlayer pattern at several measurement points for each shot obtained by the alignment measurement in S26 described later, the difference in the reduction ratio, and the like. The alignment data is corrected so as to be within the allowable value.

  In step S24, exposure is performed.

  In step S25, development is performed.

  In step S26, alignment is measured.

  In S24 to S26, the pattern of each layer constituting the interlayer pattern of the wafer is exposed and developed on the basis of the alignment data corrected in S23 (initially the design data). Alignment information such as the amount of positional deviation of the interlayer pattern at the measurement point and the difference in reduction ratio is measured.

  In S27, it is determined whether the spec is in. In step S26, it is determined whether the positional deviation amount of the interlayer pattern, the reduction rate, and the like are within the allowable values. In the case of YES, since it is determined that the value is within the allowable value (spec-in), the next step of S30 proceeds. On the other hand, in the case of NO, since it has been found that the value is not within the allowable value (spec-in), the resist on the wafer is removed in S28, the wafer is cleaned in S29, the process proceeds to S21, the alignment data is corrected in S23, and S24 Repeat thereafter.

  As described above, several measurement points are set for each shot, which is the minimum unit of the exposure apparatus 32, and measurement is performed so that the shift direction, shift amount, rotation direction, rotation amount, etc. of the alignment in the entire wafer surface can be known. In step S26, it is determined whether or not the spec-in is performed by comparing with a predetermined alignment error tolerance (S27). If the spec-in is performed, the exposure process is completed, and post-baking, etching, and the like are performed. Advance to the wafer process. On the other hand, if not spec-in, the resist adhering to the wafer surface is stripped by a resist stripping process such as a liquid phase or oxygen plasma (S28), and the wafer surface is washed, and then the alignment obtained for this wafer is obtained. Based on the measurement information, the alignment data is corrected so that correct alignment can be obtained by re-exposure (alignment data is corrected in the direction opposite to the shifted direction). It becomes possible to manufacture a non-defective wafer by performing re-exposure using the data thus corrected.

1 is a configuration diagram of one embodiment of the present invention. It is another Example block diagram of this invention. It is an operation | movement explanatory flowchart of this invention. It is explanatory drawing (the 1) of this invention. It is explanatory drawing (the 2) of this invention. It is explanatory drawing (the 3) of this invention. It is explanatory drawing (the 4) of this invention. It is an example of the interlayer shift table of this invention. It is explanatory drawing (the 5) of this invention. It is explanatory drawing (the 6) of this invention. It is explanatory drawing (the 7) of this invention. It is explanatory drawing (the 8) of this invention. It is an example of the alignment pattern of this invention. It is an example of a display of the amount of position shift of the present invention. It is another operation | movement description flowchart of this invention.

1: electron gun 2: electron beam column 3: electron beam 4: electron detector 5: vacuum chamber 6: XY stage 7: stage controller 8: plate 9: sample 90: thin film 91: wafer 12: high voltage power supplies 21, 22 : Current amplifier 23: AD
24: PC
25: moving means 26: scanning means 27: image acquiring means 28: measuring means 29: evaluation means 30: measurement data storage means 31: CAD data storage means 32: exposure apparatus

Claims (12)

In an alignment measuring apparatus that measures alignment between patterns on multiple layers formed on a substrate,
A moving means for moving and positioning the substrate at the position of the pattern to be aligned among the plurality of layers formed on the substrate;
Arranging means for arranging the alignment object in the atmosphere or in a pressure close to the atmosphere;
A scanning unit that scans while irradiating the alignment target arranged in the atmosphere or in a pressure close to the atmosphere by the arrangement unit with the electron beam beam narrowly narrowed in a vacuum in the positioned state;
First image acquisition means for acquiring an image of an upper layer pattern of a plurality of layers formed on the substrate while being scanned while being irradiated with an electron beam accelerated by a first acceleration voltage by the scanning means. When,
An image of a lower layer pattern of a plurality of layers formed on the substrate is acquired in a state in which the scanning unit scans while irradiating an electron beam beam accelerated by an acceleration voltage obtained by increasing the first acceleration voltage. A second image acquisition means;
An alignment measuring apparatus comprising: a measuring unit that measures a positional deviation amount between the acquired pattern of the first upper layer and the pattern of the second lower layer . In an alignment measuring apparatus that measures alignment between patterns on multiple layers formed on a substrate,
A moving means for moving and positioning the substrate at the position of the pattern to be aligned among the plurality of layers formed on the substrate;
Arranging means for arranging the alignment object in the atmosphere or in a pressure close to the atmosphere;
A scanning unit that scans while irradiating the alignment target arranged in the atmosphere or in a pressure close to the atmosphere by the arrangement unit with the electron beam beam narrowly narrowed in a vacuum in the positioned state;
An upper layer image acquisition means for acquiring an image of an upper layer pattern of a plurality of layers formed on the substrate in a state of being scanned while irradiating an electron beam with the scanning means;
While scanning while irradiating an electron beam that is accelerated by the first acceleration voltage by said scanning means, first to obtain an image of the first underlying pattern of a plurality layers formed on said substrate A lower layer image acquisition means;
A second of a plurality of layers formed on the substrate is scanned while being irradiated with an electron beam beam accelerated by the second acceleration voltage with the first acceleration voltage raised or lowered by the scanning means. Second lower layer image acquisition means for acquiring an image of the lower layer pattern of
An alignment measurement comprising: a measuring unit that measures a positional deviation amount between the acquired upper layer pattern and one or more of the first lower layer pattern and the second lower layer pattern. apparatus.   The upper layer and lower layer or lower layer pattern images are obtained by detecting a substrate current flowing through the substrate when scanning while irradiating a finely focused electron beam, and acquiring an upper layer or lower layer pattern image. The alignment measuring apparatus according to claim 1.   An image of the upper layer pattern is detected by detecting secondary electrons emitted from the upper layer pattern or reflected electrons reflected by the upper layer pattern when scanning while irradiating a finely focused electron beam. The alignment measuring device according to claim 1, wherein the alignment measuring device is acquired.   The amount of positional deviation between the acquired upper layer pattern and lower layer pattern is measured, and compared with a preset allowable value, it is determined that the alignment is good and when the value is outside the allowable value, the alignment is determined to be bad. 5. The alignment measuring apparatus according to claim 1, wherein   6. An alignment measuring apparatus, wherein when the alignment is determined to be poor, an instruction is given to peel off the exposed and developed resist on the substrate and perform resist coating, exposure and development again.   The sizes of the upper layer pattern and the lower layer pattern are respectively measured and compared with design values, respectively, the reduction rate of the upper layer pattern and the lower layer pattern is calculated, or the error of the reduction rate of both is calculated. An alignment measurement apparatus according to any one of claims 1 to 6.   The positional relationship between the lower layer image of the bottom of the contact or via hole acquired from the bottom of the contact or via hole pattern that is the lower layer pattern, and the upper layer image of the pattern that is arranged to contact the contact or via hole that is the upper layer pattern The alignment measuring apparatus according to claim 1, wherein the quality of the contact hole or the via hole is determined based on a preset allowable value.   9. The alignment according to claim 1, wherein the amount of positional deviation between the upper layer pattern and the lower layer pattern is measured in an area for each shot exposed on the substrate by an exposure apparatus. measuring device.   4. The alignment measurement apparatus according to claim 3, wherein an acceleration pattern of the electron beam is varied to acquire an image of a lower layer pattern having the best contrast. In an alignment measurement method for measuring alignment between patterns on a plurality of layers formed on a substrate,
A movement step of moving and positioning the substrate to the position of the pattern to be aligned among the plurality of layers formed on the substrate;
In the positioned state, the alignment object is arranged in the atmosphere or in a pressure close to the atmosphere by an arrangement means for arranging the electron beam narrowed in vacuum in the atmosphere or in a pressure close to the atmosphere. A scanning step of scanning while irradiating;
A first image acquisition step of acquiring an image of an upper layer pattern among a plurality of layers formed on the substrate in a state of being scanned while irradiating the electron beam accelerated at the first acceleration voltage in the scanning step. When,
An image of a lower layer pattern of a plurality of layers formed on the substrate is scanned while irradiating with an electron beam accelerated by a second acceleration voltage that has been increased by the first acceleration voltage in the scanning step. A second image acquisition step to acquire;
An alignment measurement method, comprising: a measurement step of measuring a positional deviation amount between the acquired pattern of the first upper layer and the pattern of the second lower layer . In an alignment measurement method for measuring alignment between patterns on a plurality of layers formed on a substrate,
A movement step of moving and positioning the substrate to the position of the pattern to be aligned among the plurality of layers formed on the substrate;
In the positioned state, the alignment object is arranged in the atmosphere or in a pressure close to the atmosphere by an arrangement means for arranging the electron beam narrowed in vacuum in the atmosphere or in a pressure close to the atmosphere. A scanning step of scanning while irradiating;
An upper layer image acquisition step of acquiring an image of an upper layer pattern among a plurality of layers formed on the substrate in a state of being scanned while irradiating an electron beam in the scanning step;
While scanning while irradiating an electron beam that is accelerated by the first acceleration voltage at the scanning step, the first to obtain an image of the first underlying pattern of a plurality layers formed on said substrate A lower layer image acquisition step;
A second of the plurality of layers formed on the substrate is scanned while being irradiated with an electron beam beam accelerated by a second acceleration voltage that has been increased or decreased in the scanning step. A second lower layer image acquisition step of acquiring an image of a lower layer pattern;
An alignment measuring method comprising: a measuring step of measuring a positional deviation amount between the acquired upper layer pattern and any one or more of the first lower layer pattern and the second lower layer pattern. .

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