JP4255657B2 - Semiconductor manufacturing process management method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor manufacturing process management method, a semiconductor manufacturing process management system, and Inline electron beam evaluation system In particular, the present invention relates to a technique for improving alignment accuracy when patterns formed of various material films are stacked.
[0002]
[Prior art]
In general, in a manufacturing process of a semiconductor device, a semiconductor element having a fine structure is formed by sequentially laminating patterns formed of various material films such as a metal film, a semiconductor film, and an insulator film on a semiconductor substrate. . When laminating this pattern, the upper layer pattern is aligned with the lower layer pattern formed in the previous step in the exposure step. That is, when performing the exposure process of the upper layer pattern, the upper layer pattern is formed by exposing the upper layer mask pattern by aligning (aligning) the lower layer pattern formed on the semiconductor wafer with a predetermined standard. Overlaid on the pattern.
[0003]
In recent years, development of ultra-highly integrated semiconductor devices has been energetically advanced, and mask alignment in the exposure process, which is indispensable for the formation of semiconductor element structures, as semiconductor elements are miniaturized and densified. There is a strong demand for improved accuracy. Here, the alignment of the mask pattern with respect to the lower layer pattern is roughly divided into the following seven components: (1) shift, (2) wafer scaling (wafer expansion / contraction), (3) wafer rotation (wafer rotation), ( 4) Wafer orthogonality (wafer orthogonality), (5) Shot rotation (shot rotation), (6) Shot magnification (shot magnification or shot expansion / contraction ratio), and (7) Distortion matching.
[0004]
A margin (allowable range) is set for mask misalignment in each component of superposition in the exposure process as described above, and the manufacturing process of the semiconductor device is managed using the margin. For example, in Japanese Patent Application Laid-Open No. 11-274037, in a semiconductor device manufacturing method, an appropriate alignment accuracy is set for each exposure process, and a product is accurately obtained in alignment inspection between a lower layer pattern and an upper layer pattern performed after the exposure step. Has been disclosed (see FIG. 28).
[0005]
The above-described alignment inspection is generally calculated by forming a pair of so-called box marks in the lower layer pattern and the upper layer pattern of the semiconductor device and measuring the amount of positional deviation between these box marks. The measurement of the amount of deviation is carried out after the exposure and development process for forming the upper layer pattern, and usually a photoresist is used as the upper layer pattern. In addition, since one box mark formation region is used for each alignment, the box mark formation region used for each alignment is different. For this reason, a hox mark formation region is required at least as many times as alignment is performed. Therefore, these box marks are provided in a region (region on the scribe line) different from a region (chip region or product region) where elements such as transistors are formed. Thereby, the amount of misalignment can be measured and calculated without increasing the chip area.
[0006]
Hereinafter, a method for managing a semiconductor device manufacturing process based on the above-described deviation amount will be described with reference to FIG. Prior to the wafer processing (manufacturing process), a database regarding alignment margins is prepared. Process flow, photomask information, and the like are input to this database. When the wafer processing is started, an exposure process is performed through a film forming process, an etching process, and the like (step S101) (step S102). Thereafter, alignment inspection is performed (step S103), and a mask misalignment amount in the exposure process is measured.
[0007]
Subsequently, information on the alignment margin is acquired by searching the above-described database (S104), and it is determined whether the misalignment amount obtained as the above-described inspection result is smaller than the margin acquired from the database. (Step S105). Here, when the inspection result is smaller than the margin (step S105; YES), the next process is performed (step S106), and the above-described steps S101 to S105 are repeated. On the other hand, when the inspection result is larger than the margin (step S105; NO), an alarm is displayed to notify the operator of that fact. As a result, the operator grasps that the misalignment amount exceeds the standard value and takes necessary measures.
[0008]
[Problems to be solved by the invention]
However, the conventional manufacturing process management method described above has the following problems. The first problem is that even if the misalignment amount exceeds the standard value, it cannot be properly reflected in the manufacturing process, and it is difficult to effectively improve the yield. That is, according to the conventional method, it is not possible to measure the substantial overlay deviation amount between the lower layer pattern and the upper layer pattern that determines the operating characteristics of the electronic circuit. The reason for this is that, as described above, the overlay displacement amount is detected after the exposure and development process, and the overlay displacement amount is measured using the upper layer box mark and the lower layer pattern made of photoresist. is there.
[0009]
Further details will be described. A semiconductor integrated circuit includes transistors and wirings formed in each layer and holes (also called plugs) that electrically connect different layers. The relative overlay (positioning) accuracy when stacking fine elements such as transistors, wirings, and holes has been considered to be determined only by the exposure process. However, due to the recent development of miniaturization and high integration of semiconductor integrated circuits, the fine element structure of each layer, represented by holes, has a vertically long cross-sectional structure, and the etching process capability or film formation process after the exposure process. The amount of misalignment between the lower layer pattern and the upper layer pattern has also been affected by the process capability.
[0010]
FIG. 29 is a view showing an example of a cross-sectional structure after the etching step (not after the normal exposure step) in the upper layer pattern forming step, and FIG. 29 (a) shows the wafer peripheral portion. b) shows the wafer center. In the figure, L1 is an insulating film layer, L2 is a wiring layer, L3 is an insulating film layer (upper layer), and L4 is a photoresist. In this example, holes H are formed in the insulating film layer L3 using the developed photoresist L4 as a mask. The upper layer pattern made of the photoresist L4 is laminated with good overlay on the lower layer pattern made of the wiring layer L2 in both FIGS. This can be measured using a conventional overlay inspection apparatus.
[0011]
However, in the wafer peripheral portion, as shown in FIG. 29A, the superposition of the hole H formed in the insulating film layer L3 and the wiring layer L2 becomes defective. This is because all of the bottom of the hole H is not in contact with the wiring layer L2 which is the lower layer pattern. In this case, the contact resistance between the upper hole H and the lower wiring layer L2 is increased, and the characteristics of the product are deteriorated. In other words, even if it is regarded as a non-defective product in the conventional overlay inspection in the manufacturing process management, the actual electrical characteristics may exceed the management standard, and it can be said that the quality control of the manufacturing process is not substantially performed.
An example given here is the misalignment caused by the etching of the hole H being carried out obliquely with respect to the substrate surface in the etching process. This phenomenon is caused by miniaturization and high integration of the semiconductor integrated circuit. This is a phenomenon that has become apparent especially in the periphery of the wafer.
[0012]
The present invention has been made in view of the above circumstances, and it is possible to reduce the measurement error of the overlay amount and effectively suppress misalignment when stacking each layer in the semiconductor device manufacturing process. Semiconductor device manufacturing process management method, semiconductor manufacturing process management system, and Inline electron beam evaluation system The purpose is to provide.
[0013]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configuration.
The invention described in claim 1 is a method of managing a process control standard range by an overlay inspection apparatus using an optical signal by using an overlay deviation amount obtained from an inline electron beam evaluation apparatus using a substrate current signal. (A) a first step of performing an exposure process for transferring an upper layer pattern made of a photoresist after forming the lower layer pattern, and (b) the lower layer pattern using an overlay inspection apparatus using an optical signal. A second step of measuring a first overlay deviation amount with the upper layer pattern; and (c) a second step of the lower layer pattern and the upper layer pattern using an inline electron beam evaluation apparatus using a substrate current signal. A third step of measuring the overlay displacement amount; and (d) identifying a correspondence relationship between the first overlay displacement amount and the second overlay displacement amount. And (e) a fifth step of determining a process management standard relating to the first overlay deviation amount with reference to the second overlay deviation amount based on the correspondence, and (f) the process A sixth step of registering the management standard in a database to be referenced in the manufacturing process; (G) a seventh step of referring to the database and determining whether a measurement result by the overlay inspection apparatus using the optical signal satisfies the process control standard; and (h) the measurement result is the And an eighth step of subjecting the exposure processing to reprocessing when the process control standard is not satisfied. It is characterized by.
[0015]
Claim 2 The described invention is a method for managing a process control standard range by an overlay inspection apparatus using an optical signal, using an overlay deviation amount obtained from an inline electron beam evaluation apparatus using a substrate current signal, a) a first step of performing an exposure process for transferring an upper layer pattern made of a photoresist after forming a lower layer pattern; and (b) the lower layer pattern and the upper layer pattern using an overlay inspection apparatus using an optical signal. And a second step of measuring a first overlay deviation amount with (c) a second overlay deviation between the lower layer pattern and the upper layer pattern using an inline electron beam evaluation apparatus using a substrate current signal A third step of measuring the amount; and (d) a fourth step of specifying a correspondence relationship between the first overlay deviation amount and the second overlay deviation amount. And (e) a fifth step of determining a process management standard relating to the first overlay deviation amount with reference to the second overlay deviation amount based on the correspondence relationship; and (f) the process management. A sixth step of registering the standard and the corresponding relationship in a database to be referred to in the manufacturing process; (G) a seventh step of referring to the database and determining whether a measurement result by the overlay inspection apparatus using the optical signal satisfies the process control standard; and (h) the measurement result is the An eighth step of subjecting the exposure process in the manufacturing process to reprocessing when the process control standard is not satisfied, and in the eighth step, the measurement result is referred to by referring to the correspondence relationship. The second registration error amount when the first registration error amount is obtained is acquired, and the exposure condition in the manufacturing process is corrected so that the acquired second registration error amount is zero. thing It is characterized by.
[0020]
Claim 3 The described invention is a method for managing a process control standard range by an overlay inspection apparatus using an optical signal, using an overlay deviation amount obtained from an inline electron beam evaluation apparatus using a substrate current signal, a) a first step of measuring a first overlay deviation amount of the lower layer pattern using an overlay inspection apparatus using an optical signal after forming the lower layer pattern; and (b) an inline using a substrate current signal. A second step of measuring a second overlay deviation amount of the lower layer pattern using an electron beam evaluation apparatus; and (c) correspondence between the first overlay deviation amount and the second overlay deviation amount. A third step of specifying a relationship; and (d) determining a process management standard relating to the first overlay deviation amount based on the second overlay deviation amount based on the correspondence relationship. A fourth step that, in the fifth step of registering in a database to be referenced by (e) the process control standards and the relationship manufacturing process, (F) a sixth step of referring to the database and judging whether or not a measurement result by the overlay inspection apparatus using the optical signal satisfies the process control standard; and (g) the measurement result is the When the process control standard is not satisfied, the correspondence relationship is referred to obtain the second overlay deviation amount when the measurement result is the first overlay deviation amount. A seventh step of setting the amount of overlay deviation as an exposure condition in the exposure step for forming an upper layer pattern, It is characterized by.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 shows the overall configuration of a semiconductor manufacturing system to which the semiconductor manufacturing process management method of this embodiment is applied. As shown in the figure, this system includes an in-line electron beam evaluation apparatus 11 using a substrate current signal, an overlay deviation evaluation apparatus 12 using an optical signal, a semiconductor manufacturing apparatus 20, a measurement data collection unit 31, a detection value. A database 32, an apparatus control factor database 33, an apparatus data collection unit 34, a manufacturing process management database 35, a data processing unit 36, and an apparatus control factor setting unit 40 are provided. The semiconductor manufacturing apparatus 20 described above includes, for example, an exposure apparatus 21, an etching apparatus 22, a CMP apparatus 23, a film forming apparatus 24, a heat treatment apparatus 25, an ion implantation apparatus 26, and a cleaning apparatus 27. The measurement data collection unit 31 includes a detection value collection unit 31A and a wafer ID collection unit 31B, and the apparatus data collection unit 34 includes an apparatus control factor data collection unit 34A and a wafer ID collection unit 34B. In addition, a wafer ID database (not shown) is provided.
[0025]
Here, the in-line electron beam evaluation apparatus 11 irradiates an arbitrary beam to be measured on a semiconductor substrate with an electron beam under an arbitrary irradiation condition, detects a substrate current substrate current signal induced at this time, Is a device that calculates the amount of misalignment at the interface between the upper layer pattern and the lower layer pattern in a non-contact manner by performing numerical calculation processing on the device. 311196) is used. This inspection apparatus irradiates a semiconductor substrate with an electron beam as shown in FIG. 2A, and at this time, detects a substrate current signal induced in the semiconductor substrate as shown in FIG. By performing numerical calculation processing, the position information of the edge portion of the upper layer pattern is detected with high accuracy.
[0026]
Further, the inline electron beam evaluation apparatus 11 has a mechanism for reading an identification number (ID) unique to the semiconductor substrate (wafer) that has been evaluated. It has a function to output the number to the outside. This in-line electron beam evaluation apparatus 11 differs from an overlay deviation amount evaluation apparatus 12 using an optical signal, which will be described later, by using a transistor pattern or a wiring pattern existing in an in-chip area (product area). Can be measured.
[0027]
The in-line electron beam evaluation apparatus 11 sequentially irradiates a plurality of measurement positions on the semiconductor substrate with an electron beam having the same shape, and measures a current signal induced when the measurement position is irradiated with the electron beam. Thus, it is possible to store each measurement position and the current signal at the measurement position, and output each overlay displacement amount or base pattern expansion / contraction rate calculated using the current signal as a function of the measurement position. In addition, the output method of the overlay deviation amount or the lower layer pattern expansion / contraction rate as a function of the measurement position is, for example, using the overlay deviation amount or the underlying pattern expansion / contraction rate for each measurement position where the current signal measurement is actually performed. Then, a spatial distribution function related to the overlay deviation amount or the base pattern expansion / contraction rate is calculated, and the overlay deviation amount or the base pattern expansion / contraction rate is output for all positions on the semiconductor substrate. For storing the current signal, the measurement data may be stored as it is, or may be stored after performing arithmetic processing such as sum of products or average.
[0028]
The overlay deviation amount evaluation device 12 irradiates a laser beam or incoherent light to an arbitrary pattern to be measured on a semiconductor substrate, detects a signal from the pattern by a detector such as a CCD camera, and performs an operation. This is a device that calculates the amount of misalignment between the upper layer pattern and the lower layer pattern in a non-contact manner by processing. The so-called box mark position detection is determined from the signal obtained from the detector by an edge detection method such as an inner centroid method, an outer centroid method, or a Fourier seven-point method. Further, the position of the box mark may be determined by moving the correlation model on the measurement waveform obtained from the detector and using the most matched position. This overlay deviation amount evaluation device 12 basically measures the overlay deviation amount using a box mark provided in an area (area on the scribe line) different from the chip area (product area).
[0029]
The semiconductor manufacturing apparatus 20 functions to output the device control factor reflected in the pattern shape on the semiconductor substrate and the ID number of the processing semiconductor substrate to the outside. Further, the semiconductor manufacturing apparatus 20 is configured to be able to control the apparatus control factor by an external signal. Here, for example, in the case of an etching apparatus, the apparatus control factor is a processing time, a gas flow rate, an incident power amount (depending on an upper electrode or a lower electrode), an incident bias amount, an incident high-frequency phase, a wafer holding stage temperature, Point to pressure, etc. In the CMP apparatus, the number of revolutions of the polishing pad, the number of revolutions of the substrate (wafer), the pressure (load) to the substrate with respect to the polishing pad, the pressure (load) region, the supply amount of the chemical reactant, the chemical reactant Indicates the position of the supply nozzle, the supply amount of polishing slurry containing abrasive particles, the position of the polishing slurry supply nozzle containing abrasive particles, the position of the carrier head (including moving speed, etc.), the charge amount of the wafer, the processing time, etc. .
[0030]
The apparatus control factors for the exposure apparatus 21 include, for example, irradiation light quantity (exposure time), focus shift amount, shot magnification, wafer scaling (wafer expansion / contraction), alignment shift amount, wafer rotation (wafer rotation), wafer Orthogonality (wear orthogonality), shot rotation (shot rotation), shot magnification (shot magnification or shot expansion / contraction ratio), distortion matching, wafer and reticle movement speed (scan speed), stage surface temperature (wafer temperature) Point to the stage tilt angle. Also, the device control factors for the cleaning device include, for example, the number of wafer (substrate) rotations, the amount of chemical solution (including pure water) supplied, the amount of wafer charge, the temperature of the chemical solution, the processing time, and the insertion of the wafer into the chemical solution tank・ Indicate the lifting speed and chemical concentration. Further, the device control factors for the film forming device 24 indicate, for example, gas flow rate, wafer temperature (including lamp speed), processing time, incident power amount, wafer moving speed, and the like. Further, the apparatus control factors for the heat treatment apparatus 25 indicate gas flow rate, wafer temperature (including lamp speed), processing time, incident power amount, wafer moving speed, and the like. Further, the device control factors for the ion implantation device 26 indicate a dose amount, implantation energy, wafer temperature, beam scan speed, wafer holder rotation speed, beam current amount, and the like.
[0031]
The detection value collection unit 31A has a function of collecting the overlay deviation amount calculated from the inline electron beam evaluation apparatus 11 and the overlay deviation amount evaluation apparatus 12 and transmitting the overlay deviation amount to the data processing unit 36 using a desired communication protocol. The device control factor data collection unit 34A has a function of collecting each device control factor from the semiconductor manufacturing device 20 and transmitting it to the data processing unit 36 using a desired communication protocol. Further, the wafer ID collection units 31B and 34B collect the identification numbers output from the inline electron beam evaluation apparatus 11, the overlay deviation evaluation apparatus 12, and the semiconductor manufacturing apparatus 20, and use a desired communication protocol as a data processing unit. 36.
The device control factor setting unit 40 receives the device control factor correction value output from the data processing unit 36 and transmits the device control factor correction value to the semiconductor manufacturing device 20 using a desired communication protocol. It has a function to be set in each device.
[0032]
The detection value database 32 records the overlay deviation amount transmitted to the data processing unit 36 by the detection value collecting unit 31A together with the wafer identification number corresponding thereto, and in accordance with a request from the data processing unit 36, a desired overlay is recorded. It has a function of reading the deviation amount and the wafer identification number corresponding to the deviation amount. The device control factor database 33 records the device control factor transmitted to the data processing unit 36 by the device control factor data collecting unit 34A together with the corresponding identification number for each semiconductor manufacturing device (for each unit) and performs data processing. It has a function of reading out a desired device control factor and a corresponding identification number in accordance with a request from the unit 36. The manufacturing process management database 35 accumulates manufacturing process histories of individual semiconductor substrates (wafers) identified by wafer identification numbers, and holds margins (control ranges) of each overlay accuracy in the manufacturing process. is there. Therefore, the overlay deviation amount or device control factor transmitted to the data processing unit 36 by the detection value collecting unit 31A or the device control factor data collecting unit 34A is recorded for each identification number corresponding to the wafer, and data processing is performed. According to the request of the unit 36, it has a function of reading out the overlay deviation amount of the desired identification number and the device control factor.
[0033]
The data processing unit 36 reads and writes the overlay deviation amount / apparatus control factor data and wafer identification number, performs statistical processing on these data to calculate and determine a desired correction value or management range, It has a function of determining whether or not the corresponding data is within the management range. Further, the data processing unit 36 performs (1) shift and (2) wafer scaling on the overlay control factor at the interface portion between the upper layer pattern and the lower layer pattern of the semiconductor substrate (wafer) on which the overlay deviation amount is evaluated. (Wafer Stretch), (3) Wafer Rotation (Wafer Rotation), (4) Wafer Orthogonal Prediction (Wafer Orthogonality), (5) Shot Rotation (Shot Rotation), (6) Shot Magnification (Shot (Scaling factor or shot expansion / contraction ratio), (7) Distortion matching amounts are calculated, and a comparison calculation with a process management index held in the manufacturing process management database 35 is performed to calculate a desired correction. .
[0034]
In addition, the data processing unit 36 searches the manufacturing process management database 35 for a history of measured values or manufacturing process information (including process management indexes), and selects a target from the history / manufacturing process information obtained as a result of the search. A history of overlay deviation of the exposure process or a statistical tendency obtained from the history is calculated. Furthermore, it has a function of estimating a final yield of the semiconductor substrate from the history and the manufacturing process information regarding all semiconductor manufacturing processes including the process.
The semiconductor manufacturing process management system according to the first embodiment includes a plurality of computers (data processing unit 36), a semiconductor manufacturing apparatus 20, an inline electron beam evaluation apparatus 11, and an overlay deviation amount evaluation apparatus connected via a network. 12. It consists of various databases.
[0035]
Next, a semiconductor manufacturing process management method by the above-described semiconductor device manufacturing process management system according to the first embodiment will be described.
In the semiconductor device manufacturing process management method according to the first embodiment, the overlay inspection apparatus using an optical signal is calculated using the overlay deviation amount calculated by the inline electron beam evaluation apparatus using the substrate current signal. In this method, the overlay deviation amount is correctly evaluated by determining the overlay deviation amount to be performed or the process management standard based thereon, and the semiconductor device manufacturing process with a high yield is completed at an early stage.
[0036]
An example of the manufacturing procedure of the semiconductor device using the management method of the present embodiment is shown in FIGS.
FIG. 3 shows the flow of test wafer processing, and FIG. 4 shows the flow of processing in the manufacturing process. The process management standard is determined by the processing from step S111 to step S117 shown in FIG. 3, and the process management of the exposure process is operated using the process management standard by the processing from step S7121 to step S125 shown in FIG.
[0037]
First, a series of processing procedures from step S111 to step S117 will be described in detail. After inserting a test semiconductor substrate (test wafer), the same semiconductor manufacturing process as that of the product wafer is performed (step S111). In step S111, specifically, processes such as film formation, etching, and CMP are performed. At this stage, the lower layer pattern is formed. Here, after the device control factor and wafer ID in the series of semiconductor manufacturing apparatuses 20 used for forming the lower layer pattern are transferred to the data processing unit 36 via the device data collecting unit 34, the device control factor is used. Accumulated in the database 33.
Next, a desired exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process, an exposure process is performed (step S112), and the upper layer pattern is transferred to the photoresist. Here, as shown in FIG. 5, the shot position of the box mark UL of the upper layer pattern is shifted with respect to the box mark LL of the lower layer pattern for each shot, and a plurality of levels are set for the shot shift amount. FIG. 4A shows a case where the upper layer pattern is shifted by −X, FIG. 4B shows a case where the shift amount is zero, and FIG. 4C shows the upper layer pattern with respect to the lower layer pattern. The case where it is shifted by + X is shown. Thus, in the exposure process, exposure is intentionally provided with an offset at the shot position. Here, the apparatus control factor and wafer ID in the exposure apparatus 21 are transferred to the data processing unit 36 via the apparatus data collection unit 34 and then stored in the apparatus control factor database 33.
[0038]
Subsequently, the overlay deviation amount A between the upper layer pattern and the lower layer pattern made of photoresist is measured using the overlay deviation amount evaluation device 12 using an optical signal (step S113). Specifically, as shown in FIG. 5, distances S1 and S2 between the box mark LL of the lower layer pattern and the box mark UL of the upper layer pattern are measured, and a deviation amount A (= S1-S2) is determined from these differences. Is calculated. The deviation A is transferred to the data processing unit 36 through the detection value collecting unit 31A and the wafer ID collecting unit 31B together with the wafer ID of the semiconductor substrate to be measured. In step S113, the measurement is basically performed on a box mark on an area other than the product area (for example, a scribe line area). The overlay deviation amount A is measured for a plurality of levels set in the exposure process.
Subsequently, using the inline electron beam evaluation apparatus 11 using the substrate current signal, the same measurement object as the overlay deviation evaluation apparatus 12 is measured, and the overlay deviation between the upper layer pattern and the lower layer pattern made of photoresist is measured. B is measured (step S114). In step S114, it is possible to carry out the overlay deviation amount using any pattern in the product area (in-chip area).
[0039]
Here, with reference to FIG. 6, the measurement principle of the overlay deviation amount using the inline electron beam evaluation apparatus 11 will be described. An upper view of the box mark is shown in the upper part of the figure, a sectional structure diagram is shown in the middle part of the figure, and a differential waveform of the substrate current signal is shown in the lower part of the figure. The electron beam is scanned from the left to the right in the figure, and the substrate current signal is observed at each scanning position. As shown in the figure, the waveform obtained by differentiating the substrate current signal shows a peak at the edge portion of the lower layer pattern or the upper layer pattern by appropriately selecting the irradiation energy of the electron beam. That is, since the depth from the outermost surface of the edge portion is different between the upper layer pattern and the lower layer pattern, it is necessary to modulate the range of the electron beam. By appropriately modulating the electron beam in this way, the differential waveform shows a peak at each edge portion of the upper layer pattern or the lower layer pattern, and the distance between the box mark LL forming the lower layer pattern and the box mark UL forming the upper layer pattern S1 and S2 can be measured with high accuracy, and therefore, the overlay displacement amount B (= S1-S2) of the upper layer pattern with respect to the lower layer pattern can be calculated with high accuracy. The deviation amount B is transferred to the data processing unit 36 through the detection value collection unit 31A and the wafer ID collection unit 31B together with the wafer ID of the semiconductor substrate to be measured. This overlay deviation amount B is measured for a plurality of levels set during exposure.
In addition, according to the measurement method using an optical signal, since it is affected by the round portion R of the intermediate layer, the signal waveform does not show a peak, so that it becomes difficult to detect the edge portion and measurement accuracy cannot be obtained. become.
[0040]
Subsequently, the data processing unit 36 specifies the correspondence between the measured overlay deviation amount A and overlay deviation amount B (step S115). FIG. 7 shows an example of a correspondence relationship between the deviation amount A and the deviation amount B. In the figure, the horizontal axis represents the deviation amount B measured for each level using the substrate current signal, and the vertical axis represents the deviation amount A measured for each level using the optical signal. Represents. The characteristic lines in the figure are obtained by plotting the deviation A and deviation B measured using the optical signal evaluation device 12 and in-line electron beam evaluation device 11 for the same level. . As described above, the deviation amount B measured using the substrate current signal is extremely accurate and can be regarded as representing a device design value. Accordingly, the correspondence relationship shown in FIG. 7 represents the correspondence relationship between the deviation amount A measured when the optical signal is used and the device design value.
[0041]
Subsequently, the data processing unit 36 determines a process management standard related to the deviation A based on the deviation B based on the above-described correspondence (step S116). Specifically, the upper limit value BU and the lower limit value BL of the process management standard are set in advance by device design. Since the upper limit value BU and the lower limit value BL can be regarded as values on the deviation amount B, the upper limit value AU and the lower limit value AL are defined as the deviation amount A corresponding to the upper limit value BU and the lower limit value BL from the correspondence shown in FIG. can get. These upper limit value AU and lower limit value AL are determined as process management standards of the evaluation device 12 using an optical signal. Here, the deviation amount A using the optical signal is an amount with low measurement accuracy, but since the process management standard for the deviation amount A is determined based on the deviation amount B, the device design value is satisfied as a result. It is possible to correctly determine whether or not the process has been performed, and to improve the quality of process management.
[0042]
Subsequently, the process management standard determined in step S116 is registered in the manufacturing process management database 35 to be referred to in the manufacturing process (step S117), and this database is updated. In addition, when registering the process management standard, it is desirable that each device control factor used for forming the upper layer pattern and the lower layer pattern is associated.
Thus, the process management standard for the first selected exposure apparatus is prepared. Similarly, with respect to other exposure apparatuses, the overlay deviation amount is measured using the optical signal and the substrate current signal, and the process control standard is obtained from the measurement result.
[0043]
Next, a manufacturing process according to the first embodiment will be described with reference to FIG.
After loading the product semiconductor substrate (product wafer), a desired semiconductor manufacturing process is performed in step S121. However, the semiconductor manufacturing process performed in step S121 is the same process as step S111 described above.
Subsequently, one exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process and an exposure process is performed (step S122), and the upper layer pattern is transferred to the photoresist. The exposure apparatus and process conditions selected in step S122 are preferably the same as the exposure apparatus and process conditions selected in step S112. Subsequently, the overlay deviation amount A between the upper layer pattern and the lower layer pattern made of photoresist is measured using the overlay deviation amount evaluation device 12 using an optical signal (step S123). The deviation A is transferred to the data processing unit 36 via the measurement data collecting unit 31 together with the wafer ID of the semiconductor substrate to be measured. Basically, the measurement performed in step S123 is performed on a box mark on an area other than the product area (for example, a scribe line area).
[0044]
Subsequently, the manufacturing process management database 35 is searched for a process management standard based on the overlay inspection apparatus 12 using the optical signal in the product process, and the process management standard updated in the above-described step S117 is the manufacturing process management. The data is transferred from the database 35 to the data processing unit 36. Then, the data processing unit 36 determines whether or not the overlay deviation amount A obtained in step S123 is within the acquired process management standard (step S124). Here, when it is determined that the deviation A is within the process control standard (step S124; YES), this process is completed. On the other hand, if it is determined that it does not fit (out of range) (step S124; NO), the upper layer pattern made of the photoresist formed on the surface of the semiconductor substrate is peeled off and subjected to reprocessing (step). S125). This peeling process is an ashing process or an acid cleaning process. Reprocessing is performed on the semiconductor substrate that has been subjected to the peeling process (step S122).
[0045]
Note that the exposure apparatus selected in step S122 implemented through step S125 is desirably the same exposure apparatus as the exposure apparatus used immediately before the semiconductor substrate. Further, in step S113, step S114, and step S123, the overlay deviation amount evaluation can be performed on a plurality of positions on the semiconductor substrate. FIG. 8 shows an example of how to take measurement points in this case. The measurement positions are located at predetermined intervals, and are often at regular intervals. For example, it may be defined by the repetition interval of the exposure area determined in step S112, or may be the repetition interval of the chip area similarly determined in step S112.
[0046]
In addition, the process control standard determination process in step S116 includes the overlay deviation amount for each measurement position where the optical signal was actually measured in step S113 and the overlay deviation amount for each measurement position where the substrate current signal was measured in step S114. And a spatial distribution function related to the overlay deviation amount may be calculated, and the overlay deviation amount may be calculated for all positions on the semiconductor substrate. For example, it is known that the film formation process in step S111 has a distribution of the film thickness as a whole on the semiconductor substrate. For example, in the exposure process in step S112, it is known that the transferred pattern shape has a distribution as an exposure region. In the determination process in step S124, the determination of the correction value of the overlay control factor may be performed as a function of the position on the semiconductor substrate. The first embodiment has been described above.
[0047]
(Embodiment 2)
The semiconductor device manufacturing process management method according to the second embodiment of the present invention will be described below.
In the first embodiment described above, the process management standard related to the shift amount in the exposure process is defined. In the second embodiment, the process management standard related to the shot magnification or the shot expansion / contraction ratio in the exposure process is obtained, and the shot magnification is further determined. Correct. As a result, process management is performed accurately and yield is improved.
An example of the manufacturing procedure of the semiconductor device using the management method of the second embodiment is shown in FIGS. FIG. 9 shows the flow of test wafer processing, and FIG. 10 shows the flow of processing in the manufacturing process. The process management standard and the correction value for the deviation amount are determined by the processing from step S211 to step S217 shown in FIG. Then, the process management of the exposure process based on the process management standard and the correction value is operated by the processing from step S221 to step S227 shown in FIG.
[0048]
More specifically, first, a series of processing procedures from step S211 to step S217 will be described. After inserting a test semiconductor substrate (test wafer), the same semiconductor manufacturing process as that of the product wafer is performed (step S211). In step S211, specifically, processes such as film formation, etching, and CMP are performed. At this stage, the lower layer pattern is formed. Next, one exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process and an exposure process is performed (step S212), and the upper layer pattern is transferred to the photoresist. As shown in FIG. 11, the main surface of the semiconductor substrate is divided into a plurality of shot regions ST1 to ST42 and exposed. Each shot area corresponds to one exposure area. In the second embodiment, a plurality of levels are provided for the shot magnification by changing the shot magnification for each shot area.
[0049]
A method for setting the level of shot magnification will be described with reference to FIG. The shot area ST shown in FIG. 12 corresponds to each of the shot areas ST1 to ST42 shown in FIG. 11, and the size in the x direction is Lx and the size in the y direction is Ly. The shot area includes a plurality of chip patterns. In addition, measurement points P1 to P4 are provided at the center of the four sides of the shot area ST. At each measurement point, the above-described box mark LL composed of the lower layer pattern and the box mark UL composed of the upper layer pattern are arranged. Here, when the regular shot magnification is employed, the box mark UL is positioned at the center of the box mark LL at each measurement point. When the shot magnification of the upper layer pattern is set larger than that of the lower layer pattern, the box mark UL moves to the outside of the shot area ST as shown in FIG. On the other hand, when the shot magnification is set small, the box mark UL moves to the inside of the shot area ST. Thus, by adjusting the shot magnification of the exposure apparatus, the shot magnification of the shot areas ST1 to ST42 is changed, and a plurality of levels are provided for the shot magnification. The shot magnification is calculated from the amount of deviation of the box mark at each measurement point. This calculation method will be described later.
[0050]
Subsequently, the misalignment amount A is measured from each box mark at the measurement points P1 to P4 provided in each shot area by using the overlay misalignment evaluation device 12 using an optical signal (step S213).
Subsequently, the deviation amount B is measured from each box mark at the measurement points P1 to P4 in each shot area using the inline electron beam evaluation apparatus 11 using the substrate current signal (step S214).
FIG. 13 shows a list of the deviation amounts A and B measured in the above-described steps S213 and S214. In this example, the shift amount A and the shift amount B measured at the measurement points P1 to P4 in a certain shot area are shown in a coordinate format. For example, for the measurement point P1, “AY1” is measured as the y-direction component of the deviation A, and “BY1” is measured as the y-direction component of the deviation B. For example, at the measurement point P3, “AX3” is measured as the x-direction component of the deviation A, and “BX3” is measured as the x-direction component of the deviation B. In this way, the shift amount A and the shift amount B at each measurement point are similarly measured for other shot areas.
[0051]
Subsequently, a correspondence relationship between the expansion / contraction ratio due to the deviation amount A and the expansion / contraction ratio due to the deviation amount B is determined (step S215). The expansion / contraction rate due to each shift amount is calculated from the above measurement result. That is, the expansion / contraction rate MAX in the x direction due to the shift amount A is calculated from the following equation (1), and the expansion / contraction rate MAy in the y direction due to the shift amount A is calculated from the following equation (2). Further, the expansion / contraction rate MBX in the x direction due to the deviation amount B is calculated from the following equation (3), and the expansion / contraction rate MBY in the y direction due to the deviation amount B is calculated from the following equation (4).
MAX = (AX4-AX3) / Lx (1)
MAY = (AY1-AY2) / Ly (2)
MBX = (BX4-BX3) / Lx (3)
MBY = (BY1-BY2) / Ly (4)
[0052]
Using the above equation, the expansion / contraction rate due to the shift amount A and the shift amount B is calculated for each shot region. FIG. 13B shows the expansion / contraction rate of each shot area in a coordinate format. In the same figure, the expansion ratios MAX1, MAX2, MAX3, etc. are the expansion ratios in the x direction due to the shift amount A, and are calculated using the above equation (1). The expansion ratios MAY1, MAY2, MAY3, etc. The expansion / contraction rate in the y direction is calculated using the above equation (2). The expansion ratios MBX1, MBX2, MBX3, etc. are the expansion ratios in the x direction due to the deviation amount B, and are calculated using the above equation (3). The expansion ratios MBY1, MBY2, MBY3, etc. The expansion / contraction ratio in the direction, which is calculated using the above equation (4). By plotting the expansion / contraction rate calculated in this way, the correspondence as shown in FIG. 14 is obtained. Here, (a) in the figure shows the correspondence of the expansion / contraction ratio depending on the deviation amount A and the deviation amount B in the x direction, and (b) in FIG. The correspondence is shown.
[0053]
Subsequently, based on the correspondence relationship between the expansion / contraction ratios described above, a process management standard relating to the expansion / contraction ratio due to the deviation amount A is determined based on the expansion / contraction ratio due to the deviation amount B (step S216). Specifically, using the correspondence shown in FIG. 14A, when the upper limit value MBXU and the lower limit value MBXL of the expansion ratio in the x direction determined by the device design are set as the expansion ratio MBX, the expansion ratio MAX is obtained. An upper limit value MAXU and a lower limit value MAXL are obtained. Similarly, when the upper limit value MBYU and the lower limit value MBYL of the expansion / contraction rate in the y direction determined by device design are set to the expansion / contraction rate MBY using the correspondence relationship shown in FIG. MAYU and lower limit value MAYL are obtained.
[0054]
Here, the expansion / contraction ratios MAX and MAY due to the deviation amount A using the optical signal are low in measurement accuracy, but the process control standard (upper limit value) regarding the expansion / contraction ratio due to the deviation amount A with the expansion ratio due to the deviation amount B as a reference. (MAXU, MAYU and lower limit values MAXL, MAYL) are determined, and as a result, it is possible to correctly determine whether the expansion / contraction ratio in the device design is satisfied, and to improve the quality of process management. become.
Subsequently, the upper limit values MAXU and MAYU and the lower limit values MAXL and MAYL obtained in step S216 described above are registered in the database as process management standards, and this database is updated (step S217).
Thus, the process management standard for the first selected exposure apparatus is prepared. Similarly, with respect to other exposure apparatuses, the overlay deviation amount is measured using the optical signal and the substrate current signal, and the process control standard relating to the expansion / contraction rate is obtained from the measurement result.
[0055]
Next, a manufacturing process according to the second embodiment will be described with reference to FIG.
After introducing the product semiconductor substrate (product wafer), a desired semiconductor manufacturing process is performed in step S221. However, the semiconductor manufacturing process performed in step S221 is the same process as step S211 described above.
Subsequently, one exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process and an exposure process is performed (step S222), and the upper layer pattern is transferred to the photoresist. Note that the exposure apparatus selected in step S222 is preferably the same as the exposure apparatus selected in step S212 described above. Subsequently, the overlay deviation amount A between the upper layer pattern and the lower layer pattern made of photoresist is measured by using the overlay deviation amount evaluation device 12 using an optical signal (step S223), and the expansion / contraction rate due to the deviation amount A is measured. Is calculated. Basically, the measurement performed in step S223 is performed on a box mark on an area other than the product area (for example, a scribe line area).
[0056]
Subsequently, the process management standard based on the overlay inspection apparatus 12 using the optical signal in the product process is searched, and the process management standard updated in step S217 described above is acquired from the database. Then, it is determined whether or not the expansion / contraction rate by the overlay deviation amount A obtained in step S223 is within the acquired process control standard (step S224). Here, when it is determined that the expansion / contraction rate due to the deviation amount A is within the process control standard (step S224; YES), this processing is completed. On the other hand, when it is determined that it does not fit (out of range) (step S224; NO), the upper layer pattern made of the photoresist formed on the surface of the semiconductor substrate is peeled off (step S225). This peeling process is an ashing process or an acid cleaning process.
[0057]
Subsequently, a displacement amount B corresponding to the displacement amount A is obtained from a database having a correspondence relationship between the expansion / contraction rate due to the displacement amount A and the expansion / contraction rate due to the displacement amount B measured in the above-described step S212 and step S213 (step S212). S226).
Subsequently, the correction value of the shot magnification of the exposure apparatus is set so that the expansion / contraction rate due to the shift amount B is zero with reference to the correspondence relationship of the expansion / contraction rate determined in step S215 described above. Specifically, as shown in the following equation, a difference ΔMBX between the center value MBXM (= 0) of the expansion / contraction ratio standard and the actual expansion / contraction ratio MBX calculated in step S223 is calculated, and this difference ΔMBX is calculated in step This is added to the shot magnification MSO of the exposure apparatus used in S222, and this is set as a new shot magnification MSN.
ΔMBX = MBXM (standard value of standard) −MBX (measured value) (5)
MSN (new setting value) = MSO (old setting value) + ΔMBX (correction value) (6)
[0058]
Subsequently, exposure processing is performed using the correction value of the shot magnification set in step S227, and the shot magnification of the exposure apparatus is corrected so that the contraction rate of the upper layer pattern becomes zero with respect to the lower layer pattern. Then, reprocessing (exposure processing) is performed on the semiconductor substrate on which the peeling processing has been performed (step S222). The second embodiment has been described above.
[0059]
(Embodiment 3)
Hereinafter, a semiconductor device manufacturing process management method according to Embodiment 3 of the present invention will be described.
In the first and second embodiments described above, the deviation amount B is measured for the purpose of correcting the process control standard for the deviation amount A. However, in this third embodiment, the deviation is used for the purpose of calibrating the shot magnification of the exposure apparatus. The shot magnification of the exposure apparatus is corrected using the expansion / contraction rate calculated from the amount B.
An example of the manufacturing procedure of the semiconductor device using the management method of the third embodiment is shown in FIGS. FIG. 15 shows the flow of test wafer processing, and FIG. 16 shows the flow of processing in the manufacturing process. A correction value for the shot magnification of the exposure apparatus is determined by the processing from step S311 to step S315 shown in FIG. Then, in the process shown in FIG. 16, the process management of the exposure process by the correction value is used.
[0060]
First, a series of processing procedures from step S311 to step S315 will be described in detail. After inserting a test semiconductor substrate (test wafer), the same semiconductor manufacturing process as that of the product wafer is performed (step S311). In step S311, specifically, processes such as film formation, etching, and CMP are performed. At this stage, the lower layer pattern is formed. Next, one exposure apparatus to be calibrated is selected from a plurality of exposure apparatuses used in the manufacturing process, and an exposure process is performed (step S312), and the upper layer pattern is transferred to the photoresist. . Also in the third embodiment, as in the second embodiment described above, a plurality of levels are provided for the shot magnification by changing each shot magnification for the plurality of shot regions ST1 to ST42 shown in FIG.
Subsequently, the shift amount B is measured from each box mark of the measurement points P1 to P4 of each shot area shown in FIG. 12 using the inline electron beam evaluation apparatus 11 using the substrate current signal (step S313). This deviation amount B is the same as that shown in FIG.
[0061]
Subsequently, a correction value for the shot magnification is determined so that the measured deviation amount B becomes zero (step S314). That is, the correspondence relationship between the set values MSX and MSY of the shot magnification for the exposure apparatus and the expansion / contraction ratios MBX and MBY due to the displacement amount B is obtained, and a new shot magnification is determined from these correspondence relationships so that the displacement amount B is zero. This is used as a correction value. Here, the setting values MSX and MSY of the exposure apparatus shot magnification are grasped from the shot magnification of the exposure apparatus set with respect to the level at which the deviation amount B is measured, and the expansion / contraction ratios MBX and MBY by the deviation amount B are It is calculated from the aforementioned equations (3) and (4). These set values MSX, MSY and expansion / contraction ratios MBX, MBY are shown in a coordinate format in FIG.
[0062]
By plotting the values shown in FIG. 17, the correspondence shown in FIG. 18 is obtained. FIG. 6A is a characteristic diagram showing the correspondence between the set value of the shot magnification MSX of the exposure apparatus in the x direction and the calculated value of the expansion / contraction rate MBX from the shift amount B, and FIG. 6 is a characteristic diagram showing a correspondence relationship between a set value of shot magnification MSY of the exposure apparatus in the direction and a calculated value of expansion / contraction rate MBY from deviation amount B. FIG. From this correspondence, the shot magnifications MSX and MSY with the deviation amount B set to zero, that is, the shot magnifications MSX and MSY when the expansion ratios MBX and MBY are set to zero are determined as correction values, and these are set as new shot magnifications. .
Subsequently, the correction value determined in step S314 is set in the exposure apparatus (step S315).
As described above, the calibration of the shot magnification is performed for the selected one exposure apparatus. Thereby, the shot magnification of the exposure apparatus is optimized so that the overlay deviation amount between the upper layer pattern and the lower layer pattern on the actual semiconductor substrate becomes zero. Calibration is performed on other exposure apparatuses as necessary.
[0063]
Next, a manufacturing process according to the third embodiment will be described with reference to FIG.
After introducing the product semiconductor substrate (product wafer), a desired semiconductor manufacturing process is performed in step S321. However, the semiconductor manufacturing process performed in step S321 is the same process as step S311 described above.
Subsequently, one exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process and an exposure process is performed (step S322), and the upper layer pattern is transferred to the photoresist. The exposure apparatus selected in step S322 is the same as the exposure apparatus selected in step S312 described above, and the shot magnification is calibrated. Thereby, the deviation amount B becomes zero, and the upper layer pattern is formed at an appropriate position with respect to the lower layer pattern. Thereafter, the product wafer processing is completed through a predetermined manufacturing process. The third embodiment has been described above.
[0064]
(Embodiment 4)
The semiconductor device manufacturing process management method according to the fourth embodiment of the present invention will be described below.
In the above-described third embodiment, the deviation amount B between the lower layer pattern and the upper layer pattern is measured to correct the shot magnification of the exposure apparatus. However, in the fourth embodiment, the influence on the etching process is included. The shot magnification of the exposure apparatus is set by measuring the shift amount B and calculating the expansion / contraction rate.
An example of the manufacturing procedure of the semiconductor device using the management method of the fourth embodiment is shown in FIGS. FIG. 19 shows the flow of test wafer processing, and FIG. 20 shows the flow of processing in the manufacturing process. A correction value for the shot magnification of the exposure apparatus is determined by the processing from step S411 to step S416 shown in FIG. In the process shown in FIG. 20, the process management of the exposure process using the correction value is used.
[0065]
First, a series of processing procedures from step S411 to step S416 will be described in detail. After inserting a test semiconductor substrate (test wafer), the same semiconductor manufacturing process as that of the product wafer is performed (step S411). In step S411, specifically, processes such as film formation, etching, and CMP are performed. At this stage, the lower layer pattern is formed. Next, one exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process and an exposure process is performed (step S412), and the upper layer pattern is transferred to the photoresist. In the fourth embodiment, the shot magnifications for the plurality of shot regions ST1 to ST42 shown in FIG. 11 are the same, and the shot magnification is changed for each semiconductor substrate (wafer), thereby providing a plurality of levels for the shot magnification.
[0066]
Subsequently, as shown in FIG. 21B, etching is performed using the developed upper layer pattern L4 made of photoresist as a mask to form holes H in the intermediate layer L3 (step S413). This etching process may include resist stripping.
In the example shown in FIG. 21B, the hole H is formed in a state where the bottom of the hole H and the lower layer pattern L1 are aligned. This is to correct the shot magnification as will be described later. In step S413, the formation state of the hole H differs depending on each level.
[0067]
Subsequently, the deviation amount B is measured for each level using the inline electron beam evaluation apparatus 11 using the substrate current signal (step S414). The deviation B is measured at the measurement points P1 to P4 of each shot area shown in FIG. 12, and the box mark in this case has a cross-sectional structure shown in FIG. From this box mark, a deviation amount B between the bottom surface of the hole H and the lower layer pattern L1 is measured. Here, the measured deviation amount B is measured in correspondence with the position in the same semiconductor substrate for each level. As a result, a deviation amount B for a plurality of shot magnifications is obtained in correspondence with each shot region of the semiconductor substrate.
[0068]
Subsequently, a correction value for the shot magnification is determined so that the measured deviation amount B becomes zero (step S415). That is, using the same method as in the above-described third embodiment, the correspondence relationship between the set values MSX and MSY of the shot magnification for the exposure apparatus and the expansion / contraction ratios MBX and MBY due to the displacement amount B is obtained, and the deviation from these correspondence relationships is obtained. A new shot magnification is determined so that the amount B is zero, and this is used as a correction value. The shot magnification which is this correction value is calculated for each shot area as shown in FIG.
Subsequently, the shot magnification of the exposure apparatus is corrected using the correction value determined in step S415 (step S416).
As described above, the shot magnification corrected for each shot area is set for one selected exposure apparatus, and thereby, the overlay deviation amount of the upper layer pattern and the lower layer pattern is zero over the entire surface of the semiconductor substrate. Thus, the shot magnification of the exposure apparatus is optimized.
[0069]
Next, a manufacturing process according to the fourth embodiment will be described with reference to FIG.
After loading the product semiconductor substrate (product wafer), a desired semiconductor manufacturing process is performed in step S421. However, the semiconductor manufacturing process performed in step S421 is the same process as step S411 described above.
Subsequently, one exposure apparatus is selected from a plurality of exposure apparatuses used in the manufacturing process and an exposure process is performed (step S422), and the upper layer pattern is transferred to the photoresist.
Subsequently, an etching process is performed (S423). However, the etching process performed in step S423 is the same as that in step S413 described above.
Here, the exposure apparatus selected in step S422 is the same as the exposure apparatus selected in step S312 described above, and the shot magnification is corrected for each shot area. Thereby, the shift amount B in each shot area after the etching process becomes zero, and the upper layer pattern is formed at an appropriate position with respect to the lower layer pattern as shown in FIG. Thereafter, the product wafer processing is completed through a predetermined manufacturing process. The fourth embodiment has been described above.
[0070]
(Embodiment 5)
The semiconductor device manufacturing process management method according to the fifth embodiment of the present invention will be described below.
In the above-described fourth embodiment, the amount of deviation B between the lower layer pattern and the upper layer pattern is set to zero by correcting the shot magnification of the exposure apparatus. However, in this fifth embodiment, the processing conditions ( By correcting the etching conditions, the same effect as that obtained when the shot magnification is corrected is obtained.
An example of the manufacturing procedure of the semiconductor device using the management method of the fifth embodiment is shown in FIGS. FIG. 22 shows the flow of test wafer processing, and FIG. 23 shows the flow of processing in the manufacturing process. The correction value for the etching condition is determined by the processing from step S511 to step S516 shown in FIG. Then, in the process shown in FIG. 22, the process management of the etching process using the correction value is operated.
[0071]
First, a series of processing procedures from step S511 to step S516 will be described in detail. After inserting a test semiconductor substrate (test wafer), the same semiconductor manufacturing process as that of the product wafer is performed (step S511). In step S511, specifically, processes such as film formation, etching, and CMP are performed. At this stage, the lower layer pattern is formed. Next, an exposure process is performed using an exposure apparatus used in the manufacturing process (step S512), and the upper layer pattern is transferred to the photoresist. The exposure conditions at this time are the same as those in the manufacturing process.
[0072]
Subsequently, as shown in FIG. 21B, etching is performed using the developed upper layer pattern L4 made of photoresist as a mask to form holes H in the intermediate layer L3 (step S513). In the fifth embodiment, a plurality of levels are provided for the etching conditions by changing the etching conditions for each semiconductor substrate.
In the example shown in FIG. 21B, the hole H is formed in a state where the bottom portion of the hole H and the lower layer pattern L1 are aligned. However, in step S513, the formation state of the hole H depends on each level. Is different.
[0073]
Subsequently, the deviation amount B is measured for each level using the inline electron beam evaluation apparatus 11 using the substrate current signal (step S514). This deviation amount B is measured at the measurement points P1 to P4 of each shot area shown in FIG. 12, and the box mark in this case is the same as that in the fourth embodiment described above, as shown in FIG. It has the cross-sectional structure shown. From this box mark, a deviation amount B between the bottom surface of the hole H and the lower layer pattern L1 is measured. Here, the measured deviation B is measured for each level, and the deviation B for each etching condition is obtained.
[0074]
Subsequently, a correction value of the etching condition is determined so that the deviation amount B becomes zero (step S515). That is, using the same method as in the third embodiment, as shown in FIG. 24, the expansion / contraction ratios MBX and MBY according to the deviation amounts B obtained under the respective etching conditions E1, E2, and E3 are calculated. In FIG. 24, for example, the etching condition E1 is applied to the semiconductor substrate (wafer No.) WF1, and the expansion / contraction ratios MBX1 and MBY1 with the deviation amount B are obtained with respect to the etching condition E1. When the etching conditions and the expansion / contraction rate shown in FIG. 24 are plotted, a characteristic diagram showing the correspondence shown in FIG. 25 is obtained. In the figure, the horizontal axis represents the etching conditions, the left vertical axis represents the x-direction expansion / contraction rate MBX, and the right vertical axis represents the y-direction expansion / contraction rate MBY. From FIG. 25, the etching condition E when the expansion ratios MBX and MBY are set to zero is obtained, and this is set as a correction value for the etching condition.
Subsequently, the etching condition of the etching apparatus is corrected using the correction value determined in step S515 (step S516).
As described above, the corrected etching conditions are set for the etching apparatus, whereby the etching conditions are optimized so that the deviation amount B of the hole bottom with respect to the lower layer pattern becomes zero and the expansion / contraction rate becomes zero.
[0075]
Next, a manufacturing process according to the fifth embodiment will be described with reference to FIG.
After introducing the product semiconductor substrate (product wafer), a desired semiconductor manufacturing process is performed in step S521. However, the semiconductor manufacturing process performed in step S521 is the same process as step S511 described above.
Subsequently, an exposure process is performed (step S522), and the upper layer pattern is transferred to the photoresist. However, the exposure process performed in step S522 is the same process as step S512 described above.
Subsequently, an etching process is performed (S523). Here, the etching conditions used in step S523 are set in the above-described step S516, and as a result, similarly to the case shown in FIG. The deviation amount B from the pattern becomes zero, and each layer is formed at an appropriate position. Thereafter, the product wafer processing is completed through a predetermined manufacturing process. The fifth embodiment has been described above.
[0076]
(Embodiment 6)
Hereinafter, a semiconductor device manufacturing process management method according to the sixth embodiment of the present invention will be described.
In the first to fifth embodiments described above, the semiconductor device manufacturing process management method is described in which the amount of deviation between the lower layer pattern and the upper layer pattern is directly measured and controlled to be zero. However, in the sixth embodiment, the amount of deviation from the set dimension (design value) related to the lower layer pattern is measured in the preceding manufacturing process, and the intentional deviation in the preceding manufacturing process is intentionally performed in the subsequent manufacturing process. A semiconductor device manufacturing process management method will be described in which an upper layer pattern is formed with a shift amount equivalent to the amount, thereby indirectly setting the shift amount between the upper layer pattern and the lower layer pattern to zero. As a result, process management is performed without reprocessing, and the yield is improved.
[0077]
An example of the manufacturing procedure of the semiconductor device using the management method of the sixth embodiment is shown in FIGS. FIG. 26 shows the flow of test wafer processing, and FIG. 27 shows the flow of processing in the manufacturing process. The process management standard is determined and updated by the processing from step S611 to step S616 shown in FIG. Then, the process management of the exposure process according to the process management standard is operated by the processing from step S621 to step S626 shown in FIG.
First, a series of processing procedures from step S611 to step S616 will be described in detail. After inserting a test semiconductor substrate (test wafer), the same semiconductor manufacturing process as that of the product wafer is performed (step S611). In step S611, specifically, processes such as film formation, etching, and CMP are performed. At this stage, the lower layer pattern is formed. Here, in the sixth embodiment, the box mark is designed in advance so that the expansion / contraction rate can be measured from the distance between the lower layer patterns, and the processing conditions in step S611 are set so that a plurality of expansion / contraction rates can be obtained. Establish a level.
[0078]
Subsequently, by using the overlay deviation amount evaluation device 12 using an optical signal, the set dimension and the actual semiconductor substrate (wafer) to be measured are measured with respect to the lower layer pattern from the box mark provided in each shot area. The deviation A is measured (step S612), and using the in-line electron beam evaluation apparatus 11 using the substrate current signal, the set dimensions relating to the lower layer pattern and the actual semiconductor substrate to be measured are similarly determined from the box marks of each shot area. The deviation amount B from the (wafer) is measured (step S613). Subsequently, the deviation amount A and the deviation amount B are transferred to the data processing unit 36 via the measurement data collecting unit 31, and the correspondence relationship between the expansion / contraction rate due to the deviation amount A and the expansion / contraction rate due to the deviation amount B is determined ( Step S615). The calculation method (principle) of the expansion / contraction rate is the same as that in the second embodiment. Subsequently, based on the correspondence relationship between the expansion / contraction ratios described above, a process management standard relating to the expansion / contraction ratio due to the deviation amount A is determined based on the expansion / contraction ratio due to the deviation amount B (step S615). Finally, the process management standard obtained in step S615 described above is registered in the manufacturing process management database 35, and this database is updated (step S616). As described above, the preparation of the process management standard relating to the process before the exposure process is made.
[0079]
Next, a manufacturing process according to the sixth embodiment will be described with reference to FIG.
After loading the product semiconductor substrate (product wafer), a desired semiconductor manufacturing process is performed in step S621. However, the semiconductor manufacturing process performed in step S621 is the same process as step S611 described above. Subsequently, by using the overlay deviation amount evaluation device 12 using an optical signal, the deviation A between the set dimension relating to the lower layer pattern and the actual semiconductor substrate (wafer) to be measured is measured from the interval between the lower layer patterns. In step S622, the data processing unit 36 calculates the expansion / contraction rate based on the deviation A. Basically, the measurement performed in step S622 is performed on a box mark on an area other than the product area (for example, a scribe line area).
[0080]
Subsequently, the process management standard based on the overlay inspection apparatus 12 using the optical signal in the product process is searched, and the process management standard updated in the above-described step S616 is acquired from the manufacturing process management database 35. Then, it is determined whether or not the expansion / contraction rate based on the overlay deviation amount A calculated in step S622 is within the acquired process control standard (step S623). Here, when it is determined that the expansion / contraction rate due to the deviation amount A is within the process control standard (step S623; YES), an exposure process for forming an upper layer pattern is performed using the initially set exposure conditions. (Step S626).
[0081]
On the contrary, when it is determined that the expansion / contraction rate due to the deviation amount A is not within the process control standard (out of the range) (step S623; NO), the expansion / contraction due to the deviation amount A is the same as in the second embodiment. The expansion / contraction rate from the deviation amount B corresponding to the expansion / contraction rate from the deviation amount A measured in step S622 is acquired from the manufacturing process management database 35 that stores the correspondence between the rate and the expansion / contraction rate due to the deviation amount B (step S622). S624). Subsequently, the expansion / contraction rate by the deviation amount B acquired from the manufacturing process management database 35 is set to the shot magnification of the exposure apparatus (step S625). Subsequently, exposure processing for forming an upper layer pattern is performed using the shot magnification set in step S625 (step S626). As a result, the overlay deviation amount of the upper layer pattern becomes zero with respect to the lower layer pattern.
According to the sixth embodiment, the deviation amount B is obtained from the database using the set dimension related to the lower layer pattern measured before the exposure process and the deviation amount A of the measurement target, and the expansion / contraction rate by the deviation amount B is obtained. Since the shot magnification used in the exposure process for forming the upper layer pattern in the subsequent process is set, the process can be managed accurately without reprocessing. The sixth embodiment has been described above.
[0082]
Below, the effect by embodiment which concerns on this invention is supplementarily demonstrated.
Conventional box marks have various drawbacks, making it difficult to measure the amount of positional deviation with sufficient accuracy. As one of the major factors that influence the measurement accuracy of the alignment between the lower layer (underlying) pattern and the upper layer (uppering) pattern, the cross-sectional shape asymmetry of the box mark is raised. As shown in FIG. 2A, in the case of a box mark having an asymmetric upper layer pattern, the outline of the box mark by a conventional optical overlay inspection apparatus becomes ambiguous, and in particular, the value of shot magnification (shot magnification). A large error will occur. This asymmetry of the box mark is caused by various manufacturing processes of the semiconductor device. Various manufacturing processes have pattern density dependency, size dependency, and position dependency (in the wafer surface or in the shot surface). For this reason, overlay misalignment measurement marks provided in areas other than areas (chip areas or product areas) in which elements such as transistors are formed (for example, on scribe lines) (typically box marks) are identically symmetric. Not formed in shape.
[0083]
This pattern cross-sectional asymmetry is due to proximity effects and lens aberrations in the exposure process, microloading effects in the etching process, coverage asymmetry in the film forming process, and reflow asymmetry or box mark constituent material in the heat treatment process. Due to the occurrence of distortion due to the difference in thermal expansion coefficient, the CMP process causes the substrate surface polishing characteristics depending on the pattern arrangement. As described above, depending on the presence or absence of asymmetry in the cross-sectional shape, depending on the conventional evaluation apparatus using the optical signal, the overlay deviation amount detected from the box mark provided in a region different from the chip region, and the actual chip There is a difference between the overlay deviation amounts in the region, and the deviation amounts cannot be measured correctly. On the other hand, according to the embodiment of the present invention, since the edge of the box mark is detected using the substrate current, it is possible to accurately measure the shift amount.
[0084]
Further, according to the overlay inspection apparatus using the optical signal, it is not possible to measure the overlay displacement amount of the pattern in the chip area with a desired accuracy. The reason is that an overlay inspection apparatus using an optical signal measures overlay deviation by measuring a mark having a size of 10 microns or more typified by a box mark arranged in an area outside a chip (such as a scribe line). This is because the amount is calculated. Basically, it is impossible to place an overlay measurement mark with a size of 10 microns or more in an in-chip area where the area is severely constrained, and as described above, in an area outside the chip (for example, a scribe line area). Has been placed. In particular, in an exposure process in which a scanner type exposure apparatus is used, an overlay deviation amount calculated by an overlay measurement mark (for example, a box mark) arranged in an area outside the chip and an overlay in the pattern in the chip area. Since there is a large difference between the deviation amounts, the process management cannot be performed sufficiently. On the other hand, according to the embodiment of the present invention, since the deviation amount B is measured using the substrate current, the deviation amount can be measured using the pattern in the in-chip region. Therefore, it becomes possible to carry out process management strictly.
[0085]
Furthermore, in recent years, the number of masks for creating a semiconductor integrated circuit has increased rapidly, and the number of box marks formed on the scribe line region has increased, and the area occupied by the box marks tends to increase. As a result, when the conventional box mark is used, the area itself occupied by the box mark on the wafer becomes too large, and the area ratio occupied by the actual product chip is relatively decreasing. On the other hand, according to the embodiment of the present invention, it is possible to measure the amount of deviation using the pattern in the chip region, so there is no need to provide a box mark on the outer periphery of the chip. Therefore, the restriction by the box mark is eliminated. It is also possible to measure the amount of deviation using an extremely small box mark.
[0086]
【The invention's effect】
As described above, the present invention has the following effects.
That is, according to the present invention, it is possible to appropriately set and evaluate the process management index (margin) of the process variation regarding the overlay accuracy when the patterns formed from various thin film materials in the semiconductor device manufacturing process are stacked. Therefore, it is possible to accurately and promptly determine the quality of the product in the semiconductor device manufacturing process.
Further, according to the present invention, by measuring the overlay component of the semiconductor substrate processed in the semiconductor manufacturing process, and by optimizing the device control factor of a desired semiconductor manufacturing apparatus according to the measured value, The start-up of the semiconductor device manufacturing process with a high yield can be completed early, and the semiconductor device manufacturing process with a high yield can always be maintained.
The reason is that the semiconductor manufacturing process management system according to the present invention includes an in-line electron beam evaluation apparatus using a substrate current signal that can calculate the amount of overlay deviation at the interface portion between the upper layer pattern and the lower layer pattern. And a semiconductor manufacturing apparatus (including an exposure apparatus) capable of reading and writing apparatus control factors, and using the overlay deviation amount and the process control index, a semiconductor substrate processed in the semiconductor manufacturing process This is because the configuration includes a data processing unit for setting pass / fail judgment, calculation / setting of correction values related to the process control index or the device control factor.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor device manufacturing process management system according to a first embodiment.
FIG. 2 is a diagram for explaining the measurement principle of the inline electron beam evaluation apparatus according to the first embodiment.
FIG. 3 is a flowchart showing a flow of test wafer processing according to the first embodiment.
FIG. 4 is a flowchart showing a flow of product wafer processing according to the first embodiment.
FIG. 5 is a diagram for explaining box marks for measuring overlay deviation amounts A and B according to the first embodiment.
6 is a diagram for explaining the principle of measurement of overlay deviation amounts A and B according to Embodiment 1. FIG.
7 is a characteristic diagram showing a correspondence relationship between a deviation amount A and a deviation amount B according to Embodiment 1. FIG.
8 is a diagram showing an image of a semiconductor substrate (wafer) according to the first embodiment, and is a diagram showing an example of how to take measurement points for deviation amounts A and B. FIG.
FIG. 9 is a flowchart showing a flow of test wafer processing according to the second embodiment.
FIG. 10 is a flowchart showing a flow of product wafer processing according to the second embodiment.
FIG. 11 is a diagram showing an arrangement of shot areas according to the second embodiment.
FIG. 12 is a diagram showing a box mark according to the second embodiment and is a diagram for explaining a method for setting a shot magnification level;
FIG. 13 is a diagram illustrating a measured value of a deviation amount and a calculated value of an expansion / contraction rate according to the second embodiment.
FIG. 14 is a diagram illustrating a correspondence relationship between expansion / contraction ratios according to a deviation amount A and a deviation amount B according to the second embodiment.
FIG. 15 is a flowchart showing a flow of test wafer processing according to the third embodiment.
FIG. 16 is a flowchart showing a flow of product wafer processing according to the third embodiment.
FIG. 17 is a diagram showing set values MSX, MSY and expansion / contraction ratios MBX, MBY according to the third embodiment in a coordinate format.
FIG. 18 is a characteristic diagram showing a correspondence relationship between set values of shot magnifications MSX and MSY of the exposure apparatus and calculated values of expansion / contraction ratios MBX and MBY from a deviation amount B.
FIG. 19 is a flowchart showing a flow of test wafer processing according to the fourth embodiment.
FIG. 20 is a flowchart showing a flow of product wafer processing according to the fourth embodiment.
FIG. 21 is a diagram for explaining a correspondence relationship between a shot magnification and a shot region and a cross section of each layer stacked on a semiconductor substrate according to the fourth embodiment.
FIG. 22 is a flowchart showing a flow of test wafer processing according to the fifth embodiment.
FIG. 23 is a flowchart showing a flow of product wafer processing according to the fifth embodiment.
24 is a diagram showing etching conditions (E1, E2, E3) for each semiconductor substrate according to the fifth embodiment and expansion / contraction ratios MBX, MBY depending on a deviation amount B. FIG.
FIG. 25 is a characteristic diagram showing a relationship between etching conditions E and expansion ratios MBX and MBY according to the fifth embodiment.
FIG. 26 is a flowchart showing a flow of test wafer processing according to the sixth embodiment.
FIG. 27 is a flowchart showing a flow of product wafer processing according to the sixth embodiment.
FIG. 28 is a flowchart showing the flow of wafer processing according to the prior art.
FIG. 29 is a diagram for explaining a hole formation state in an etching process, and a diagram for explaining misalignment occurring in the etching process.
[Explanation of symbols]
11; Inline electron beam evaluation apparatus (evaluation apparatus using substrate current), 12; Evaluation apparatus using optical signal, 20; Semiconductor manufacturing apparatus, 21; Exposure apparatus, 22; Etching apparatus, 23; CMP apparatus, 24; Deposition apparatus 25; Heat treatment apparatus 26; Ion implantation apparatus 27; Cleaning apparatus 31; Measurement data collection section 31A; Detection value collection section 31B; Wafer ID collection section 32; Detection value database 33; Control factor database 34; Device data collection unit 34A; Device control factor data collection unit 34B; Wafer ID collection unit 35; Manufacturing process management database 36; Data processing unit (computer) 40; Device control factor setting unit .

Claims (3)

A method of managing a process control standard range by an overlay inspection apparatus using an optical signal, using an overlay deviation amount obtained from an inline electron beam evaluation apparatus using a substrate current signal,
(A) a first step of performing an exposure process for transferring an upper layer pattern made of a photoresist after forming a lower layer pattern;
(B) a second step of measuring a first overlay deviation amount between the lower layer pattern and the upper layer pattern using an overlay inspection apparatus using an optical signal;
(C) a third step of measuring a second overlay deviation amount between the lower layer pattern and the upper layer pattern using an inline electron beam evaluation apparatus using a substrate current signal;
(D) a fourth step of specifying a correspondence relationship between the first overlay deviation amount and the second overlay deviation amount;
(E) a fifth step of determining a process management standard relating to the first overlay deviation amount based on the second overlay deviation amount based on the correspondence relationship;
(F) a sixth step of registering the process control standard in a database to be referred to in the manufacturing process;
(G) a seventh step of referring to the database and determining whether or not a measurement result by the overlay inspection apparatus using the optical signal satisfies the process control standard;
(H) an eighth step of subjecting the exposure process to reprocessing when the measurement result does not satisfy the process control standard;
A method of managing a semiconductor manufacturing process , comprising : A method of managing a process control standard range by an overlay inspection apparatus using an optical signal, using an overlay deviation amount obtained from an inline electron beam evaluation apparatus using a substrate current signal,
(A) a first step of performing an exposure process for transferring an upper layer pattern made of a photoresist after forming a lower layer pattern;
(B) a second step of measuring a first overlay deviation amount between the lower layer pattern and the upper layer pattern using an overlay inspection apparatus using an optical signal;
(C) a third step of measuring a second overlay deviation amount between the lower layer pattern and the upper layer pattern using an inline electron beam evaluation apparatus using a substrate current signal;
(D) a fourth step of specifying a correspondence relationship between the first overlay deviation amount and the second overlay deviation amount;
(E) a fifth step of determining a process management standard relating to the first overlay deviation amount based on the second overlay deviation amount based on the correspondence relationship;
(F) a sixth step of registering the process management standard and the correspondence relationship in a database to be referred to in a manufacturing process;
(G) a seventh step of referring to the database and determining whether or not a measurement result by the overlay inspection apparatus using the optical signal satisfies the process control standard;
And (h) an eighth step of subjecting the exposure process in the manufacturing process to reprocessing when the measurement result does not satisfy the process control standard,
In the eighth step, referring to the correspondence relationship, the second overlay deviation amount when the measurement result is the first overlay deviation amount is obtained, and the obtained second overlay deviation is obtained. A semiconductor manufacturing process management method , wherein exposure conditions in the manufacturing process are corrected so that an overlay deviation amount is zero . A method of managing a process control standard range by an overlay inspection apparatus using an optical signal, using an overlay deviation amount obtained from an inline electron beam evaluation apparatus using a substrate current signal,
(A) a first step of measuring a first overlay deviation amount of the lower layer pattern using an overlay inspection apparatus using an optical signal after forming the lower layer pattern;
(B) a second step of measuring a second overlay deviation amount of the lower layer pattern using an inline electron beam evaluation apparatus using a substrate current signal;
(C) a third step of specifying a correspondence relationship between the first overlay deviation amount and the second overlay deviation amount;
(D) a fourth step of determining a process management standard related to the first overlay deviation amount on the basis of the correspondence relationship, with the second overlay deviation amount as a reference;
(E) a fifth step of registering the process management standard and the correspondence relationship in a database to be referred to in a manufacturing process;
(F) a sixth step of referring to the database to determine whether a measurement result by the overlay inspection apparatus using the optical signal satisfies the process control standard;
(G) Obtaining the second overlay deviation amount when the measurement result is the first overlay deviation amount with reference to the correspondence when the measurement result does not satisfy the process control standard. A seventh step of setting the acquired second overlay deviation amount as an exposure condition in the exposure step for forming the upper layer pattern;
A method of managing a semiconductor manufacturing process , comprising :

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