WO2007088587A1 - Semiconductor measuring apparatus and semiconductor measuring method - Google Patents

Semiconductor measuring apparatus and semiconductor measuring method Download PDF

Info

Publication number
WO2007088587A1
WO2007088587A1 PCT/JP2006/301545 JP2006301545W WO2007088587A1 WO 2007088587 A1 WO2007088587 A1 WO 2007088587A1 JP 2006301545 W JP2006301545 W JP 2006301545W WO 2007088587 A1 WO2007088587 A1 WO 2007088587A1
Authority
WO
WIPO (PCT)
Prior art keywords
waveform
semiconductor
hole
substrate
electron beam
Prior art date
Application number
PCT/JP2006/301545
Other languages
French (fr)
Japanese (ja)
Inventor
Keizo Yamada
Yeong Uk Ko
Original Assignee
Topcon Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Topcon Corporation filed Critical Topcon Corporation
Priority to CN2006800509087A priority Critical patent/CN101356635B/en
Priority to KR1020087016766A priority patent/KR101085413B1/en
Priority to PCT/JP2006/301545 priority patent/WO2007088587A1/en
Priority to JP2007556727A priority patent/JP5005551B2/en
Publication of WO2007088587A1 publication Critical patent/WO2007088587A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor

Definitions

  • the present invention relates to a semiconductor measurement apparatus and a semiconductor measurement method using an electron beam, and particularly to a measurement technique suitable for evaluating a fine structure such as a contact hole.
  • One of the fine structures of semiconductor devices is a contact hole.
  • This contact hole forms part of a wiring structure for electrically connecting, for example, a transistor and another electric element formed in the silicon substrate.
  • a method for measuring the structure of this contact hole a method using an electron beam is generally used, and CD SEM is widely known as this type of apparatus.
  • the surface of a semiconductor substrate on which a microstructure to be measured is formed is scanned in a line shape with an electron beam, and secondary electrons generated at that time are detected and a fine waveform is obtained from a waveform. Measure the structure.
  • This secondary electron waveform contains information about the edge of the microstructure, and this edge is recognized as a contrast difference.
  • the surface of the semiconductor substrate is scanned with an electron beam, and the waveform force of the substrate current generated at that time is determined.
  • this substrate current since the substrate current is induced by the electron beam that has passed through the inside of the hole and reached the semiconductor substrate, this substrate current includes information on the internal structure of the hole. From the current waveform, You can know the internal structure of the hall.
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-026449
  • An object of the present invention is to provide a semiconductor measuring apparatus capable of correctly measuring the structure of the hole bottom even if the structure of the hole bottom is complicated.
  • a semiconductor measurement apparatus irradiates a semiconductor substrate with an electron beam, and forms a fine pattern formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam.
  • a semiconductor measurement apparatus configured to obtain an evaluation value of a structure, wherein the evaluation value of the microstructure is obtained based on a waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform Means are provided.
  • the fine structure is a hole
  • the evaluation means extracts the waveform force of the substrate current and the edge of the hole.
  • the evaluation unit calculates an evaluation value of the hole from an edge of the hole.
  • the evaluation unit extracts a peak force of the waveform of the substrate current and an edge of the hole.
  • the semiconductor measurement apparatus irradiates a semiconductor substrate with an electron beam, and obtains an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam.
  • the semiconductor measurement apparatus configured as described above includes an evaluation unit that obtains an evaluation value of the microstructure based on an integrated waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform. It is characterized by.
  • the fine structure is a hole
  • the evaluation unit extracts the integrated waveform force and an edge of the hole.
  • the evaluation unit calculates an evaluation value of the hole from an edge of the hole.
  • the semiconductor measurement apparatus according to the present invention irradiates a semiconductor substrate with an electron beam, and obtains an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam.
  • a semiconductor measurement apparatus configured as described above, wherein an equivalent circuit of the microstructure is specified based on a waveform of the substrate current, and an evaluation value of the microstructure is obtained based on a waveform obtained using the equivalent circuit An evaluation means is provided.
  • the fine structure is a hole
  • the evaluation unit extracts a waveform force obtained by using the equivalent circuit, and an edge of the hole is extracted.
  • the evaluation unit calculates an evaluation value of the hole from an edge of the hole.
  • the semiconductor measurement method irradiates a semiconductor substrate with an electron beam, and obtains an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam.
  • a semiconductor measurement method is characterized in that an evaluation value of the microstructure is obtained based on a waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.
  • FIG. 1 is a configuration diagram of a semiconductor measuring device according to a first embodiment of the present invention.
  • FIG. 2 is a flowchart showing the flow of operation of the semiconductor measuring apparatus according to the first embodiment of the present invention.
  • FIG. 3A is a diagram showing a first example of a hole structure (normal structure) to be measured according to the first embodiment of the present invention.
  • FIG. 3B is a diagram showing a second example of a hole structure (a structure having a gate) to be measured according to the first embodiment of the present invention.
  • FIG. 3C is a diagram showing a third example of a hole structure (a structure having a floating gate) to be measured according to the first embodiment of the present invention.
  • FIG. 4A A diagram showing a first example of a waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
  • FIG. 4B A diagram showing a second example of the waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
  • FIG. 4C A diagram showing a third example of the waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
  • FIG. 4D is a diagram showing a fourth example of the waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
  • FIG. 5A is an equivalent circuit diagram of the hole structure of the first example according to the first embodiment of the present invention.
  • FIG. 5B] is an equivalent circuit diagram of the hole structure of the second example according to the first embodiment of the present invention.
  • FIG. 5C is an equivalent circuit diagram of the hole structure of the third example according to the first embodiment of the present invention.
  • FIG. 6A] A differential circuit diagram for explaining the basic principle of the semiconductor measuring device according to the first embodiment of the present invention.
  • FIG. 6C is an output waveform diagram of the differentiating circuit for explaining the basic principle of the semiconductor measuring device according to the first embodiment of the present invention.
  • FIG. 7A is an explanatory diagram of a substrate current generation mechanism (image charge formation period) according to the first embodiment of the present invention.
  • FIG. 7B is an explanatory diagram of a substrate current generation mechanism (initial tunnel current formation) according to the first embodiment of the present invention.
  • FIG. 7C is an explanatory diagram of a substrate current generation mechanism (late tunnel formation) according to the first embodiment of the present invention.
  • FIG. 7D is an explanatory diagram of the generation mechanism (discharge period) of the substrate current according to the first embodiment of the present invention.
  • Waveform force of substrate current according to the first embodiment of the present invention is an explanatory diagram of the principle of extracting the edge of a contact hole.
  • FIG. 9 is a flowchart showing a flow of operations of the semiconductor measuring apparatus according to the second embodiment of the present invention. It is
  • O 10 A flow chart showing the flow of operation of the semiconductor measuring apparatus according to the third embodiment of the present invention.
  • FIG. 11 is a diagram showing an equivalent circuit of a hole structure which is a measurement target of the semiconductor measurement apparatus according to the third embodiment of the present invention.
  • FIG. 12 is a characteristic diagram showing a non-linear relationship between the electron beam irradiation amount and the surface potential when an electron beam is irradiated onto the hole structure that is the measurement object according to the third embodiment of the present invention. Explanation of symbols
  • FIG. 1 shows the configuration of the semiconductor measuring apparatus according to the first embodiment of the present invention.
  • This semiconductor measuring apparatus irradiates a semiconductor substrate, which is a measurement object (sample), with an electron beam, measures a substrate current induced by the electron beam, and forms a hole formed in the semiconductor substrate from the substrate current.
  • the basic principle is to obtain an evaluation value of the microstructure such as
  • an electron gun 10 that generates an electron beam EB is attached to an upper portion of a chamber 20 that houses a semiconductor substrate 23 that is a measurement object (sample).
  • the electron gun 10 includes an electron beam source 11, and a high voltage power source 40 is connected to the electron beam source 11.
  • a condenser lens 12, an aperture 13, a deflection electrode 14, and an objective lens 15 are arranged in this order along the emission direction of the electron flow from the electron beam source 11.
  • a deflection control device 50 is connected to the deflection electrode 14 so that the electron beam EB can be deflected with high accuracy.
  • the energy, current amount, and focus state of the electron beam EB can be arbitrarily controlled.
  • An XY stage 21 for supporting the semiconductor substrate 23 and a tray 22 fixed on the XY stage 21 are accommodated in the chamber 20, and the semiconductor substrate 23 is placed on the tray 22. It is placed.
  • the irradiation direction of the electron beam EB emitted from the electron gun 10 is directed to the surface of the semiconductor substrate 23 placed on the tray 22, and by moving the position of the tray 22 by the XY stage 21, The irradiation position of the electron beam EB to the semiconductor substrate 23 can be adjusted.
  • a secondary electron detector 24 for detecting secondary electrons, whose surface force is also emitted from the semiconductor substrate 23 when the electron beam EB is irradiated, is provided inside the chamber 120.
  • an electrode is provided inside the chamber 20 for applying a bias voltage to the semiconductor substrate 23, an electrode is provided, and a voltage applying device for supplying a noise voltage to the electrode is provided outside the chamber 20. It has been.
  • the degree of vacuum inside the chamber 20 is, for example, 10 It is maintained at minus 6 [torr].
  • the semiconductor in order to irradiate the semiconductor substrate with the electron beam EB irradiated from the electron gun 10 with a position accuracy of the order of nm, the semiconductor is relatively relative to the irradiation axis of the fixed electron beam EB.
  • the position of the substrate 23 is moved by the XY stage 21.
  • a drive device for the XY stage 21 a Norse motor, an ultrasonic motor, or a piezoelectric element is used.
  • the positional accuracy of the semiconductor substrate 23 placed on the XY stage 21 is controlled to about several nm.
  • a current measuring device 30 is connected to the tray 22, and a substrate current induced in the semiconductor substrate 23 is measured by the current measuring device 30 via the tray 22.
  • the current measuring device 30 includes an AZD converter that AZD converts the measured substrate current value into a digital signal, and outputs the measured value as digital data.
  • the tray 22 is provided with an electron beam irradiation position measuring device 22A for measuring the irradiation position of the electron beam EB on the semiconductor substrate 23.
  • Electron beam irradiation position measurement device 22A outputs the coordinates of the measured electron beam irradiation position (electron beam irradiation coordinates).
  • the irradiation coordinates of the electron beam obtained by the electron beam irradiation position measuring device 22A are used as parameters for forming a secondary electron image and a substrate current waveform, which will be described later.
  • the coordinate system of the irradiation position of the electron beam EB is not particularly limited.
  • the semiconductor measurement apparatus includes a sequence control apparatus (including a pattern matching engine) 100, a focus control apparatus 110, a secondary electron image recording apparatus 120, a substrate current waveform recording apparatus 130, a waveform processing apparatus 140, and an edge extraction.
  • the sequence control device 100 controls the deflection control device 50 so that the electron beam EB scans the surface of the semiconductor substrate 23 when the substrate current is measured, and the irradiation position of the electron beam on the semiconductor substrate. It controls the pattern matching to adjust the irradiation position of the electron beam EB with high accuracy.
  • the one-dimensional scanning means scanning in a line shape.
  • Two-dimensional scanning means that line-shaped scanning is repeated a plurality of times at regular intervals, and is a concept similar to horizontal scanning and vertical scanning on a television screen, for example.
  • pattern matching is performed to compare the actual pattern and the reference pattern for each semiconductor substrate so that the actual pattern matches the reference pattern. Shift the irradiation position of electron beam EB. This makes it possible to accurately adjust the irradiation position of the electron beam with an accuracy of several nm for each semiconductor substrate.
  • the semiconductor measurement apparatus includes a high-resolution deflection control device 50 for accurately linearly scanning the electron beam EB in order to accurately shift the irradiation position of the electron beam EB in pattern matching, and also performs sequence control.
  • the apparatus 100 includes an image recognition apparatus (including a pattern matching engine) and software for performing pattern matching.
  • the focus control device 110 controls the focus position of the objective lens 15, and controls the focus amount of the objective lens 15 during measurement to control the focus amount of the electron beam. This is for setting the tip to a desired size and shape.
  • the focus amount of the electron beam EB focus position of the objective lens 15
  • the distance of the wafer surface force is obtained optically or electrically, and the focus amount is set based on the distance.
  • a method that sets the amount of focus for the state in which the image obtained by scanning the beam is the clearest or the state force that maximizes the contrast of the secondary electrons, and the image obtained by the substrate current value when the electron beam is irradiated A method such as a method of setting the focus amount can be used for the state where the image becomes the clearest or the state force that maximizes the contrast.
  • the secondary electron image recording device 120 records an image formed by secondary electrons detected by the secondary electron detector 24.
  • the substrate current waveform recording device 130 stores the waveform of the substrate current value measured by the current measuring device 30 in association with the irradiation coordinates of the electron beam EB at that time. Beam illumination It is read from the shooting position recording device 22A.
  • the waveform processing device 140 shapes the waveform of the substrate current value to remove unnecessary noise components.
  • the edge extraction device 150 extracts the contact hole edge from the waveform-shaped substrate current waveform, and calculates an evaluation value related to the shape of the contact hole.
  • the display device 160 displays the evaluation value.
  • the database device 170 stores the evaluation values calculated by the edge extraction device 150 in a database.
  • alignment of the electron beam EB and the semiconductor substrate 23 is performed under the control of the sequence controller 100. That is, the position coordinate of the hole to be measured is specified with respect to the control system of the XY stage 21 holding the semiconductor substrate 23, the XY stage 21 is moved, and the center of the hole is set at the irradiation position of the electron beam EB. Match roughly. Then, the electron beam EB is irradiated while scanning two-dimensionally, and pattern matching is performed by comparing the image of secondary electrons generated at that time with the template image, and the amount of deviation between the center of the template image and the center of the hole Is calculated. This deviation amount is input to the deflection controller 50, and the irradiation position of the electron beam EB is shifted so that the irradiation position of the electron beam EB is accurately aligned with the center of the hole to be measured.
  • step S 11 to S 14 for calculating the evaluation value of the substrate current force hole are executed under the control of the sequence control device 100.
  • the substrate current waveform is acquired by irradiating the semiconductor substrate 23 with the electron beam EB (step Sl l). That is, a predetermined region on the surface of the semiconductor substrate 23 is two-dimensionally scanned by the electron beam EB with reference to the hole center.
  • the electron beam EB is irradiated perpendicularly to the surface of the semiconductor substrate 23, the focus position of the objective lens 15 is controlled so that the tip of the electron beam EB has a desired size, and the deflection control device By applying a control voltage to 50, one-dimensional scanning is repeated at regular intervals and at a constant speed (for example, 10 one-dimensional scannings are performed at regular intervals).
  • the semiconductor substrate irradiated with the electron beam EB by this scanning Secondary electrons and reflected electrons are generated from a minute region on the surface of the substrate 23, and a substrate current is induced in the semiconductor substrate 23.
  • the substrate current induced in the semiconductor substrate 23 by the above-described scanning is measured by the current measuring device 30 and converted into an electric signal having a necessary dynamic range.
  • This electrical signal is immediately sampled and converted to a digital signal with the required resolution so that the signal quality is not degraded.
  • the resolution of this digital signal is 16 bits and its sampling frequency is 400 MHz.
  • the irradiation position of the electron beam EB is measured by the electron beam irradiation position measuring device 22A.
  • the measurement value of the substrate current obtained by scanning the electron beam EB in this way includes information on the structure of the bottom surface of the hole, and the measurement coordinates (electron beam) measured by the above-described electron beam irradiation position measuring device.
  • secondary electrons generated from a minute region on the surface of the semiconductor substrate 23 by the above-described scanning are detected by the secondary electron detector 24.
  • the secondary electrons can be detected by using a well-known photomultiplier, multichannel plate, or simple electrode to directly collect secondary electrons and use them as current signals.
  • the important thing is that a relationship in which the amount of secondary electrons detected by the secondary electron detector 24 is proportional to the amount of secondary electrons actually generated can be obtained.
  • the output value of the secondary electron detector 24 is set to be exactly proportional to the number of input electrons. As a result, secondary electrons are detected linearly from the small signal region to the large signal region.
  • the secondary electron is expressed for the purpose of expressing it as a binary image, so that the detected value has a large difference between when there is a signal and when there is no signal. It is set! That is, the detection value is set to 0 when very few electrons are input to the detector, and the amplifier has nonlinear characteristics that generate a large detection value when electrons exceeding a certain threshold are input. It has become.
  • the measurement value of the secondary electrons obtained by the above-mentioned scanning includes information on the surface structure of the semiconductor substrate 23, and the measurement coordinates (electricity) measured by the electron beam irradiation position measurement device 22A.
  • Digital information is recorded in the secondary electron image recording device 120 (for example, a memory or a hard disk) as image information expressed as a function of a child beam irradiation position) or a measurement time (electron beam EB irradiation time).
  • the backscattered electrons that have generated micro-region forces on the surface of the semiconductor substrate 23 are detected by a backscattered electron detector (not shown), and the backscattered electron image obtained from the detected value is digitally recorded on a backscattered electron image recording device (not shown). Is done.
  • secondary electrons and reflected electrons can be distinguished by differences in energy and emission direction, but depending on the type of detection device, they can be handled together without being distinguished.
  • a plurality of units may be arranged. In such a case, information shall be recorded independently according to the number of detectors. Is desirable.
  • each of the secondary electron detector 24 and the backscattered electron detector may be arranged one by one.
  • the waveform of the substrate current measured as described above is shaped by the waveform processing device 140 in order to remove unnecessary noise and high frequency components.
  • Examples of the waveform processing include moving average filter processing, waveform processing for removing a specific frequency, or filter processing for extracting only a signal of a specific frequency. These waveform shaping processes can be performed in hardware or software.
  • the edge extraction device 150 also extracts the edge of the hole with respect to the waveform force of the substrate current (step S12).
  • the edge extraction device 150 extracts an edge of a hole from the above-described substrate current waveform using an edge extraction algorithm, and converts the extracted edge coordinate value into the XY coordinate system.
  • This embodiment has a feature in the principle of the edge extraction algorithm, and details thereof will be described later.
  • the edge extraction device 150 applies a circle approximation function or an ellipse approximation function to the converted XY coordinate values (step S13), and performs curve fitting using the least square method.
  • the edge coordinates of the current waveform described above correspond to the edge coordinates of the hole, and the shape of the edge of the hole is reproduced by connecting the coordinate values of the edge of the substrate current waveform obtained by one-dimensional scanning. be able to.
  • the edge extraction device 150 calculates the evaluation value of the hole shape by using the above approximate function to which the parameter is fitted (step S14).
  • the hole evaluation value includes the hole diameter, hole center position, hole inclination angle, hole rotation angle, hole roundness, hole distortion, edge roughness, and the like.
  • an elliptic function is used as an approximate function, the major axis, minor axis, focus, distortion, rotation, etc. of the ellipse are calculated. These values are displayed on a display device 160 such as a computer display or stored as digital data in a database device 170.
  • This edge extraction algorithm is based on obtaining an evaluation value of the fine structure based on the waveform of the substrate current when the measured waveform of the substrate current is regarded as a differential waveform.
  • the edge extracting device 150 is configured.
  • FIG. 3 shows a cross-sectional structure of a contact hole that is a measurement target of the semiconductor measurement apparatus.
  • FIG. 3A shows a cross-sectional structure of a normal contact hole HA.
  • an interlayer insulating film F is formed on the main surface of the silicon substrate S via an oxide film, and a contact hole HA is formed so as to penetrate the interlayer insulating film F. .
  • the silicon substrate S is exposed at the bottom of the hole HA.
  • a P-type or N-type diffusion layer is formed on the silicon substrate S, and this diffusion layer has conductivity.
  • FIG. 3B shows a cross-sectional structure of the contact hole HB formed on the gate G.
  • the gate G is a control electrode that constitutes a MOS transistor, and the gate G is very thin.
  • a gate oxide film GOX of nm order is formed, and a silicon substrate S exists below it.
  • the gate G and the silicon substrate S are insulated from each other by the gate oxide film GOX and are not connected in a direct current.
  • FIG. 3C is a force showing the cross-sectional structure of the contact hole formed on the gate G2.
  • This example is a floating gate (electrically isolated) used in flash memory or the like that has attracted attention in recent years. Gate) structure. That is, an insulator ONO for accumulating charges exists under the gate G2, and a normal gate G1 exists under the insulator ONO. Under the gate G1, there is a silicon substrate S through a gate oxide film GOX.
  • This floating gate structure is a structure in which the gate G shown in FIG. 3B is stacked. In other words, the insulating film is characterized in that two layers of gates are formed with the electrode interposed therebetween.
  • the contact holes HA to HC shown in FIGS. 3A to 3C, respectively, have a very large aspect ratio, but a conventional SEM cannot measure the shape of the hole bottom.
  • the electron beam EB that is narrowly focused is irradiated so as to hit the bottom of the holes HA to HC, and the shape (size) of the hole bottom is determined from the change in the substrate current induced in the silicon substrate S at that time. Is identified.
  • FIGS. 4A to 4D show the waveform of the substrate current actually observed in this manner.
  • FIG. 4A shows the waveform of the substrate current when the electron beam EB is irradiated on the hole structure shown in FIG. 3A, and an N-type diffusion layer is formed on the surface of the silicon substrate S corresponding to the bottom of the hole. It is a waveform when it is.
  • FIG. 4B shows the waveform of the substrate current when the electron beam EB is irradiated to the hole structure shown in FIG. 3A.
  • a P-type diffusion layer is formed on the surface of the silicon substrate S corresponding to the bottom of the hole.
  • 4C shows the substrate current when the electron beam EB is irradiated to the hole structure shown in FIG. 3B
  • FIG. 4D shows the substrate current when the electron beam EB is irradiated to the hole structure shown in FIG. 3C. Is
  • FIG. 5A shows an electrical equivalent circuit of the normal contact hole HA shown in FIG. 3A.
  • the equivalent circuit of the contact hole HA is composed of the resistance R1 of the silicon substrate S, and the irradiated electron beam EB flows to the silicon substrate S through the resistance R1. Therefore, silicon Regardless of whether the diffusion layer formed on the surface of the substrate S is N-type or P-type, when the normal contact hole HA is irradiated with the electron beam EB, as shown in Fig. 4A and Fig. 4B In addition, a trapezoidal substrate current waveform is obtained.
  • the edge of the hole is possible to easily extract the edge of the hole from such a trapezoidal substrate current waveform.
  • the coordinates when the waveform crosses a predetermined threshold value, or the maximum slope of the waveform in each slope region Define the coordinates indicating the value as the edge of the hole and extract the required number of edges.
  • the circle shape, ellipse approximation, or straight line approximation is applied to the extracted edge to extract the shape of the hole.
  • the obtained substrate current waveform must be trapezoidal as shown in FIGS. 4C and 4D. .
  • FIG. 5B shows an electrical equivalent circuit of the contact hole HB shown in FIG. 3B.
  • a gate G exists at the bottom of the contact hole HB.
  • This electrical equivalent circuit is composed of one capacitor C1 formed of a gate G that also has a polysilicon force, a gate insulating film GOX, and a silicon substrate S, and a resistor R1 that the silicon substrate S has. And the resistor R1 are connected in series.
  • the capacitor C 1 and the resistor R1 form a time constant circuit, and this time constant is determined by the product of the capacitance value of the capacitor C1 and the resistance value of the resistor R1. Therefore, the Hall structure in this case is equivalent to a circuit having a time constant proportional to the capacitance value of the capacitor C1 and the resistance value of the resistor R1.
  • other parasitic CR components are ignored for convenience of explanation.
  • FIG. 5C shows an electrical equivalent circuit of the contact hole HC shown in FIG. 3C.
  • the bottom of the contact hole HC has a gate G2, an insulating film ONO, and a gate.
  • Gl, gate oxide GOX, and silicon substrate S exist.
  • the hole structure includes two gates, a gate G2 and a gate G1, and two insulating films, a gate oxide film GOX and a nitride film ONO.
  • the two electrodes and the two insulating films form capacitors CI and C2 connected in series.
  • the silicon substrate S forms a resistor R.
  • capacitors CI, C2 and resistor R1 are connected in series.Therefore, the hole structure in this case is the capacitance value and resistance of resistor R1 when capacitors CI, C2 are directly connected. This is equivalent to a circuit having a time constant composed of a resistance value.
  • FIG. 6A generally, when a capacitor C and a resistor R are connected in series, a differentiation circuit is obtained.
  • a rectangular waveform as shown in FIG. 6B is input to the differentiating circuit, the rectangular waveform is differentiated, and a differential waveform having a component proportional to the amount of inclination of the rectangular waveform is output as shown in FIG. 6C.
  • the input rectangular waveform has both positive and negative slopes at the rise and fall, an output having both positive and negative values can be obtained.
  • a current that flows in both plus and minus is generated from a rectangular current waveform that flows in one direction.
  • This waveform is unidirectional if there is a differential circuit in the hole structure of the measurement object, regardless of the time constant of the measurement object or the force affected by the scanning speed of the electron beam EB irradiated for measurement. Even if only the current flowing through is supplied, both positive and negative currents are observed. Therefore, it can be seen from the waveforms shown in FIGS. 4C and 4D that the equivalent circuit of the hole structure shown in FIGS. 3B and 3C includes a differentiation circuit.
  • Fig. 7A shows the state of charge redistribution that occurs in the initial stage (image charge formation period) when the measurement target is irradiated with the electron beam EB.
  • the electron beam EB scans at a constant speed toward the left side force and right side of the figure.
  • FIG. 7B shows the next stage of the image charge formation period described above.
  • the thickness of the mono-acid film is about 10 nm.
  • charges accumulate on the electrode of the gate G, and the potential of the gate G rises in proportion to the amount of irradiation current.
  • FIG. 7C when the potential of the gate G exceeds, for example, about 10 V, the electric field E at that time becomes lOMVZcm, and the tunnel current IT starts flowing in the gate oxide film GOX having a thickness of about lOnm. , The charge moves.
  • FIG. 7D shows the state of charge transfer when the scanning position of the electron beam EB deviates from the contact hole to be measured and the irradiation of the electron beam EB to the measurement object is completed.
  • the supply of electrons by the electron beam EB is lost, and as a result, charges accumulated in the region sandwiched between the gate G, the gate oxide film GOX, and the silicon substrate S are discharged.
  • a tunnel current IT flows in the opposite direction to the charge accumulation process shown in FIG. 7C.
  • the current at this time is expressed by the following equation.
  • the waveform of the substrate current shown in FIG. 8 has two peaks P1 and P2, which correspond to the differential waveform obtained by the differentiation circuit shown in FIG. 5B described above. Therefore, if we consider that this peak P1 and peak P2 are obtained by differentiating the waveform observed when there is no insulator such as a gate at the bottom of the hole, each peak corresponds to the edge of the hole.
  • the hole diameter CD can be calculated as the hole evaluation value from the interval between these peaks P1 and P2.
  • a plurality of edges are obtained from a plurality of substrate current waveforms obtained when the electron beam EB is scanned two-dimensionally with respect to a single hole.
  • circular approximation elliptical
  • the shape of the bottom of the hole can be evaluated from the measured substrate current waveform.
  • the gate oxide film does not function as a complete capacitance as described above. That is, when a certain amount of charge accumulates in the gate electrode and the surface potential rises, a tunneling current flows through the gate oxide film, so a differential waveform different from a pure capacitance is observed. . Therefore, a more accurate method for determining the edge of the hole is to extract the waveform of the region where the gate oxide film functions as a pure capacitor from the components that make up the observed waveform, and then calculate the waveform force derivative. Therefore, the exact hole edge can be extracted. Or, conversely, by adjusting the electron beam dose as small as possible, there is a method of measuring in a state where the structure composed of the gate electrode, the gate insulating film, and the silicon substrate functions as a pure capacitor. .
  • a force that produces a trapezoidal waveform as the substrate current waveform is differentiated as one method for extracting the edge of the hole.
  • the place where the differential value shows the maximum value is extracted as the edge of the hole.
  • the shape of the hole is evaluated by applying a circle approximation, an ellipse approximation or another approximate curve to the multiple edges obtained as described above.
  • FIG. 9 shows an operation flow of the semiconductor measuring apparatus according to the second embodiment of the present invention.
  • the apparatus configuration of this embodiment is basically the same as that of the first embodiment described above, but the principle of the edge extraction algorithm is different. That is, the edge extraction algorithm of the present embodiment is based on obtaining an evaluation value of the fine structure based on the integrated waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.
  • Such an evaluation means is configured as an edge extraction device 150, for example.
  • the operation flow of the present embodiment shown in FIG. 9 includes step S22 related to waveform integration processing, step S23 related to filtering, instead of step S12 of the operation flow of the first embodiment shown in FIG. Step S24 related to edge detection.
  • Figure 9 shows Steps common to the steps shown in FIG. 2 are given the same reference numerals.
  • the waveform obtained in step S 11 is a differential waveform, it is integrated once and returned to the original waveform (step S 22). After that, necessary components are extracted from the integrated waveform using a filter that extracts components corresponding to the bottom of the hole as required (step S23).
  • the differential waveform contains high-frequency components or low-frequency components that are unnecessary for estimating the size of noise and holes, so these are removed as appropriate to obtain a waveform that correctly reflects the bottom of the hole.
  • the current waveform obtained by integrating in this way is the same as the waveform obtained by measuring the normal contact hole HA as shown in FIG.
  • To extract edges step S24.
  • edge extraction algorithm all algorithms commonly known in mathematics such as threshold value method, differentiation method, Sobel method, Laplacian method can be used. The following is the same as in the first embodiment (steps S13 and S14).
  • FIG. 10 shows an operation flow of the semiconductor measuring apparatus according to the third embodiment of the present invention.
  • steps that are the same as those shown in FIG. 9 are given the same reference numerals.
  • the apparatus configuration of the present embodiment is basically the same as that of the first or second embodiment described above.
  • the apparatus includes step S32 relating to inverse calculation, and the waveform of the substrate current obtained in step S11. Based on the above, it is essential to identify an equivalent circuit of a fine structure and obtain an evaluation value of the fine structure based on the waveform obtained by using this equivalent circuit. Composed.
  • an equivalent circuit (parameter values are not set) is prepared in advance, which represents in detail the hole structure to be measured including the gate structure and the control gate structure.
  • an equivalent circuit which represents in detail the hole structure to be measured including the gate structure and the control gate structure.
  • a specific component of the capacitor formed by the gate electrode is also incorporated in the equivalent circuit.
  • the equivalent circuit of FIG. 11 is as shown in FIG. 12 formed by a gate electrode by incorporating a zener diode ZD into the equivalent circuit of the Hall structure of FIG. 3B. It expresses the nonlinearity that is a specific component of a simple capacitor.
  • R2 is the resistance component of the gate.
  • the Zener diode ZD is also called a constant voltage diode. When the voltage across the diode reaches a constant voltage, current flows through the diode and keeps the voltage across the diode constant.
  • the measurement object can be expressed more accurately by a mathematical expression.
  • the measured substrate current waveform can be converted into the substrate current waveform indicated by a normal contact hole.
  • a waveform simulating the original waveform is obtained using the above-described equivalent circuit (step S32). Specifically, this parameter is obtained by inversely calculating each parameter of the equivalent circuit so that the waveform obtained using the equivalent circuit prepared in advance matches the waveform actually observed in step S11. Identify each parameter. Next, filtering is performed on the waveform obtained using the equivalent circuit with the specified parameters (step S23), and the edge extraction method is applied to extract the edge and obtain the evaluation value of the hole ( Steps S12 to S14).
  • the waveform obtained by the equivalent circuit is a force that becomes a differential waveform.
  • the content of the equivalent circuit varies depending on the hole structure.
  • the waveform obtained by the equivalent circuit also changes. Therefore, in step S12 of this embodiment, edge detection is performed by applying an appropriate edge extraction algorithm to the waveform obtained using the equivalent circuit. That is, if the waveform obtained using the equivalent circuit is a differential waveform, the same edge extraction algorithm as in the first embodiment is applied, and if it is a trapezoidal waveform, the same conventional power as in the second embodiment is applied. A known edge extraction algorithm may be applied.
  • the force described in the case where a gate is present at the bottom of the hole may be any member that is present at the bottom of the hole.
  • the member does not need to be present on the entire bottom surface of the hole, but may be present on a part of the bottom of the hole.
  • the present invention is a semiconductor measuring device and a semiconductor measuring method.
  • the present invention is not limited to this.
  • Semiconductor inspection equipment, semiconductor inspection methods, semiconductor analysis equipment, semiconductor analysis methods, semiconductor analysis equipment, semiconductor analysis methods, semiconductor evaluation equipment, semiconductor evaluation equipment, semiconductor manufacturing equipment, semiconductor manufacturing equipment It may be expressed as a method or the like.
  • the present invention is useful for a semiconductor device or an apparatus used for inspection, analysis, manufacturing, measurement or evaluation in a manufacturing process thereof, and a semiconductor device manufacturing method.
  • the present invention is used in the fields of inspection techniques, analysis techniques, measurement techniques, evaluation techniques, and semiconductor device manufacturing apparatuses and methods that use a method of irradiating a semiconductor substrate such as a wafer with an electron beam or ion beam. Can do.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Abstract

Provided is a semiconductor measuring apparatus which can evaluate complicated fine structures by two-dimensionally scanning the surface of a semiconductor substrate whereupon a fine structure is formed with an electron beam and measuring a substrate current of that time. The semiconductor measuring apparatus is configured to irradiate a semiconductor substrate with an electron beam and obtain an evaluation value of a fine structure formed on the semiconductor substrate from a substrate current induced to the semiconductor substrate by the electron beam. The semiconductor measuring apparatus is characterized in that the apparatus is provided with an evaluating means for obtaining the evaluation value of the fine structure based on the waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.

Description

明 細 書  Specification
半導体測定装置および半導体測定方法  Semiconductor measuring apparatus and semiconductor measuring method
技術分野  Technical field
[0001] 本発明は、電子ビームを利用した半導体測定装置および半導体測定方法に関し、 特にコンタクトホール等の微細構造を評価するのに好適な測定技術に関する。 背景技術  TECHNICAL FIELD [0001] The present invention relates to a semiconductor measurement apparatus and a semiconductor measurement method using an electron beam, and particularly to a measurement technique suitable for evaluating a fine structure such as a contact hole. Background art
[0002] 半導体デバイスの微細構造の一つにコンタクトホールがある。このコンタクトホール は、シリコン基板に形成された例えばトランジスタと他の電気素子とを電気的に接続 するための配線構造の一部をなす。このコンタクトホールの構造を測定するための方 法として、電子ビームを用いた方法が一般に利用されており、この種の装置として CD SEMが広く知られている。  [0002] One of the fine structures of semiconductor devices is a contact hole. This contact hole forms part of a wiring structure for electrically connecting, for example, a transistor and another electric element formed in the silicon substrate. As a method for measuring the structure of this contact hole, a method using an electron beam is generally used, and CD SEM is widely known as this type of apparatus.
[0003] 上述の CDSEMによれば、測定対象の微細構造が形成された半導体基板表面を電 子ビームでライン状に走査し、そのときに生じる二次電子を検出して得られる波形か ら微細構造を測定する。この二次電子の波形には微細構造が有するエッジに関する 情報が含まれており、このエッジはコントラストの差として認識される。  [0003] According to the above-described CDSEM, the surface of a semiconductor substrate on which a microstructure to be measured is formed is scanned in a line shape with an electron beam, and secondary electrons generated at that time are detected and a fine waveform is obtained from a waveform. Measure the structure. This secondary electron waveform contains information about the edge of the microstructure, and this edge is recognized as a contrast difference.
[0004] 一方、アスペクトレシオの高!、ホール構造の場合、従来の CDSEMでは、ホール内 部からの二次電子を効率よく捕捉できないため、ホールの内部構造を精度良く把握 することができない。このような問題を解決する技術として、二次電子の代わりに基板 電流を利用した EBSCOPEと 、う技術が出現した (特許文献 1参照)。  [0004] On the other hand, in the case of a hole structure with a high aspect ratio, the conventional CDSEM cannot efficiently capture secondary electrons from the inside of the hole, and thus cannot accurately grasp the internal structure of the hole. As a technique for solving such a problem, EBSCOPE using substrate current instead of secondary electrons has appeared (see Patent Document 1).
[0005] 上述の EBSCOPEによれば、半導体基板表面を電子ビームで走査し、そのときに生 じる基板電流の波形力 ホール構造を求める。ここで、基板電流は、ホールの内部を 通過して半導体基板に到達した電子ビームによって誘起されるので、この基板電流 には、ホールの内部構造に関する情報が含まれており、その電流波形から、ホール の内部構造を知ることができる。  [0005] According to the above-mentioned EBSCOPE, the surface of the semiconductor substrate is scanned with an electron beam, and the waveform force of the substrate current generated at that time is determined. Here, since the substrate current is induced by the electron beam that has passed through the inside of the hole and reached the semiconductor substrate, this substrate current includes information on the internal structure of the hole. From the current waveform, You can know the internal structure of the hall.
特許文献 1:特開 2005— 026449号公報  Patent Document 1: Japanese Patent Laid-Open No. 2005-026449
発明の開示  Disclosure of the invention
発明が解決しょうとする課題 [0006] しかしながら、上述の従来技術に係る EBSCOPEによれば、ホール底の構造が単純 な場合には、観測された基板電流の波形からホール底の構造を把握する事は容易 であるが、ホール底に酸ィ匕膜やチッ化膜などの種々の残膜が存在し、ホール底の構 造が複雑になる程、観測される基板電流の波形が非常に複雑になるため、そのホー ル底の構造を正しく測定することが困難になるという問題があった。 Problems to be solved by the invention [0006] However, according to EBSCOPE according to the above-described conventional technology, when the hole bottom structure is simple, it is easy to grasp the hole bottom structure from the observed substrate current waveform. There are various residual films such as oxide film and nitride film on the bottom, and the more complicated the structure of the hole bottom, the more complicated the waveform of the observed substrate current. There was a problem that it was difficult to measure the structure of the film correctly.
[0007] 本発明は、ホール底の構造が複雑であっても、そのホール底の構造を正しく測定 することができる半導体測定装置を提供することを目的とする。  [0007] An object of the present invention is to provide a semiconductor measuring apparatus capable of correctly measuring the structure of the hole bottom even if the structure of the hole bottom is complicated.
課題を解決するための手段  Means for solving the problem
[0008] 上記課題を解決するため、本発明に係る半導体測定装置は、半導体基板に電子 ビームを照射し、該電子ビームによって前記半導体基板に誘起された基板電流から 前記半導体基板に形成された微細構造の評価値を得るように構成された半導体測 定装置であって、前記基板電流の波形を微分波形と見なしたときの該基板電流の波 形に基づき前記微細構造の評価値を得る評価手段を備えたことを特徴とする。 In order to solve the above-described problem, a semiconductor measurement apparatus according to the present invention irradiates a semiconductor substrate with an electron beam, and forms a fine pattern formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. A semiconductor measurement apparatus configured to obtain an evaluation value of a structure, wherein the evaluation value of the microstructure is obtained based on a waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform Means are provided.
[0009] 前記半導体測定装置にお!/、て、前記微細構造はホールであり、前記評価手段は、 前記基板電流の波形力も前記ホールのエッジを抽出することを特徴とする。 [0009] In the semiconductor measurement apparatus, the fine structure is a hole, and the evaluation means extracts the waveform force of the substrate current and the edge of the hole.
前記半導体測定装置において、前記評価手段は、前記ホールのエッジから該ホー ルの評価値を算出することを特徴とする。  In the semiconductor measuring apparatus, the evaluation unit calculates an evaluation value of the hole from an edge of the hole.
前記半導体測定装置において、前記評価手段は、前記基板電流の波形のピーク 力 前記ホールのエッジを抽出することを特徴とする。  In the semiconductor measurement apparatus, the evaluation unit extracts a peak force of the waveform of the substrate current and an edge of the hole.
[0010] 本発明に係る半導体測定装置は、半導体基板に電子ビームを照射し、該電子ビー ムによって前記半導体基板に誘起された基板電流から前記半導体基板に形成され た微細構造の評価値を得るように構成された半導体測定装置であって、前記基板電 流の波形を微分波形と見なしたときの該基板電流の積分波形に基づき前記微細構 造の評価値を得る評価手段を備えたことを特徴とする。 The semiconductor measurement apparatus according to the present invention irradiates a semiconductor substrate with an electron beam, and obtains an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. The semiconductor measurement apparatus configured as described above includes an evaluation unit that obtains an evaluation value of the microstructure based on an integrated waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform. It is characterized by.
[0011] 前記半導体測定装置において、前記微細構造はホールであり、前記評価手段は、 前記積分波形力 前記ホールのエッジを抽出することを特徴とする。  [0011] In the semiconductor measurement apparatus, the fine structure is a hole, and the evaluation unit extracts the integrated waveform force and an edge of the hole.
前記半導体測定装置において、前記評価手段は、前記ホールのエッジから該ホー ルの評価値を算出することを特徴とする。 [0012] 本発明に係る半導体測定装置は、半導体基板に電子ビームを照射し、該電子ビー ムによって前記半導体基板に誘起された基板電流から前記半導体基板に形成され た微細構造の評価値を得るように構成された半導体測定装置であって、前記基板電 流の波形に基づき前記微細構造の等価回路を特定し、該等価回路を用いて得られ る波形に基づき前記微細構造の評価値を得る評価手段を備えたことを特徴とする。 In the semiconductor measuring apparatus, the evaluation unit calculates an evaluation value of the hole from an edge of the hole. The semiconductor measurement apparatus according to the present invention irradiates a semiconductor substrate with an electron beam, and obtains an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. A semiconductor measurement apparatus configured as described above, wherein an equivalent circuit of the microstructure is specified based on a waveform of the substrate current, and an evaluation value of the microstructure is obtained based on a waveform obtained using the equivalent circuit An evaluation means is provided.
[0013] 前記半導体測定装置にお!/、て、前記微細構造はホールであり、前記評価手段は、 前記等価回路を用いて得られる波形力 前記ホールのエッジを抽出することを特徴 とする。  [0013] In the semiconductor measurement apparatus, the fine structure is a hole, and the evaluation unit extracts a waveform force obtained by using the equivalent circuit, and an edge of the hole is extracted.
前記半導体測定装置において、前記評価手段は、前記ホールのエッジから該ホー ルの評価値を算出することを特徴とする。  In the semiconductor measuring apparatus, the evaluation unit calculates an evaluation value of the hole from an edge of the hole.
[0014] 本発明に係る半導体測定方法は、半導体基板に電子ビームを照射し、該電子ビー ムによって前記半導体基板に誘起された基板電流から前記半導体基板に形成され た微細構造の評価値を得る半導体測定方法であって、前記基板電流の波形を微分 波形と見なしたときの該基板電流の波形に基づき前記微細構造の評価値を得ること を特徴とする。 The semiconductor measurement method according to the present invention irradiates a semiconductor substrate with an electron beam, and obtains an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. A semiconductor measurement method is characterized in that an evaluation value of the microstructure is obtained based on a waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.
発明の効果  The invention's effect
[0015] 本発明によれば、ホール底に残膜が存在しても、ホール底の構造を正しく測定する ことが可能になる。  [0015] According to the present invention, it is possible to correctly measure the structure of the hole bottom even if there is a residual film on the hole bottom.
図面の簡単な説明  Brief Description of Drawings
[0016] [図 1]本発明の第 1実施形態に係る半導体測定装置の構成図である。 FIG. 1 is a configuration diagram of a semiconductor measuring device according to a first embodiment of the present invention.
[図 2]本発明の第 1実施形態に係る半導体測定装置の動作の流れを示すフローチヤ ートである。  FIG. 2 is a flowchart showing the flow of operation of the semiconductor measuring apparatus according to the first embodiment of the present invention.
[図 3A]本発明の第 1実施形態に係る測定対象のホール構造 (通常の構造)の第 1例 を示す図である。  FIG. 3A is a diagram showing a first example of a hole structure (normal structure) to be measured according to the first embodiment of the present invention.
[図 3B]本発明の第 1実施形態に係る測定対象のホール構造 (ゲートを有する構造) の第 2例を示す図である。  FIG. 3B is a diagram showing a second example of a hole structure (a structure having a gate) to be measured according to the first embodiment of the present invention.
[図 3C]本発明の第 1実施形態に係る測定対象のホール構造 (フローティングゲートを 有する構造)の第 3例を示す図である。 圆 4A]本発明の第 1実施形態に係る半導体測定装置によって観測される基板電流 の波形の第 1例を示す図である。 FIG. 3C is a diagram showing a third example of a hole structure (a structure having a floating gate) to be measured according to the first embodiment of the present invention. FIG. 4A] A diagram showing a first example of a waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
圆 4B]本発明の第 1実施形態に係る半導体測定装置によって観測される基板電流 の波形の第 2例を示す図である。 FIG. 4B] A diagram showing a second example of the waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
圆 4C]本発明の第 1実施形態に係る半導体測定装置によって観測される基板電流 の波形の第 3例を示す図である。 FIG. 4C] A diagram showing a third example of the waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
圆 4D]本発明の第 1実施形態に係る半導体測定装置によって観測される基板電流 の波形の第 4例を示す図である。 FIG. 4D is a diagram showing a fourth example of the waveform of the substrate current observed by the semiconductor measuring device according to the first embodiment of the present invention.
圆 5A]本発明の第 1実施形態に係る第 1例のホール構造の等価回路図である。 圆 5B]本発明の第 1実施形態に係る第 2例のホール構造の等価回路図である。 圆 5C]本発明の第 1実施形態に係る第 3例のホール構造の等価回路図である。 圆 6A]本発明の第 1実施形態に係る半導体測定装置の基本原理を説明するための 微分回路図である。 FIG. 5A] is an equivalent circuit diagram of the hole structure of the first example according to the first embodiment of the present invention. FIG. 5B] is an equivalent circuit diagram of the hole structure of the second example according to the first embodiment of the present invention. [5C] FIG. 5C is an equivalent circuit diagram of the hole structure of the third example according to the first embodiment of the present invention. FIG. 6A] A differential circuit diagram for explaining the basic principle of the semiconductor measuring device according to the first embodiment of the present invention.
圆 6B]本発明の第 1実施形態に係る半導体測定装置の基本原理を説明するための 微分回路の入力波形図である。 6B] An input waveform diagram of the differentiating circuit for explaining the basic principle of the semiconductor measuring device according to the first embodiment of the present invention.
[図 6C]本発明の第 1実施形態に係る半導体測定装置の基本原理を説明するための 微分回路の出力波形図である。  FIG. 6C is an output waveform diagram of the differentiating circuit for explaining the basic principle of the semiconductor measuring device according to the first embodiment of the present invention.
圆 7A]本発明の第 1実施形態に係る基板電流の発生メカニズム (イメージチャージ形 成期)の説明図である。 FIG. 7A is an explanatory diagram of a substrate current generation mechanism (image charge formation period) according to the first embodiment of the present invention.
圆 7B]本発明の第 1実施形態に係る基板電流の発生メカニズム(トンネル電流形成 初期)の説明図である。 FIG. 7B is an explanatory diagram of a substrate current generation mechanism (initial tunnel current formation) according to the first embodiment of the present invention.
圆 7C]本発明の第 1実施形態に係る基板電流の発生メカニズム(トンネル電流形成 後期)の説明図である。 [7C] FIG. 7C is an explanatory diagram of a substrate current generation mechanism (late tunnel formation) according to the first embodiment of the present invention.
圆 7D]本発明の第 1実施形態に係る基板電流の発生メカニズム (放電期)の説明図 である。 FIG. 7D is an explanatory diagram of the generation mechanism (discharge period) of the substrate current according to the first embodiment of the present invention.
圆 8]本発明の第 1実施形態に係る基板電流の波形力 コンタクトホールのエッジを 抽出する原理の説明図である。 8] Waveform force of substrate current according to the first embodiment of the present invention is an explanatory diagram of the principle of extracting the edge of a contact hole.
[図 9]本発明の第 2実施形態に係る半導体測定装置の動作の流れを示すフローチヤ ートである。 FIG. 9 is a flowchart showing a flow of operations of the semiconductor measuring apparatus according to the second embodiment of the present invention. It is
圆1— 圆 1—
〇 10]本発明の第 3実施形態に係る半導体測定装置の動作の流れを示すフローチ ヤートである。  O 10] A flow chart showing the flow of operation of the semiconductor measuring apparatus according to the third embodiment of the present invention.
圆 11]本発明の第 3実施形態に係る半導体測定装置の測定対象であるホール構造 の等価回路を示す図である。 [11] FIG. 11 is a diagram showing an equivalent circuit of a hole structure which is a measurement target of the semiconductor measurement apparatus according to the third embodiment of the present invention.
圆 12]本発明の第 3実施形態に係る測定対象であるホール構造に電子ビームを照 射したときの、電子ビーム照射量と表面電位との非線形関係を示す特性図である。 符号の説明 FIG. 12 is a characteristic diagram showing a non-linear relationship between the electron beam irradiation amount and the surface potential when an electron beam is irradiated onto the hole structure that is the measurement object according to the third embodiment of the present invention. Explanation of symbols
電子銃  Electron gun
11 電子ビーム源  11 Electron beam source
12 コンデンサレンズ  12 condenser lens
13 ァパチヤ一  13 Apachiya
14 偏向電極  14 Deflection electrode
15 対物レンズ  15 Objective lens
20 真空チャンノ ー  20 Vacuum channel
21 ΧΥステージ  21 ΧΥ Stage
22 卜レイ  22 Aoi Rei
23 半導体基板 (試料)  23 Semiconductor substrate (sample)
24 2次電子検出器  24 Secondary electron detector
30 電流測定装置  30 Current measuring device
40 高圧電源  40 High voltage power supply
100 シーケンス制御装置  100 sequence controller
110 フォーカス制御装置  110 Focus control device
120 二次電子画像記録装置  120 Secondary electron image recording device
130 基板電流波形記録装置  130 Substrate current waveform recorder
140 波形処理装置  140 Waveform processor
150 エッジ抽出装置  150 Edge extractor
160 表示装置 170 データベース装置 160 Display device 170 Database device
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0018] 次に本発明を実施するための最良の形態について、図面を参照して説明する。 Next, the best mode for carrying out the present invention will be described with reference to the drawings.
[第 1実施形態]  [First embodiment]
図 1に、本発明の第 1実施形態による半導体測定装置の構成を示す。  FIG. 1 shows the configuration of the semiconductor measuring apparatus according to the first embodiment of the present invention.
この半導体測定装置は、測定対象物 (試料)である半導体基板に電子ビームを照 射し、該電子ビームによって誘起された基板電流を測定し、該基板電流から上記半 導体基板に形成されたホール等の微細構造の評価値を得ることを基本原理としてい る。  This semiconductor measuring apparatus irradiates a semiconductor substrate, which is a measurement object (sample), with an electron beam, measures a substrate current induced by the electron beam, and forms a hole formed in the semiconductor substrate from the substrate current. The basic principle is to obtain an evaluation value of the microstructure such as
[0019] 同図に示すように、測定対象物 (試料)である半導体基板 23を収容するチャンバ一 20の上部には、電子ビーム EBを発生する電子銃 10が取り付けられている。電子銃 10は電子ビーム源 11を備え、この電子ビーム源 11には高圧電源 40が接続されて ヽ る。電子銃 10の内部には、上記電子ビーム源 11からの電子流の放出方向に沿って 、コンデンサレンズ 12、ァパチヤ一 13、偏向電極 14、対物レンズ 15がこの順に配置 されている。このうち、偏向電極 14には偏向制御装置 50が接続され、電子ビーム EB を高精度で偏向可能となっている。また、電子ビーム EBのエネルギー、電流量、フォ 一カス状態も任意に制御可能となって 、る。  As shown in the figure, an electron gun 10 that generates an electron beam EB is attached to an upper portion of a chamber 20 that houses a semiconductor substrate 23 that is a measurement object (sample). The electron gun 10 includes an electron beam source 11, and a high voltage power source 40 is connected to the electron beam source 11. Inside the electron gun 10, a condenser lens 12, an aperture 13, a deflection electrode 14, and an objective lens 15 are arranged in this order along the emission direction of the electron flow from the electron beam source 11. Among these, a deflection control device 50 is connected to the deflection electrode 14 so that the electron beam EB can be deflected with high accuracy. In addition, the energy, current amount, and focus state of the electron beam EB can be arbitrarily controlled.
[0020] チャンバ一 20の内部には、半導体基板 23を支持するための XYステージ 21と、こ の XYステージ 21上に固定されたトレイ 22とが収容され、トレイ 22上には半導体基板 23が載置されている。上記電子銃 10から放出される電子ビーム EBの照射方向は、 トレイ 22上に載置された半導体基板 23の表面に向けられており、 XYステージ 21でト レイ 22の位置を移動させることにより、半導体基板 23に対する電子ビーム EBの照射 位置を調整することが可能となって 、る。  An XY stage 21 for supporting the semiconductor substrate 23 and a tray 22 fixed on the XY stage 21 are accommodated in the chamber 20, and the semiconductor substrate 23 is placed on the tray 22. It is placed. The irradiation direction of the electron beam EB emitted from the electron gun 10 is directed to the surface of the semiconductor substrate 23 placed on the tray 22, and by moving the position of the tray 22 by the XY stage 21, The irradiation position of the electron beam EB to the semiconductor substrate 23 can be adjusted.
[0021] また、チャンバ一 20内部には、電子ビーム EBの照射に伴って半導体基板 23の表 面力も放出される二次電子を検出するための二次電子検出器 24が設けられている。 他には、チャンバ一 20内部には、半導体基板 23にバイアス電圧を印加するための 図示しな!、電極が設けられ、この電極にノィァス電圧を供給する電圧印加装置はチ ヤンバー 20外部に設けられている。チャンバ一 20の内部の真空度は、例えば 10の マイナス 6乗 [torr]程度に維持される。 In addition, a secondary electron detector 24 for detecting secondary electrons, whose surface force is also emitted from the semiconductor substrate 23 when the electron beam EB is irradiated, is provided inside the chamber 120. In addition, an electrode is provided inside the chamber 20 for applying a bias voltage to the semiconductor substrate 23, an electrode is provided, and a voltage applying device for supplying a noise voltage to the electrode is provided outside the chamber 20. It has been. The degree of vacuum inside the chamber 20 is, for example, 10 It is maintained at minus 6 [torr].
[0022] ここで、電子銃 10から照射された電子ビーム EBを nmオーダーの位置精度で半導 体基板に照射するために、固定された電子ビーム EBの照射軸に対して相対的に半 導体基板 23の位置を XYステージ 21により移動させるようになって 、る。 XYステージ 21の駆動装置としてはノ ルスモーターや超音波モーターあるいは圧電素子などが 利用される。レーザー測長器やレーザースケール等高精度測定技術を併用すること により、 XYステージ 21上に載置された半導体基板 23の位置精度は数 nm程度に制 御される。 Here, in order to irradiate the semiconductor substrate with the electron beam EB irradiated from the electron gun 10 with a position accuracy of the order of nm, the semiconductor is relatively relative to the irradiation axis of the fixed electron beam EB. The position of the substrate 23 is moved by the XY stage 21. As a drive device for the XY stage 21, a Norse motor, an ultrasonic motor, or a piezoelectric element is used. By using high-precision measurement technology such as a laser length measuring instrument and laser scale, the positional accuracy of the semiconductor substrate 23 placed on the XY stage 21 is controlled to about several nm.
[0023] トレイ 22には、電流測定装置 30が接続されており、半導体基板 23に誘起された基 板電流がトレイ 22を介して電流測定装置 30により測定されるようになっている。電流 測定装置 30は、測定した基板電流値をデジタル信号に AZD変換する AZD変換 器を備えており、測定値をデジタルデータとして出力する。  A current measuring device 30 is connected to the tray 22, and a substrate current induced in the semiconductor substrate 23 is measured by the current measuring device 30 via the tray 22. The current measuring device 30 includes an AZD converter that AZD converts the measured substrate current value into a digital signal, and outputs the measured value as digital data.
[0024] また、トレイ 22には、半導体基板 23上での電子ビーム EBの照射位置を測定するた めの電子ビーム照射位置測定装置 22Aが取り付けられて 、る。電子ビーム照射位置 測定装置 22Aは、測定した電子ビーム照射位置の座標 (電子ビームの照射座標)を 出力する。この電子ビーム照射位置測定装置 22Aによって得られた電子ビームの照 射座標は、後述の二次電子画像および基板電流波形を形成するためのパラメータと して使用される。なお、電子ビーム EBの照射位置の座標系は特に限定されない。  The tray 22 is provided with an electron beam irradiation position measuring device 22A for measuring the irradiation position of the electron beam EB on the semiconductor substrate 23. Electron beam irradiation position measurement device 22A outputs the coordinates of the measured electron beam irradiation position (electron beam irradiation coordinates). The irradiation coordinates of the electron beam obtained by the electron beam irradiation position measuring device 22A are used as parameters for forming a secondary electron image and a substrate current waveform, which will be described later. The coordinate system of the irradiation position of the electron beam EB is not particularly limited.
[0025] また、本半導体測定装置は、シーケンス制御装置 (パターンマッチングエンジンを 含む) 100、フォーカス制御装置 110、二次電子画像記録装置 120、基板電流波形 記録装置 130、波形処理装置 140、エッジ抽出装置 150、表示装置 160、データべ ース装置 170を備え、これらは、コンピュータ等の情報処理装置上に構築されている  [0025] In addition, the semiconductor measurement apparatus includes a sequence control apparatus (including a pattern matching engine) 100, a focus control apparatus 110, a secondary electron image recording apparatus 120, a substrate current waveform recording apparatus 130, a waveform processing apparatus 140, and an edge extraction. Device 150, display device 160, and database device 170, which are built on an information processing device such as a computer.
[0026] このうち、シーケンス制御装置 100は、基板電流の測定時に電子ビーム EBが半導 体基板 23の表面を走査するように偏向制御装置 50を制御すると共に、半導体基板 に対する電子ビームの照射位置を設定する際に電子ビーム EBの照射位置を高精度 に調整するためのパターンマッチングに関する制御を担うものである。 Among these, the sequence control device 100 controls the deflection control device 50 so that the electron beam EB scans the surface of the semiconductor substrate 23 when the substrate current is measured, and the irradiation position of the electron beam on the semiconductor substrate. It controls the pattern matching to adjust the irradiation position of the electron beam EB with high accuracy.
なお、本実施形態では、 1次元走査とはライン状に走査することを意味する。また、 2次元走査とは、ライン状の走査を一定の間隔で複数回にわたって繰り返すことを意 味し、例えばテレビ画面における水平走査および垂直走査と同様の概念である。 In the present embodiment, the one-dimensional scanning means scanning in a line shape. Also, Two-dimensional scanning means that line-shaped scanning is repeated a plurality of times at regular intervals, and is a concept similar to horizontal scanning and vertical scanning on a television screen, for example.
[0027] ここで、パターンマッチングについて補足説明すると、半導体基板上に形成された ホール等のパターンの位置は、同一ロットであっても半導体基板ごとにわずかに異な る。これを調整するため、 XYステージ 21による位置合わせと併用して、半導体基板 ごとに実際のパターンと基準パターンとを比較するパターンマッチングを実施し、実 際のパターンと基準パターンとが一致するように電子ビーム EBの照射位置をシフト する。これにより、半導体基板ごとに数 nmの精度で電子ビームの照射位置を正確に 調整する。 [0027] Here, a supplementary explanation will be given for pattern matching. The positions of patterns such as holes formed on a semiconductor substrate are slightly different for each semiconductor substrate even in the same lot. In order to adjust this, combined with alignment by the XY stage 21, pattern matching is performed to compare the actual pattern and the reference pattern for each semiconductor substrate so that the actual pattern matches the reference pattern. Shift the irradiation position of electron beam EB. This makes it possible to accurately adjust the irradiation position of the electron beam with an accuracy of several nm for each semiconductor substrate.
[0028] 本半導体測定装置は、パターンマッチングにおいて電子ビーム EBの照射位置を 精度よくシフトさせるため、電子ビーム EBを正確に直線走査するための高分解能の 偏向制御装置 50を備え、また、シーケンス制御装置 100は、パターンマッチングを実 施するための画像認識装置 (パターンマッチングエンジンを含む)およびソフトウェア 一等を備える。  [0028] The semiconductor measurement apparatus includes a high-resolution deflection control device 50 for accurately linearly scanning the electron beam EB in order to accurately shift the irradiation position of the electron beam EB in pattern matching, and also performs sequence control. The apparatus 100 includes an image recognition apparatus (including a pattern matching engine) and software for performing pattern matching.
[0029] フォーカス制御装置 110は、対物レンズ 15のフォーカス位置を制御するものであり 、測定時に対物レンズ 15のフォーカス位置を制御することにより電子ビームのフォー カス量を制御し、この電子ビーム EBの先端を所望のサイズ及び形状に設定するため のものである。電子ビーム EBのフォーカス量(対物レンズ 15のフォーカス位置)を設 定する方法としては、ウェハー表面力 の距離を光学的あるいは電気的に求めて、 その距離を元にフォーカス量を設定する方法、電子ビームを走査して得られた画像 が最も鮮明になる状態あるいは二次電子のコントラストが最大になる状態力もフォー カス量を設定する方法、電子ビームを照射した際の基板電流値によって得られる画 像が最も鮮明になる状態あるいはコントラストが最大になる状態力もフォーカス量を設 定する方法などの方法を利用することができる。  The focus control device 110 controls the focus position of the objective lens 15, and controls the focus amount of the objective lens 15 during measurement to control the focus amount of the electron beam. This is for setting the tip to a desired size and shape. As a method of setting the focus amount of the electron beam EB (focus position of the objective lens 15), the distance of the wafer surface force is obtained optically or electrically, and the focus amount is set based on the distance. A method that sets the amount of focus for the state in which the image obtained by scanning the beam is the clearest or the state force that maximizes the contrast of the secondary electrons, and the image obtained by the substrate current value when the electron beam is irradiated A method such as a method of setting the focus amount can be used for the state where the image becomes the clearest or the state force that maximizes the contrast.
[0030] 二次電子画像記録装置 120は、二次電子検出器 24によって検出された二次電子 により形成される画像を記録するものである。基板電流波形記録装置 130は、電流 測定装置 30によって測定された基板電流値の波形を、そのときの電子ビーム EBの 照射座標と対応づけて記憶するものであり、この照射座標は、上述の電子ビーム照 射位置記録装置 22Aから読み出される。 The secondary electron image recording device 120 records an image formed by secondary electrons detected by the secondary electron detector 24. The substrate current waveform recording device 130 stores the waveform of the substrate current value measured by the current measuring device 30 in association with the irradiation coordinates of the electron beam EB at that time. Beam illumination It is read from the shooting position recording device 22A.
[0031] 波形処理装置 140は、上記基板電流値の波形を波形整形して不要なノイズ成分を 除去するものである。エッジ抽出装置 150は、波形整形された基板電流波形からコン タクトホールのエッジを抽出し、このコンタクトホールの形状に関する評価値を演算す るものである。表示装置 160は、上記評価値を表示するものである。データベース装 置 170は、エッジ抽出装置 150で演算された上記評価値をデータベース化して格納 するものである。 [0031] The waveform processing device 140 shapes the waveform of the substrate current value to remove unnecessary noise components. The edge extraction device 150 extracts the contact hole edge from the waveform-shaped substrate current waveform, and calculates an evaluation value related to the shape of the contact hole. The display device 160 displays the evaluation value. The database device 170 stores the evaluation values calculated by the edge extraction device 150 in a database.
[0032] 次に、図 2に示すフローに沿って、本半導体測定装置の動作を説明する。ここでは 、コンタクトホールを測定対象として説明する。  Next, the operation of the semiconductor measurement apparatus will be described along the flow shown in FIG. Here, a contact hole will be described as a measurement target.
先ず、シーケンス制御装置 100の制御の下に、電子ビーム EBと半導体基板 23との 位置合わせを行う。即ち、半導体基板 23を保持している XYステージ 21の制御系に 対して測定対象のホールの位置座標を指定して XYステージ 21を移動させ、電子ビ ーム EBの照射位置にホールの中心を大まかに合わせる。そして、電子ビーム EBを 2 次元走査しながら照射し、そのときに発生する二次電子による画像とテンプレート画 像とを比較してパターンマッチングを行い、テンプレート画像の中心とホールの中心 とのずれ量を算出する。このずれ量を偏向制御装置 50に入力し、電子ビーム EBの 照射位置をシフトさせて電子ビーム EBの照射位置を測定対象のホール中心に正確 に合わせる。  First, alignment of the electron beam EB and the semiconductor substrate 23 is performed under the control of the sequence controller 100. That is, the position coordinate of the hole to be measured is specified with respect to the control system of the XY stage 21 holding the semiconductor substrate 23, the XY stage 21 is moved, and the center of the hole is set at the irradiation position of the electron beam EB. Match roughly. Then, the electron beam EB is irradiated while scanning two-dimensionally, and pattern matching is performed by comparing the image of secondary electrons generated at that time with the template image, and the amount of deviation between the center of the template image and the center of the hole Is calculated. This deviation amount is input to the deflection controller 50, and the irradiation position of the electron beam EB is shifted so that the irradiation position of the electron beam EB is accurately aligned with the center of the hole to be measured.
[0033] 上述の位置合わせが終了すると、シーケンス制御装置 100の制御の下、基板電流 力 ホールの評価値を算出するための以下の一連の処理 (ステップ S 11〜S 14)を 実行する。  When the above alignment is completed, the following series of processes (steps S 11 to S 14) for calculating the evaluation value of the substrate current force hole are executed under the control of the sequence control device 100.
先ず、半導体基板 23に電子ビーム EBを照射して基板電流波形を取得する (ステツ プ Sl l)。即ち、ホール中心を基準として電子ビーム EBにより半導体基板 23の表面 上の所定領域を 2次元走査する。この 2次元装置では、半導体基板 23の表面に対し て電子ビーム EBを垂直に照射し、電子ビーム EBの先端が所望のサイズになるように 対物レンズ 15のフォーカス位置を制御すると共に、偏向制御装置 50に制御電圧を 加えることにより 1次元走査を等間隔かつ一定速度で繰り返し行う(例えば、等間隔で 10回の 1次元走査を行う)。この走査により、電子ビーム EBが照射された半導体基板 23の表面上の微小領域から二次電子および反射電子が生じ、また半導体基板 23に 基板電流が誘起される。 First, the substrate current waveform is acquired by irradiating the semiconductor substrate 23 with the electron beam EB (step Sl l). That is, a predetermined region on the surface of the semiconductor substrate 23 is two-dimensionally scanned by the electron beam EB with reference to the hole center. In this two-dimensional apparatus, the electron beam EB is irradiated perpendicularly to the surface of the semiconductor substrate 23, the focus position of the objective lens 15 is controlled so that the tip of the electron beam EB has a desired size, and the deflection control device By applying a control voltage to 50, one-dimensional scanning is repeated at regular intervals and at a constant speed (for example, 10 one-dimensional scannings are performed at regular intervals). The semiconductor substrate irradiated with the electron beam EB by this scanning Secondary electrons and reflected electrons are generated from a minute region on the surface of the substrate 23, and a substrate current is induced in the semiconductor substrate 23.
[0034] 上述の走査により半導体基板 23に誘起された基板電流は、電流測定装置 30によ つて測定され、必要なダイナミックレンジを有する電気信号に変換される。この電気信 号は、信号の品質が劣化しないように即座にサンプリングされて、必要な分解能を持 つデジタル信号に変換される。例えば、このデジタル信号の分解能は 16ビットであり 、そのサンプリング周波数は 400MHzである。上述の基板電流の測定と並行して、電 子ビーム照射位置測定装置 22Aにより電子ビーム EBの照射位置が測定される。  The substrate current induced in the semiconductor substrate 23 by the above-described scanning is measured by the current measuring device 30 and converted into an electric signal having a necessary dynamic range. This electrical signal is immediately sampled and converted to a digital signal with the required resolution so that the signal quality is not degraded. For example, the resolution of this digital signal is 16 bits and its sampling frequency is 400 MHz. In parallel with the above-described measurement of the substrate current, the irradiation position of the electron beam EB is measured by the electron beam irradiation position measuring device 22A.
[0035] このようにして電子ビーム EBの走査により得られた基板電流の測定値は、ホールの 底面の構造に関する情報を含み、上述の電子ビーム照射位置測定装置により測定 された測定座標 (電子ビームの照射位置)又は測定時間 (電子ビーム EBの照射時刻 )の関数で表される波形情報として、基板電流波形記録装置 130 (例えばメモリー、 ハードディスク)にデジタル記録される。  The measurement value of the substrate current obtained by scanning the electron beam EB in this way includes information on the structure of the bottom surface of the hole, and the measurement coordinates (electron beam) measured by the above-described electron beam irradiation position measuring device. As a waveform information expressed as a function of measurement time (irradiation time of electron beam EB) or digitally recorded on a substrate current waveform recording device 130 (for example, a memory or a hard disk).
[0036] 一方、上述の走査により半導体基板 23の表面上の微小領域から発生した二次電 子は、二次電子検出器 24によって検出される。この二次電子の検出には良く知られ たフォトマルチプライヤーやマルチチャンネルプレートあるいは単純な電極を用いて 直接二次電子を回収し、電流信号とする方法がある。ここで、重要な事は、二次電子 検出装置 24で検出される二次電子の量が実際に発生する二次電子の量に比例す る関係が得られる事であり、本実施形態では、二次電子検出器 24の出力値は、入力 した電子数に正確に比例するように設定される。これにより、小信号領域から大信号 領域に至るまで二次電子を直線的に検出する。  On the other hand, secondary electrons generated from a minute region on the surface of the semiconductor substrate 23 by the above-described scanning are detected by the secondary electron detector 24. The secondary electrons can be detected by using a well-known photomultiplier, multichannel plate, or simple electrode to directly collect secondary electrons and use them as current signals. Here, the important thing is that a relationship in which the amount of secondary electrons detected by the secondary electron detector 24 is proportional to the amount of secondary electrons actually generated can be obtained. The output value of the secondary electron detector 24 is set to be exactly proportional to the number of input electrons. As a result, secondary electrons are detected linearly from the small signal region to the large signal region.
[0037] これに対し、通常の SEMでは、二次電子を 2値画像として表現する事を目的として Vヽるため、信号がある場合と無!、場合で検出値が大きな差を持つように設定されて!ヽ る。即ち、非常に少ない電子が検出器に入力されている場合は検出値は 0とされ、あ る閾値以上の電子が入力されると大きな検出値を発生するような非線形特性を有す る増幅器になっている。  [0037] On the other hand, in ordinary SEM, the secondary electron is expressed for the purpose of expressing it as a binary image, so that the detected value has a large difference between when there is a signal and when there is no signal. It is set! That is, the detection value is set to 0 when very few electrons are input to the detector, and the amplifier has nonlinear characteristics that generate a large detection value when electrons exceeding a certain threshold are input. It has become.
[0038] 上述の走査により得られた二次電子の測定値は、半導体基板 23の表面構造に関 する情報を含み、電子ビーム照射位置測定装置 22Aにより測定された測定座標 (電 子ビームの照射位置)又は測定時間(電子ビーム EBの照射時刻)の関数で表される 画像情報として、二次電子画像記録装置 120 (例えばメモリー、ハードディスク)にデ ジタル記録される。 [0038] The measurement value of the secondary electrons obtained by the above-mentioned scanning includes information on the surface structure of the semiconductor substrate 23, and the measurement coordinates (electricity) measured by the electron beam irradiation position measurement device 22A. Digital information is recorded in the secondary electron image recording device 120 (for example, a memory or a hard disk) as image information expressed as a function of a child beam irradiation position) or a measurement time (electron beam EB irradiation time).
また、半導体基板 23の表面上の微小領域力も発生した反射電子については、図 示しない反射電子検出器によって検出され、その検出値から得られる反射電子画像 が図示しない反射電子画像記録装置にデジタル記録される。  Also, the backscattered electrons that have generated micro-region forces on the surface of the semiconductor substrate 23 are detected by a backscattered electron detector (not shown), and the backscattered electron image obtained from the detected value is digitally recorded on a backscattered electron image recording device (not shown). Is done.
[0039] なお、二次電子と反射電子はエネルギーや放出方向の差によって区別できるが、 検出装置の種類によっては、区別せずに一緒にして取り扱うことも出来る。また、二 次電子検出器 24および反射電子検出器(図示なし)のそれぞれについては、複数台 配置してもよぐその場合は検出器の台数に応じて独立に情報を記録できる構成と することが望ましい。もちろん、二次電子検出器 24および反射電子検出器(図示なし )のそれぞれを 1台づっ配置してもよい。  Note that secondary electrons and reflected electrons can be distinguished by differences in energy and emission direction, but depending on the type of detection device, they can be handled together without being distinguished. In addition, for each of the secondary electron detector 24 and the backscattered electron detector (not shown), a plurality of units may be arranged. In such a case, information shall be recorded independently according to the number of detectors. Is desirable. Of course, each of the secondary electron detector 24 and the backscattered electron detector (not shown) may be arranged one by one.
[0040] 以上のようにして測定された基板電流の波形は、不要なノイズや高周波成分を除 去するために、波形処理装置 140により波形整形される。上記波形処理の例として は、移動平均フィルター処理、特定の周波数を取り除く波形処理、あるいは特定の周 波数の信号だけを取り出すフィルター処理等がある。これらの波形整形処理はハー ドウエアで行われても、ソフトウエアーで行われても良 ヽ。  [0040] The waveform of the substrate current measured as described above is shaped by the waveform processing device 140 in order to remove unnecessary noise and high frequency components. Examples of the waveform processing include moving average filter processing, waveform processing for removing a specific frequency, or filter processing for extracting only a signal of a specific frequency. These waveform shaping processes can be performed in hardware or software.
[0041] 続いて、エッジ抽出装置 150により、基板電流の波形力もホールのエッジを抽出す る(ステップ S12)。即ち、エッジ抽出装置 150は、エッジ抽出アルゴリズムを用いて、 上述の基板電流波形の中からホールのエッジを抽出し、この抽出されたエッジの座 標値を XY座標系に変換する。本実施形態は、このエッジ抽出アルゴリズムの原理に 特徴を有しており、この詳細については後述する。  Subsequently, the edge extraction device 150 also extracts the edge of the hole with respect to the waveform force of the substrate current (step S12). In other words, the edge extraction device 150 extracts an edge of a hole from the above-described substrate current waveform using an edge extraction algorithm, and converts the extracted edge coordinate value into the XY coordinate system. This embodiment has a feature in the principle of the edge extraction algorithm, and details thereof will be described later.
[0042] また、エッジ抽出装置 150は、変換された XY座標値に対して円近似関数または楕 円近似関数を適用し (ステップ S 13)、最少自乗法をもちいてカーブフィティングする 。即ち、上述の電流波形のエッジ座標は、ホールのエッジ座標に対応しており、 1次 元走査によって得られた基板電流波形のエッジの座標値を結ぶことにより、ホールの エッジの形状を再現することができる。  [0042] Further, the edge extraction device 150 applies a circle approximation function or an ellipse approximation function to the converted XY coordinate values (step S13), and performs curve fitting using the least square method. In other words, the edge coordinates of the current waveform described above correspond to the edge coordinates of the hole, and the shape of the edge of the hole is reproduced by connecting the coordinate values of the edge of the substrate current waveform obtained by one-dimensional scanning. be able to.
[0043] そこで、上述のエッジの座標値に対して近似関数を適用することにより、ホールの 2 次元的形状を数学的に表現する。具体的には、上述の変換されたエッジの座標値に 対して例えば円または楕円の近似関数を適用し、この近似関数の値とエッジの座標 値との誤差が最小になるように、近似関数を規定する各種のパラメータをフイツティン グする。これにより、ホールの 2次元的形状が表現される。このような近似関数を用い ると、ホールの相対位置がずれてもホール形状は正確に維持されるので、ァライメン トの誤差が生じても、ホールの測定値に与える影響を小さく抑えることが出来る。なお 、近似関数としてどのような関数を採用するかは、測定対象のホールの設計パターン 力 適切に決定される。 [0043] Therefore, by applying an approximation function to the above-mentioned edge coordinate values, Mathematical expression of dimensional shape. Specifically, an approximate function of, for example, a circle or an ellipse is applied to the above-described converted edge coordinate value, and the approximation function is set so that the error between the approximate function value and the edge coordinate value is minimized. Fitting various parameters that specify This represents the two-dimensional shape of the hole. If such an approximate function is used, the hole shape is accurately maintained even if the relative positions of the holes are deviated. Therefore, even if an alignment error occurs, the effect on the measured value of the hole can be kept small. . It should be noted that what kind of function is adopted as the approximate function is appropriately determined by the design pattern force of the hole to be measured.
[0044] また、エッジ抽出装置 150は、パラメータがフィッティングされた上述の近似関数を 用いて、ホール形状の評価値を演算する (ステップ S 14)。例えば、ホールの評価値 としは、ホールの直径、ホール中心位置、ホール傾斜角度、ホール回転角度、ホー ル真円度、ホール歪量、エッジラフネス等が演算される。近似関数として楕円関数を 用いた場合には、楕円の長径、短径、焦点、歪、回転などが演算される。これらの評 価値は、コンピュータディスプレイ等の表示装置 160に表示され、或いはデータべ一 ス装置 170にデジタルデータとして保管される。  [0044] Further, the edge extraction device 150 calculates the evaluation value of the hole shape by using the above approximate function to which the parameter is fitted (step S14). For example, the hole evaluation value includes the hole diameter, hole center position, hole inclination angle, hole rotation angle, hole roundness, hole distortion, edge roughness, and the like. When an elliptic function is used as an approximate function, the major axis, minor axis, focus, distortion, rotation, etc. of the ellipse are calculated. These values are displayed on a display device 160 such as a computer display or stored as digital data in a database device 170.
[0045] 次に、上述のエッジ抽出装置 150におけるエッジ抽出アルゴリズムの原理を詳細に 説明する。本エッジ抽出アルゴリズムは、測定された基板電流の波形を微分波形と見 なしたときの該基板電流の波形に基づき微細構造の評価値を得ることを本質として おり、そのような評価手段は、例えばエッジ抽出装置 150として構成される。  Next, the principle of the edge extraction algorithm in the edge extraction device 150 will be described in detail. This edge extraction algorithm is based on obtaining an evaluation value of the fine structure based on the waveform of the substrate current when the measured waveform of the substrate current is regarded as a differential waveform. The edge extracting device 150 is configured.
[0046] 図 3は、本半導体測定装置の測定対象であるコンタクトホールの断面構造を示して いる。  FIG. 3 shows a cross-sectional structure of a contact hole that is a measurement target of the semiconductor measurement apparatus.
ここで、図 3Aは、通常のコンタクトホール HAの断面構造を示している。同図に示す ように、シリコン基板 Sの主面には酸ィ匕膜を介して層間絶縁膜 Fが形成され、この層 間絶縁膜 Fを貫通するようにコンタクトホール HAが形成されて ヽる。ホール HAの底 にはシリコン基板 Sが露出している。通常、シリコン基板 Sには P型又は N型の拡散層 が形成されており、この拡散層は導電性を有している。  Here, FIG. 3A shows a cross-sectional structure of a normal contact hole HA. As shown in the figure, an interlayer insulating film F is formed on the main surface of the silicon substrate S via an oxide film, and a contact hole HA is formed so as to penetrate the interlayer insulating film F. . The silicon substrate S is exposed at the bottom of the hole HA. Normally, a P-type or N-type diffusion layer is formed on the silicon substrate S, and this diffusion layer has conductivity.
[0047] 図 3Bは、ゲート G上に形成されたコンタクトホール HBの断面構造を示している。ゲ ート Gは MOSトランジスタを構成する制御電極であり、このゲート G下には非常に薄 い nmオーダーのゲート酸ィ匕膜 GOXが形成されており、その下にはシリコン基板 Sが 存在する。ゲート Gとシリコン基板 Sとはゲート酸ィ匕膜 GOXにより絶縁されており直流 的には接続されていない。 FIG. 3B shows a cross-sectional structure of the contact hole HB formed on the gate G. The gate G is a control electrode that constitutes a MOS transistor, and the gate G is very thin. A gate oxide film GOX of nm order is formed, and a silicon substrate S exists below it. The gate G and the silicon substrate S are insulated from each other by the gate oxide film GOX and are not connected in a direct current.
[0048] 図 3Cは、ゲート G2上に形成されたコンタクトホールの断面構造を示している力 こ の例は、近年注目されているフラッシュメモリーなどで用いられているフローティング ゲート(電気的に孤立したゲート)構造を有している。即ち、ゲート G2の下には電荷を 蓄積するための絶縁体 ONOが存在し、その下に通常のゲート G1が存在する。その ゲート G1の下にはゲート酸ィ匕膜 GOXを介してシリコン基板 Sが存在する。このフロー ティングゲート構造は、上述の図 3Bに示すゲート Gを積み重ねたような構造である。 つまり、絶縁膜が電極を挟んで 2層のゲートが形成されていることに特徴がある。  [0048] FIG. 3C is a force showing the cross-sectional structure of the contact hole formed on the gate G2. This example is a floating gate (electrically isolated) used in flash memory or the like that has attracted attention in recent years. Gate) structure. That is, an insulator ONO for accumulating charges exists under the gate G2, and a normal gate G1 exists under the insulator ONO. Under the gate G1, there is a silicon substrate S through a gate oxide film GOX. This floating gate structure is a structure in which the gate G shown in FIG. 3B is stacked. In other words, the insulating film is characterized in that two layers of gates are formed with the electrode interposed therebetween.
[0049] 上述の図 3 A〜図 3Cにそれぞれ示すコンタクトホール HA〜HCは非常にァスぺク ト比が大きぐ従来の SEMではそのホール底の形状を測定する事はできないが、本実 施形態の半導体測定装置では、細く絞った電子ビーム EBをホール HA〜HCの底 に当たるように照射して、そのときにシリコン基板 Sに誘起される基板電流の変化から ホール底の形状 (サイズ)を特定する。  [0049] The contact holes HA to HC shown in FIGS. 3A to 3C, respectively, have a very large aspect ratio, but a conventional SEM cannot measure the shape of the hole bottom. In the semiconductor measurement apparatus of the embodiment, the electron beam EB that is narrowly focused is irradiated so as to hit the bottom of the holes HA to HC, and the shape (size) of the hole bottom is determined from the change in the substrate current induced in the silicon substrate S at that time. Is identified.
[0050] 図 4A〜図 4Dは、そのようにして実際に観測された基板電流の波形を示して 、る。  [0050] FIGS. 4A to 4D show the waveform of the substrate current actually observed in this manner.
ここで、図 4Aは、上述の図 3Aに示すホール構造に電子ビーム EBを照射した場合 の基板電流の波形であり、ホール底に相当するシリコン基板 Sの表面に N型の拡散 層が形成されている場合の波形である。図 4Bは、同じく上述の図 3Aに示すホール 構造に電子ビーム EBを照射した場合の基板電流の波形であるが、ホール底に相当 するシリコン基板 Sの表面には P型の拡散層が形成されている。図 4Cは、上述の図 3 Bに示すホール構造に電子ビーム EBを照射した場合の基板電流であり、図 4Dは、 上述の図 3Cに示すホール構造に電子ビーム EBを照射した場合の基板電流である  Here, FIG. 4A shows the waveform of the substrate current when the electron beam EB is irradiated on the hole structure shown in FIG. 3A, and an N-type diffusion layer is formed on the surface of the silicon substrate S corresponding to the bottom of the hole. It is a waveform when it is. FIG. 4B shows the waveform of the substrate current when the electron beam EB is irradiated to the hole structure shown in FIG. 3A. A P-type diffusion layer is formed on the surface of the silicon substrate S corresponding to the bottom of the hole. ing. 4C shows the substrate current when the electron beam EB is irradiated to the hole structure shown in FIG. 3B, and FIG. 4D shows the substrate current when the electron beam EB is irradiated to the hole structure shown in FIG. 3C. Is
[0051] 次に、上述の図 4A〜図 4Dに示す各波形が観測される理由を説明する。 Next, the reason why each waveform shown in FIGS. 4A to 4D is observed will be described.
図 5Aは、上述の図 3Aに示す通常のコンタクトホール HAの電気的等価回路を示し ている。コンタクトホール HAの等価回路はシリコン基板 Sの持つ抵抗 R1からなり、照 射された電子ビーム EBは抵抗 R1を通じてシリコン基板 Sに流れる。従って、シリコン 基板 Sの表面に形成された拡散層が N型であるか P型であるかに関わらず、通常のコ ンタクトホール HAに電子ビーム EBを照射した場合には、図 4Aおよび図 4Bに示す ように、台形状の基板電流波形が得られる。 FIG. 5A shows an electrical equivalent circuit of the normal contact hole HA shown in FIG. 3A. The equivalent circuit of the contact hole HA is composed of the resistance R1 of the silicon substrate S, and the irradiated electron beam EB flows to the silicon substrate S through the resistance R1. Therefore, silicon Regardless of whether the diffusion layer formed on the surface of the substrate S is N-type or P-type, when the normal contact hole HA is irradiated with the electron beam EB, as shown in Fig. 4A and Fig. 4B In addition, a trapezoidal substrate current waveform is obtained.
[0052] このような台形状の基板電流波形からは容易にホールのエッジを抽出することが可 能である。例えば、閾値法、最大傾斜法を用いて、基板電流波形のうち、台形を構成 する波形の傾斜領域において、波形が所定の閾値を横切るときの座標、あるいは各 傾斜領域での波形の傾きの最大値を示す座標をホールのエッジと定義して必要個 数のエッジを抽出する。抽出されたエッジに対して、円近似あるいは楕円近似あるい は直線近似などを適用して、ホールの形状を抽出する。これに対し、図 3B, Cに示す ようにホール底にゲートやフローティングゲートが存在するホール構造では、図 4Cお よび図 4Dに示すように、得られる基板電流波形は台形にならな!/、。  It is possible to easily extract the edge of the hole from such a trapezoidal substrate current waveform. For example, using the threshold method and the maximum gradient method, in the slope region of the waveform that forms the trapezoid in the substrate current waveform, the coordinates when the waveform crosses a predetermined threshold value, or the maximum slope of the waveform in each slope region Define the coordinates indicating the value as the edge of the hole and extract the required number of edges. The circle shape, ellipse approximation, or straight line approximation is applied to the extracted edge to extract the shape of the hole. On the other hand, as shown in FIGS. 3B and C, in the hole structure where the gate or floating gate exists at the bottom of the hole, the obtained substrate current waveform must be trapezoidal as shown in FIGS. 4C and 4D. .
[0053] 図 5Bは、上述の図 3Bに示すコンタクトホール HBの電気的等価回路を示しており、 コンタクトホール HBの底にはゲート Gが存在している。この電気的等価回路は、ポリ シリコン力もなるゲート Gとゲート絶縁膜 GOXとシリコン基板 Sとから形成される 1つの コンデンサー C1と、シリコン基板 Sが有する抵抗 R1とから構成され、これらコンデンサ 一 C 1と抵抗 R1とが直列接続された構造になって 、る。これらコンデンサー C 1及び 抵抗 R1により時定数回路が形成され、この時定数はコンデンサー C1の容量値と抵 抗 R1の抵抗値との積で決定される。従って、この場合のホール構造は、コンデンサ 一 C 1の容量値と抵抗 R 1の抵抗値とに比例した時定数を持つ回路と等価になる。な お、ここでは、説明の便宜上、他の寄生 CR成分を無視している。  FIG. 5B shows an electrical equivalent circuit of the contact hole HB shown in FIG. 3B. A gate G exists at the bottom of the contact hole HB. This electrical equivalent circuit is composed of one capacitor C1 formed of a gate G that also has a polysilicon force, a gate insulating film GOX, and a silicon substrate S, and a resistor R1 that the silicon substrate S has. And the resistor R1 are connected in series. The capacitor C 1 and the resistor R1 form a time constant circuit, and this time constant is determined by the product of the capacitance value of the capacitor C1 and the resistance value of the resistor R1. Therefore, the Hall structure in this case is equivalent to a circuit having a time constant proportional to the capacitance value of the capacitor C1 and the resistance value of the resistor R1. Here, other parasitic CR components are ignored for convenience of explanation.
[0054] 図 5Cは、上述の図 3Cに示すコンタクトホール HCの電気的等価回路を示しており 、図 3Cに示すように、コンタクトホール HCの底には、ゲート G2、絶縁膜 ONO、ゲー ト Gl、ゲート酸化膜 GOX、シリコン基板 Sが存在している。図 5C力も理解されるよう に、このホール構造には、ゲート G2及びゲート G1の 2つのゲートと、ゲート酸化膜 G OX及び窒化膜 ONOの 2つの絶縁膜が存在する。この 2つの電極と 2つの絶縁膜は 、直列接続されたコンデンサー CI, C2を形成する。また、シリコン基板 Sは抵抗 Rを 形成する。これらコンデンサー CI, C2及び抵抗 R1は直列接続され、従って、この場 合のホール構造は、コンデンサー CI, C2を直接接続した時の容量値と抵抗 R1の抵 抗値とからなる時定数を有する回路と等価になる。 FIG. 5C shows an electrical equivalent circuit of the contact hole HC shown in FIG. 3C. As shown in FIG. 3C, the bottom of the contact hole HC has a gate G2, an insulating film ONO, and a gate. Gl, gate oxide GOX, and silicon substrate S exist. As shown in FIG. 5C, the hole structure includes two gates, a gate G2 and a gate G1, and two insulating films, a gate oxide film GOX and a nitride film ONO. The two electrodes and the two insulating films form capacitors CI and C2 connected in series. The silicon substrate S forms a resistor R. These capacitors CI, C2 and resistor R1 are connected in series.Therefore, the hole structure in this case is the capacitance value and resistance of resistor R1 when capacitors CI, C2 are directly connected. This is equivalent to a circuit having a time constant composed of a resistance value.
[0055] ここで、図 6Aに示すように、一般に、コンデンサー Cと抵抗 Rとを直列接続すると、 微分回路が得られる。この微分回路に対して図 6Bに示すような矩形波形を入力する と、この矩形波形が微分され、図 6Cに示すように、矩形波形の傾斜量に比例する成 分を有する微分波形が出力される。ここで、入力される矩形波形は、その立ち上がり 及び立下りにおいて、プラス及びマイナスの両方向の傾斜を持つので、出力される 微分波形は、プラス及びマイナスの両方の値を有する出力が得られる。  Here, as shown in FIG. 6A, generally, when a capacitor C and a resistor R are connected in series, a differentiation circuit is obtained. When a rectangular waveform as shown in FIG. 6B is input to the differentiating circuit, the rectangular waveform is differentiated, and a differential waveform having a component proportional to the amount of inclination of the rectangular waveform is output as shown in FIG. 6C. The Here, since the input rectangular waveform has both positive and negative slopes at the rise and fall, an output having both positive and negative values can be obtained.
[0056] つまり、微分回路によれば、一方向に流れる矩形の電流波形からプラス及びマイナ スの両方に流れる電流が生成される。この波形は、測定対象の持つ時定数や測定の ために照射される電子ビーム EBの走査速度などによって影響を受ける力 いずれに しても、測定対象のホール構造に微分回路が存在すると、一方向に流れる電流しか 供給していなくても、プラス及びマイナス両方に流れる電流が観測される。従って、上 述の図 4C, Dに示す波形から、図 3B, Cに示すホール構造の等価回路は微分回路 を含むことが分かる。  That is, according to the differentiating circuit, a current that flows in both plus and minus is generated from a rectangular current waveform that flows in one direction. This waveform is unidirectional if there is a differential circuit in the hole structure of the measurement object, regardless of the time constant of the measurement object or the force affected by the scanning speed of the electron beam EB irradiated for measurement. Even if only the current flowing through is supplied, both positive and negative currents are observed. Therefore, it can be seen from the waveforms shown in FIGS. 4C and 4D that the equivalent circuit of the hole structure shown in FIGS. 3B and 3C includes a differentiation circuit.
[0057] ここで、上述の図 3B、 Cのように、ホール底にゲートが存在し、シリコン基板 Sが露 出して ヽな 、場合の基板電流の発生メカニズムにつ 、て説明しておく。  Here, as shown in FIGS. 3B and 3C described above, the generation mechanism of the substrate current in the case where the gate exists at the bottom of the hole and the silicon substrate S is exposed will be described.
図 7Aは、電子ビーム EBが測定対象に照射された初期 (イメージチャージ形成期) に起こる電荷の再分布の様子を示している。同図では、電子ビーム EBが、図の左側 力 右側に向かって一定速度で走査する。  Fig. 7A shows the state of charge redistribution that occurs in the initial stage (image charge formation period) when the measurement target is irradiated with the electron beam EB. In the figure, the electron beam EB scans at a constant speed toward the left side force and right side of the figure.
[0058] 電子ビーム EBの照射位置が測定対象のコンタクトホールに到達し、そのホール底 に存在するゲート Gに電子ビーム EBが照射されると、ゲート Gの表面から二次電子が 発生すると共に、表面に残った電荷によって基板側にイメージチャージ ICGが誘起さ れる。イメージチャージ ICGの蓄積量は、ゲート Gとゲート酸ィ匕膜 GOXとで形成され るコンデンサーの容量値によって定まる。このときのイメージチャージ ICGの形成に伴 V、基板電流 IKが観測される。このときの電流は次式により表現される。  [0058] When the irradiation position of the electron beam EB reaches the contact hole to be measured and the gate G existing at the bottom of the hole is irradiated with the electron beam EB, secondary electrons are generated from the surface of the gate G, Image charge ICG is induced on the substrate side by the charge remaining on the surface. The amount of image charge ICG accumulated is determined by the capacitance value of the capacitor formed by gate G and gate oxide film GOX. V and substrate current IK are observed as the image charge ICG is formed. The current at this time is expressed by the following equation.
1=1 (l-exp(-AA))  1 = 1 (l-exp (-AA))
0  0
t: time constant  t: time constant
[0059] 図 7Bは、上述のイメージチャージ形成期の次の段階を示している。この例では、ゲ 一ト酸ィ匕膜の膜厚は 10nm程である。電子ビーム EBの照射が始まってから時間がた つと、ゲート Gの電極上に電荷が蓄積し、ゲート Gの電位が照射電流量に比例して上 昇する。そして、図 7Cに示すように、ゲート Gの電位が例えば約 10Vを超えると、その ときの電界 Eは lOMVZcmとなり、膜厚が lOnm程のゲート酸化膜 GOXの中をトン ネル電流 ITが流れ始め、電荷が移動する。このとき、表面電位が一定に成るようにト ンネル電流 ITが生じ、この結果、表面の電位は一定に保たれる。このときのトンネル 電流 ITも基板電流 IKとして観測される。このときの電流は次式により表現される。 I=AE2exp(-B/E) FIG. 7B shows the next stage of the image charge formation period described above. In this example, The thickness of the mono-acid film is about 10 nm. As time elapses after irradiation of the electron beam EB begins, charges accumulate on the electrode of the gate G, and the potential of the gate G rises in proportion to the amount of irradiation current. Then, as shown in FIG. 7C, when the potential of the gate G exceeds, for example, about 10 V, the electric field E at that time becomes lOMVZcm, and the tunnel current IT starts flowing in the gate oxide film GOX having a thickness of about lOnm. , The charge moves. At this time, a tunnel current IT is generated so that the surface potential is constant, and as a result, the surface potential is kept constant. The tunnel current IT at this time is also observed as the substrate current IK. The current at this time is expressed by the following equation. I = AE 2 exp (-B / E)
[0060] 図 7Dは、電子ビーム EBの走査位置が測定対象のコンタクトホールから外れ、測定 対象に対する電子ビーム EBの照射が終了した時の電荷移動の様子を示している。 この状態では、電子ビーム EBによる電子の供給がなくなる結果、ゲート Gとゲート酸 化膜 GOXとシリコン基板 Sに挟まれた領域に蓄積した電荷が放電する。この放電過 程では、上述の図 7Cに示す電荷の蓄積過程とは逆方向にトンネル電流 ITが流れる 。このときの電流は次式により表現される。  FIG. 7D shows the state of charge transfer when the scanning position of the electron beam EB deviates from the contact hole to be measured and the irradiation of the electron beam EB to the measurement object is completed. In this state, the supply of electrons by the electron beam EB is lost, and as a result, charges accumulated in the region sandwiched between the gate G, the gate oxide film GOX, and the silicon substrate S are discharged. During this discharge process, a tunnel current IT flows in the opposite direction to the charge accumulation process shown in FIG. 7C. The current at this time is expressed by the following equation.
1=1 exp(-A/t)  1 = 1 exp (-A / t)
0  0
[0061] 以上力も理解されるように、ゲート酸ィ匕膜 GOXなどの絶縁膜がホール底のゲート電 極の下に存在する場合、複雑な電流波形が観測されるが、その電流波形力 ホール の構造を解釈することが可能となる。即ち、ゲート Gの下に絶縁体がある場合、ゲート Gと絶縁体とシリコン基板 Sは微分回路を形成するので、観測された波形を微分波形 と見なして、この波形力もホール構造を把握することが可能になる。  [0061] As can be seen from the above, when an insulating film such as a gate oxide film GOX exists under the gate electrode at the bottom of the hole, a complex current waveform is observed. It is possible to interpret the structure of That is, when there is an insulator under the gate G, the gate G, the insulator, and the silicon substrate S form a differential circuit, so that the observed waveform is regarded as a differential waveform, and this waveform force can also grasp the hole structure. Is possible.
[0062] 例えば、図 8に示した基板電流の波形には 2つのピーク P1とピーク P2が存在し、前 述の図 5Bに示す微分回路による微分波形に相当する。そこで、このピーク P1とピー ク P2は、ホール底にゲートなどの絶縁物が存在しない場合に観測される波形を微分 したことにより得られたものと考えれば、各ピークはホールのエッジに対応するものと 解釈することができ、これらピーク P1とピーク P2との間隔から、ホールの評価値として ホール径 CDを算出することができる。  For example, the waveform of the substrate current shown in FIG. 8 has two peaks P1 and P2, which correspond to the differential waveform obtained by the differentiation circuit shown in FIG. 5B described above. Therefore, if we consider that this peak P1 and peak P2 are obtained by differentiating the waveform observed when there is no insulator such as a gate at the bottom of the hole, each peak corresponds to the edge of the hole. The hole diameter CD can be calculated as the hole evaluation value from the interval between these peaks P1 and P2.
[0063] また、電子ビーム EBを単一のホールに対して 2次元走査したときに得られる複数の 基板電流波形から複数のエッジが得られる。この複数のエッジに対して、円近似、楕 円近似あるいは他の形状に対応する近似関数を適用することにより、測定した基板 電流波形からホール底の形状を評価することができる。この場合において、ホールの 絶対的な大きさを求めるには、予め大きさが分力つているホールに対し同様の測定を 予め実施しておくことにより、測定値を較正すればよい。 [0063] In addition, a plurality of edges are obtained from a plurality of substrate current waveforms obtained when the electron beam EB is scanned two-dimensionally with respect to a single hole. For these multiple edges, circular approximation, elliptical By applying an approximate function corresponding to a circular approximation or other shapes, the shape of the bottom of the hole can be evaluated from the measured substrate current waveform. In this case, in order to obtain the absolute size of the hole, it is only necessary to calibrate the measured value by performing the same measurement in advance for the hole whose size is divided in advance.
[0064] また、一般に、ゲート酸ィ匕膜は前述のような完全な容量としては機能しない。即ち、 一定以上の電荷がゲート電極に蓄積して、その表面電位が上昇した状態になると、 ゲート酸ィ匕膜をトンネル電流が流れるので、純粋な容量とは異なった微分波形が観 測される。従って、より正確にホールのエッジを求める方法としては、観測された波形 を構成する成分の内、ゲート酸化膜が純粋なコンデンサ一として機能している領域の 波形を抽出し、その波形力 微分量を得ることにより正確なホールのエッジを抽出で きる。または、逆に電子ビームの照射量を可能な限り小さく調整することにより、ゲート 電極とゲート絶縁膜とシリコン基板とからなる構造が純粋なコンデンサ一として機能す る状態で測定するなどの方法がある。  [0064] In general, the gate oxide film does not function as a complete capacitance as described above. That is, when a certain amount of charge accumulates in the gate electrode and the surface potential rises, a tunneling current flows through the gate oxide film, so a differential waveform different from a pure capacitance is observed. . Therefore, a more accurate method for determining the edge of the hole is to extract the waveform of the region where the gate oxide film functions as a pure capacitor from the components that make up the observed waveform, and then calculate the waveform force derivative. Therefore, the exact hole edge can be extracted. Or, conversely, by adjusting the electron beam dose as small as possible, there is a method of measuring in a state where the structure composed of the gate electrode, the gate insulating film, and the silicon substrate functions as a pure capacitor. .
[0065] なお、通常のホールを測定対象とした場合、基板電流波形として台形状の波形が 得られる力 その波形力もホールのエッジを抽出するための 1つの方法として微分が 行われる。その微分値が最大値を示す場所が、ホールのエッジとして抽出される。 以上のようにして得られた複数のエッジに対して円近似あるいは楕円近似あるいは 他の近似曲線を当てはめて、ホールの形状を評価する。  [0065] When a normal hole is a measurement target, a force that produces a trapezoidal waveform as the substrate current waveform. The waveform force is differentiated as one method for extracting the edge of the hole. The place where the differential value shows the maximum value is extracted as the edge of the hole. The shape of the hole is evaluated by applying a circle approximation, an ellipse approximation or another approximate curve to the multiple edges obtained as described above.
[0066] [第 2実施形態]  [0066] [Second Embodiment]
図 9に、本発明の第 2実施形態に係る半導体測定装置の動作の流れを示す。 本実施形態の装置構成は、基本的には上述の第 1実施形態と同様であるが、エツ ジ抽出アルゴリズムの原理が異なっている。即ち、本実施形態のエッジ抽出アルゴリ ズムは、基板電流の波形を微分波形と見なしたときの該基板電流の積分波形に基づ き微細構造の評価値を得ることを本質としており、そのような評価手段は、例えばエツ ジ抽出装置 150として構成される。  FIG. 9 shows an operation flow of the semiconductor measuring apparatus according to the second embodiment of the present invention. The apparatus configuration of this embodiment is basically the same as that of the first embodiment described above, but the principle of the edge extraction algorithm is different. That is, the edge extraction algorithm of the present embodiment is based on obtaining an evaluation value of the fine structure based on the integrated waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform. Such an evaluation means is configured as an edge extraction device 150, for example.
[0067] 図 9に示す本実施形態の動作フローは、上述の図 2に示す第 1実施形態の動作フ ローのステップ S12に代えて、波形積分処理に関するステップ S22と、フィルタリング に関するステップ S23と、エッジ検出に関するステップ S24とを備える。なお、図 9に おいて、上述の図 2に示すステップと共通するステップには同一符号を付す。 [0067] The operation flow of the present embodiment shown in FIG. 9 includes step S22 related to waveform integration processing, step S23 related to filtering, instead of step S12 of the operation flow of the first embodiment shown in FIG. Step S24 related to edge detection. Figure 9 shows Steps common to the steps shown in FIG. 2 are given the same reference numerals.
[0068] 本実施形態では、ステップ S 11で得られた波形は微分波形なので、一度積分して 元の波形に戻す (ステップ S22)。その後、必要に応じてホール底に対応する成分を 抽出するフィルターを用いて、積分波形の中から必要な成分を抽出する (ステップ S2 3)。例えば、微分波形にはノイズやホールの大きさを推定するためには不要な高周 波成分あるいは低周波数成分が含まれているので、これらを適宜取り除き、ホール底 を正しく反映する波形を得る。 In this embodiment, since the waveform obtained in step S 11 is a differential waveform, it is integrated once and returned to the original waveform (step S 22). After that, necessary components are extracted from the integrated waveform using a filter that extracts components corresponding to the bottom of the hole as required (step S23). For example, the differential waveform contains high-frequency components or low-frequency components that are unnecessary for estimating the size of noise and holes, so these are removed as appropriate to obtain a waveform that correctly reflects the bottom of the hole.
[0069] このように積分して得られた電流波形は、前述の図 3Aに示すような通常のコンタク トホール HAを測定した場合の波形と同じになるので、従来力も知られているエッジ 抽出アルゴリズムを適用してエッジを抽出する(ステップ S24)。このエッジ抽出アルゴ リズムとしては、敷居値法、微分法、ソーベル法、ラプラシアン法など通常数学で知ら れた全てのアルゴリズムを利用する事が出来る。以下は第 1実施形態と同様である( ステップ S 13, S14)。 [0069] The current waveform obtained by integrating in this way is the same as the waveform obtained by measuring the normal contact hole HA as shown in FIG. To extract edges (step S24). As this edge extraction algorithm, all algorithms commonly known in mathematics such as threshold value method, differentiation method, Sobel method, Laplacian method can be used. The following is the same as in the first embodiment (steps S13 and S14).
[0070] [第 3実施形態] [0070] [Third Embodiment]
図 10に、本発明の第 3実施形態に係る半導体測定装置の動作の流れを示す。な お、図 10において、上述の図 9に示すステップと共通するステップには同一符号を 付す。  FIG. 10 shows an operation flow of the semiconductor measuring apparatus according to the third embodiment of the present invention. In FIG. 10, steps that are the same as those shown in FIG. 9 are given the same reference numerals.
本実施形態の装置構成は、基本的には上述の第 1または第 2実施形態と同様であ る力 その動作においては、逆演算に関するステップ S32を備え、ステップ S11で得 られた基板電流の波形に基づき微細構造の等価回路を特定し、この等価回路を用 V、て得られる波形に基づき微細構造の評価値を得ることを本質としており、そのような 評価手段は、例えばエッジ抽出装置 150として構成される。  The apparatus configuration of the present embodiment is basically the same as that of the first or second embodiment described above. In the operation, the apparatus includes step S32 relating to inverse calculation, and the waveform of the substrate current obtained in step S11. Based on the above, it is essential to identify an equivalent circuit of a fine structure and obtain an evaluation value of the fine structure based on the waveform obtained by using this equivalent circuit. Composed.
[0071] 詳細に説明すると、先ず、事前に、ゲート構造やコントロールゲート構造等を含む測 定対象のホール構造を細部にわたって表現した等価回路 (パラメータの値は未設定 )を準備しておく。例えばゲート電極によって形成されるコンデンサーの特異的な成 分も等価回路に組み入れておく。  To describe in detail, first, an equivalent circuit (parameter values are not set) is prepared in advance, which represents in detail the hole structure to be measured including the gate structure and the control gate structure. For example, a specific component of the capacitor formed by the gate electrode is also incorporated in the equivalent circuit.
[0072] ここで、図 11の等価回路は、図 3Bのホール構造の等価回路にゼナーダイオード (z ener diode)ZDを組み込む事により、ゲート電極によって形成される図 12に示すよう なコンデンサーの特異的成分である非線形性を表現したものである。なお、図 11に おいて、 R2はゲートの抵抗成分である。ゼナーダイオード ZDは定電圧ダイオードと も呼ばれ、ダイオードの両端の電圧が一定の電圧になるとダイオードに電流が流れ、 ダイオードの両端の電圧を一定に保つ性質がある。このような精密な等価回路を用 いる事によって、測定対象をより正確に数式で表現することができる。この等価回路 を表現する式を解くことによって、測定された基板電流波形を、通常のコンタクトホー ルが示す基板電流波形に変換する事が出来る。 Here, the equivalent circuit of FIG. 11 is as shown in FIG. 12 formed by a gate electrode by incorporating a zener diode ZD into the equivalent circuit of the Hall structure of FIG. 3B. It expresses the nonlinearity that is a specific component of a simple capacitor. In FIG. 11, R2 is the resistance component of the gate. The Zener diode ZD is also called a constant voltage diode. When the voltage across the diode reaches a constant voltage, current flows through the diode and keeps the voltage across the diode constant. By using such a precise equivalent circuit, the measurement object can be expressed more accurately by a mathematical expression. By solving the equation expressing this equivalent circuit, the measured substrate current waveform can be converted into the substrate current waveform indicated by a normal contact hole.
[0073] 上述の等価回路を利用して元の波形を模擬した波形を得る (ステップ S32)。具体 的には、事前に準備された等価回路を用いて得られる波形が、ステップ S11におい て実際に観測された波形と一致するように、等価回路の各パラメータを逆演算するこ とにより、この各パラメータを特定する。続いて、パラメータが特定された等価回路を 用いて得られる波形に対しフィルタリング処理を施し (ステップ S23)、そしてエッジ抽 出方法を適用することにより、エッジを抽出してホールの評価値を得る (ステップ S12 〜S14)。 [0073] A waveform simulating the original waveform is obtained using the above-described equivalent circuit (step S32). Specifically, this parameter is obtained by inversely calculating each parameter of the equivalent circuit so that the waveform obtained using the equivalent circuit prepared in advance matches the waveform actually observed in step S11. Identify each parameter. Next, filtering is performed on the waveform obtained using the equivalent circuit with the specified parameters (step S23), and the edge extraction method is applied to extract the edge and obtain the evaluation value of the hole ( Steps S12 to S14).
[0074] なお、上述の説明では、図 3Bに示すホール構造を例としたので、その等価回路に より得られる波形は微分波形となる力 一般に等価回路の内容はホール構造に応じ て変わり、その等価回路により得られる波形も変わる。そこで、本実施形態のステップ S12では、等価回路を用いて得られる波形に対して適切なエッジ抽出アルゴリズムを 適用してエッジ検出を行う。即ち、等価回路を用いて得られる波形が微分波形であ れば、上述の第 1実施形態と同様のエッジ抽出アルゴリズムを適用し、台形波形であ れば、第 2実施形態と同様の従来力 知られているエッジ抽出アルゴリズムを適用す ればよい。  [0074] In the above description, since the hole structure shown in Fig. 3B is taken as an example, the waveform obtained by the equivalent circuit is a force that becomes a differential waveform. Generally, the content of the equivalent circuit varies depending on the hole structure. The waveform obtained by the equivalent circuit also changes. Therefore, in step S12 of this embodiment, edge detection is performed by applying an appropriate edge extraction algorithm to the waveform obtained using the equivalent circuit. That is, if the waveform obtained using the equivalent circuit is a differential waveform, the same edge extraction algorithm as in the first embodiment is applied, and if it is a trapezoidal waveform, the same conventional power as in the second embodiment is applied. A known edge extraction algorithm may be applied.
[0075] 以上、本発明の実施形態を説明したが、本発明の実施形態は、本発明の要旨を逸 脱しない範囲で変形が可能である。例えば、上述の実施形態では、ホール底にゲー トが存在する場合を例として説明した力 ホール底に存在する部材はどのような部材 であってもよい。また、その部材は、ホール底の全面に存在する必要はなぐホール 底の一部に存在して 、てもよ 、。  [0075] While the embodiments of the present invention have been described above, the embodiments of the present invention can be modified without departing from the spirit of the present invention. For example, in the above-described embodiment, the force described in the case where a gate is present at the bottom of the hole as an example may be any member that is present at the bottom of the hole. Moreover, the member does not need to be present on the entire bottom surface of the hole, but may be present on a part of the bottom of the hole.
[0076] また、上述の実施形態では、本発明を半導体測定装置および半導体測定方法とし て表現したが、これに限定されず、半導体検査装置、半導体検査方法、半導体分析 装置、半導体分析方法、半導体解析装置、半導体解析方法、半導体評価装置、半 導体評価方法、半導体製造装置、半導体製造方法等として表現してもよい。 In the above-described embodiment, the present invention is a semiconductor measuring device and a semiconductor measuring method. However, the present invention is not limited to this. Semiconductor inspection equipment, semiconductor inspection methods, semiconductor analysis equipment, semiconductor analysis methods, semiconductor analysis equipment, semiconductor analysis methods, semiconductor evaluation equipment, semiconductor evaluation equipment, semiconductor manufacturing equipment, semiconductor manufacturing equipment It may be expressed as a method or the like.
産業上の利用可能性 Industrial applicability
本発明は、半導体デバイス又はその製造工程での検査、分析、製造、測定又は評 価などに用いられる装置、並びに半導体デバイス製造方法に有用である。例えば、 ウェハーなどの半導体基板に電子ビー又はイオンビームを照射する手法を用いる検 查技術、分析技術、測定技術、評価技術、および半導体デバイス製造装置および方 法の分野において、本発明を利用することができる。  INDUSTRIAL APPLICABILITY The present invention is useful for a semiconductor device or an apparatus used for inspection, analysis, manufacturing, measurement or evaluation in a manufacturing process thereof, and a semiconductor device manufacturing method. For example, the present invention is used in the fields of inspection techniques, analysis techniques, measurement techniques, evaluation techniques, and semiconductor device manufacturing apparatuses and methods that use a method of irradiating a semiconductor substrate such as a wafer with an electron beam or ion beam. Can do.

Claims

請求の範囲 The scope of the claims
[1] 半導体基板に電子ビームを照射し、該電子ビームによって前記半導体基板に誘起 された基板電流から前記半導体基板に形成された微細構造の評価値を得るように構 成された半導体測定装置であって、  [1] A semiconductor measuring apparatus configured to irradiate a semiconductor substrate with an electron beam and obtain an evaluation value of a microstructure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. There,
前記基板電流の波形を微分波形と見なしたときの該基板電流の波形に基づき前記 微細構造の評価値を得る評価手段を備えたことを特徴とする半導体測定装置。  A semiconductor measuring apparatus comprising: an evaluation unit that obtains an evaluation value of the microstructure based on a waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.
[2] 前記微細構造はホールであり、  [2] The microstructure is a hole,
前記評価手段は、前記基板電流の波形から前記ホールのエッジを抽出することを 特徴とする請求項 1記載の半導体測定装置。  The semiconductor measuring apparatus according to claim 1, wherein the evaluation unit extracts an edge of the hole from a waveform of the substrate current.
[3] 前記評価手段は、前記ホールのエッジ力 該ホールの評価値を算出することを特 徴とする請求項 2記載の半導体測定装置。 3. The semiconductor measuring apparatus according to claim 2, wherein the evaluation means calculates an edge force of the hole and an evaluation value of the hole.
[4] 前記評価手段は、前記基板電流の波形のピーク力 前記ホールのエッジを抽出す ることを特徴とする請求項 2または 3の何れか 1項記載の半導体測定装置。 4. The semiconductor measurement apparatus according to claim 2, wherein the evaluation unit extracts a peak force of the waveform of the substrate current and an edge of the hole.
[5] 半導体基板に電子ビームを照射し、該電子ビームによって前記半導体基板に誘起 された基板電流から前記半導体基板に形成された微細構造の評価値を得るように構 成された半導体測定装置であって、 [5] A semiconductor measuring apparatus configured to irradiate a semiconductor substrate with an electron beam and obtain an evaluation value of a fine structure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. There,
前記基板電流の波形を微分波形と見なしたときの該基板電流の積分波形に基づき 前記微細構造の評価値を得る評価手段を備えたことを特徴とする半導体測定装置。  A semiconductor measuring apparatus comprising: an evaluation unit that obtains an evaluation value of the microstructure based on an integrated waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.
[6] 前記微細構造はホールであり、 [6] The microstructure is a hole,
前記評価手段は、前記積分波形力 前記ホールのエッジを抽出することを特徴と する請求項 5記載の半導体測定装置。  6. The semiconductor measurement apparatus according to claim 5, wherein the evaluation unit extracts an edge of the integrated waveform force of the hole.
[7] 前記評価手段は、前記ホールのエッジ力 該ホールの評価値を算出することを特 徴とする請求項 6記載の半導体測定装置。 7. The semiconductor measuring apparatus according to claim 6, wherein the evaluation means calculates an edge force of the hole and an evaluation value of the hole.
[8] 半導体基板に電子ビームを照射し、該電子ビームによって前記半導体基板に誘起 された基板電流から前記半導体基板に形成された微細構造の評価値を得るように構 成された半導体測定装置であって、 [8] A semiconductor measuring apparatus configured to irradiate a semiconductor substrate with an electron beam and obtain an evaluation value of a fine structure formed on the semiconductor substrate from a substrate current induced in the semiconductor substrate by the electron beam. There,
前記基板電流の波形に基づき前記微細構造の等価回路を特定し、該等価回路を 用いて得られる波形に基づき前記微細構造の評価値を得る評価手段を備えたことを 特徴とする半導体測定装置。 Evaluating means for identifying an equivalent circuit of the microstructure based on the waveform of the substrate current and obtaining an evaluation value of the microstructure based on a waveform obtained using the equivalent circuit A semiconductor measuring device.
[9] 前記微細構造はホールであり、  [9] The microstructure is a hole,
前記評価手段は、前記等価回路を用いて得られる波形力 前記ホールのエッジを 抽出することを特徴とする請求項 8記載の半導体測定装置。  9. The semiconductor measurement apparatus according to claim 8, wherein the evaluation means extracts a waveform force obtained by using the equivalent circuit.
[10] 前記評価手段は、前記ホールのエッジ力 該ホールの評価値を算出することを特 徴とする請求項 9記載の半導体測定装置。 10. The semiconductor measuring apparatus according to claim 9, wherein the evaluation means calculates an edge force of the hole and an evaluation value of the hole.
[11] 半導体基板に電子ビームを照射し、該電子ビームによって前記半導体基板に誘起 された基板電流から前記半導体基板に形成された微細構造の評価値を得る半導体 測定方法であって、 [11] A semiconductor measurement method for obtaining an evaluation value of a fine structure formed in a semiconductor substrate from a substrate current induced in the semiconductor substrate by irradiating an electron beam to the semiconductor substrate,
前記基板電流の波形を微分波形と見なしたときの該基板電流の波形に基づき前記 微細構造の評価値を得ることを特徴とする半導体測定方法。  An evaluation value of the microstructure is obtained based on a waveform of the substrate current when the waveform of the substrate current is regarded as a differential waveform.
PCT/JP2006/301545 2006-01-31 2006-01-31 Semiconductor measuring apparatus and semiconductor measuring method WO2007088587A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2006800509087A CN101356635B (en) 2006-01-31 2006-01-31 Apparatus and method for measuring semiconductor
KR1020087016766A KR101085413B1 (en) 2006-01-31 2006-01-31 Semiconductor measuring apparatus and semiconductor measuring method
PCT/JP2006/301545 WO2007088587A1 (en) 2006-01-31 2006-01-31 Semiconductor measuring apparatus and semiconductor measuring method
JP2007556727A JP5005551B2 (en) 2006-01-31 2006-01-31 Semiconductor measuring apparatus and semiconductor measuring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/301545 WO2007088587A1 (en) 2006-01-31 2006-01-31 Semiconductor measuring apparatus and semiconductor measuring method

Publications (1)

Publication Number Publication Date
WO2007088587A1 true WO2007088587A1 (en) 2007-08-09

Family

ID=38327174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/301545 WO2007088587A1 (en) 2006-01-31 2006-01-31 Semiconductor measuring apparatus and semiconductor measuring method

Country Status (4)

Country Link
JP (1) JP5005551B2 (en)
KR (1) KR101085413B1 (en)
CN (1) CN101356635B (en)
WO (1) WO2007088587A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449385B (en) * 2016-11-30 2019-05-31 上海华力微电子有限公司 The method for eliminating defect caused by electronics beam scanning

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315271A (en) * 1991-01-08 1993-11-26 Nec Corp Method and apparatus for diffusing impurity
JPH08236587A (en) * 1995-02-28 1996-09-13 Kaijo Corp Defective bonding detecting method and device in wire bonding device
JP2004036639A (en) * 2002-06-28 2004-02-05 Tsubakimoto Sprocket Co Sprocket with abrasion limit indication
JP2004064006A (en) * 2002-07-31 2004-02-26 Fab Solution Kk Nondestructive measurement equipment and manufacturing method for semiconductor device
JP2004071622A (en) * 2002-08-01 2004-03-04 Fab Solution Kk Method and system for managing semiconductor device manufacturing process
JP2004145466A (en) * 2002-10-22 2004-05-20 Lasertec Corp Displacement detecting method and device, as well as image processing method and image processor, and inspecting device using same
JP2005077192A (en) * 2003-08-29 2005-03-24 Hitachi Ltd Three-dimensional shape measuring device, etching condition determination method, and etching process monitoring method
JP2005156436A (en) * 2003-11-27 2005-06-16 Hitachi Ltd Semiconductor pattern measuring method and process control method
JP2005189137A (en) * 2003-12-26 2005-07-14 Hitachi High-Technologies Corp Pattern measuring method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064406A (en) * 2002-07-29 2004-02-26 Canon Inc Image reading device and its control program
JP4080902B2 (en) 2003-01-30 2008-04-23 株式会社トプコン Semiconductor device analysis apparatus and analysis method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315271A (en) * 1991-01-08 1993-11-26 Nec Corp Method and apparatus for diffusing impurity
JPH08236587A (en) * 1995-02-28 1996-09-13 Kaijo Corp Defective bonding detecting method and device in wire bonding device
JP2004036639A (en) * 2002-06-28 2004-02-05 Tsubakimoto Sprocket Co Sprocket with abrasion limit indication
JP2004064006A (en) * 2002-07-31 2004-02-26 Fab Solution Kk Nondestructive measurement equipment and manufacturing method for semiconductor device
JP2004071622A (en) * 2002-08-01 2004-03-04 Fab Solution Kk Method and system for managing semiconductor device manufacturing process
JP2004145466A (en) * 2002-10-22 2004-05-20 Lasertec Corp Displacement detecting method and device, as well as image processing method and image processor, and inspecting device using same
JP2005077192A (en) * 2003-08-29 2005-03-24 Hitachi Ltd Three-dimensional shape measuring device, etching condition determination method, and etching process monitoring method
JP2005156436A (en) * 2003-11-27 2005-06-16 Hitachi Ltd Semiconductor pattern measuring method and process control method
JP2005189137A (en) * 2003-12-26 2005-07-14 Hitachi High-Technologies Corp Pattern measuring method

Also Published As

Publication number Publication date
JPWO2007088587A1 (en) 2009-06-25
KR101085413B1 (en) 2011-11-21
JP5005551B2 (en) 2012-08-22
CN101356635A (en) 2009-01-28
CN101356635B (en) 2010-10-13
KR20080079672A (en) 2008-09-01

Similar Documents

Publication Publication Date Title
US7375330B2 (en) Charged particle beam equipment
TWI751435B (en) Systems and methods of optimal metrology guidance
US7652249B2 (en) Charged particle beam apparatus
US8275564B2 (en) Patterned wafer inspection system using a non-vibrating contact potential difference sensor
KR100526669B1 (en) A film thickness measuring apparatus and a method for measuring a thickness of a film
TW202217904A (en) Sensing element level circuitry design for electron counting detection device
JP3292159B2 (en) Film thickness measuring device and film thickness measuring method
US20070235646A1 (en) Scanning electron microscope
JP5005551B2 (en) Semiconductor measuring apparatus and semiconductor measuring method
JP4754623B2 (en) Semiconductor device manufacturing method
JP2010103320A (en) Semiconductor inspection apparatus
JP4060143B2 (en) Nondestructive measuring apparatus and semiconductor device manufacturing method
JP4906409B2 (en) Electron beam size measuring apparatus and electron beam size measuring method
JP4080902B2 (en) Semiconductor device analysis apparatus and analysis method
JP2010232434A (en) Level difference measuring method, level difference measuring device, and scanning electron microscope device
WO2008053518A1 (en) Semiconductor inspection equipment and semiconductor inspection method
TWI803837B (en) Charged-particle beam inspection systems and related non-transitory computer readable medium
US20230314128A1 (en) Processing System and Charged Particle Beam Apparatus
JP4638896B2 (en) Defect inspection apparatus and defect inspection method for magnetic recording medium
WO2007072557A1 (en) Semiconductor tester and method of testing semiconductor
JP2004286580A (en) Sample observation apparatus, edge position calculation device, and program
JP2010123934A (en) Methods of processing and displaying data of semiconductor test device, and the semiconductor test device
JP2009272264A (en) Scanning electron microscope

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007556727

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: KR

WWE Wipo information: entry into national phase

Ref document number: 200680050908.7

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06712688

Country of ref document: EP

Kind code of ref document: A1