JP2011119457A - Alignment condition optimization method and system, pattern forming method and system, exposure device, device manufacturing method, overlay accuracy evaluation method and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain the high overlay accuracy of a pattern. <P>SOLUTION: In EGA optimization simulation, an alignment processing parameter is optimized through the use of the result of EGA simulation using the measurement result of the first wafer alignment (EGA measurement) and the result of EGA simulation using the measurement result of the second wafer alignment (EGA measurement) (steps S38, S39, S42, S43). Thus, even when a pattern is formed on a wafer by using a double patterning method, it is possible to achieve the high overlay accuracy of the pattern. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an alignment condition optimization method and system, a pattern formation method and system, an exposure apparatus, a device manufacturing method, and an overlay accuracy evaluation method and system, and more particularly, a pattern formed on a reference layer on an object. And a target layer formed by a double process method (double patterning method) in which a mask layer is formed through a plurality of lithography processes including exposure and development over the reference layer, for example, through two lithography processes. Alignment condition optimization method and system for optimizing alignment condition, pattern formation method and system using alignment condition optimized by the alignment condition optimization method, and exposure apparatus provided with the alignment condition optimization system Manufactured by a device using the pattern forming method or pattern forming system Method, and a suitable overlay accuracy evaluation method and system to assess the overlay accuracy between patterns in the corresponding reference layer the pattern of the target layer formed by the double process method (double patterning method).

  Electronic devices (microdevices) such as semiconductor elements and liquid crystal display elements are manufactured by hierarchically stacking device patterns (patterns) on a substrate using an exposure apparatus or the like. Conventionally, in order to appropriately manage overlay accuracy, for example, as disclosed in Patent Document 1, prior exposure to a test wafer prior to an actual process, measurement of overlay error and line width error of the exposure result, Adjustment of alignment related parameters, exposure amount, synchronization accuracy, and focus control related control system parameters in the exposure apparatus based on the measurement result is performed.

  On the other hand, in response to the miniaturization of patterns of semiconductor elements and the like, the exposure apparatus used in the lithography process shortens the exposure wavelength, increases the numerical aperture NA of the projection optical system in order to increase the resolving power, so-called Optimization of illumination conditions such as modified illumination and development of mask technologies such as phase shift reticles have been performed. Recently, in order to substantially increase the numerical aperture NA while ensuring a wide focal depth, an exposure apparatus using an immersion method has been developed. However, shortening the exposure wavelength and increasing the numerical aperture NA increase the manufacturing cost of the exposure apparatus, and consequently increase the manufacturing cost of the device.

  Therefore, recently, a so-called double process method (double patterning method) has been proposed in which a fine circuit pattern exceeding the resolution limit of the exposure apparatus is formed by repeating the lithography process twice. However, in the conventional overlay accuracy management method, when the double patterning method is adopted, the overlay accuracy cannot be appropriately managed.

US Patent Application Publication No. 2008/0294280

According to a first aspect of the present invention, a pattern formed on the target layer after a plurality of lithography steps including exposure and development on the target layer on the object, and formed on the object prior to the target layer. A positioning condition optimization method for optimizing a positioning condition with a ground pattern formed on a reference layer serving as a reference for overlaying the pattern,
When the first pattern is formed on the target layer so as to overlap the base pattern formed on the reference layer on the object, the reference layer detected for alignment of the first pattern with respect to the base pattern A first detection result of at least some of the first marks formed with the base pattern and a second pattern on the target layer on which the first pattern is formed on the object. When forming, using a second detection result of at least some of the plurality of first marks detected for alignment of the second pattern with respect to the base pattern, and A first alignment including a step of optimizing an alignment condition of a pattern formed on the target layer with respect to a base pattern formed on the reference layer on the object; It is not a condition optimization method.

  According to this, the alignment condition is optimized using the first and second detection results of the first mark. Therefore, by following this optimized alignment condition, even when the pattern is formed on the object using the double patterning method, the overlay accuracy of the pattern of the target layer with respect to the base pattern and the first pattern and the first pattern are increased. It is possible to achieve high alignment accuracy with the two patterns.

  According to a second aspect of the present invention, a pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object, and formed on the object prior to the target layer. An alignment condition optimization method for optimizing an alignment condition with a ground pattern formed on a reference layer serving as a reference for superimposing the formed patterns, wherein the alignment condition is optimized on the object together with the ground pattern. A first mark, a second mark formed on the target layer with the first pattern on the first layer, and a second mark formed on the first and second marks on the target layer. Using the detection result obtained by detecting the third mark formed together with the second pattern formed at the time of the exposure, the shape is formed on the reference layer on the object. A second alignment condition optimizing method comprising the step of optimizing the alignment condition of a pattern to be formed on the target layer for the underlying patterns.

  According to this, the alignment condition of the pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object is optimal using the detection result obtained by detecting the first to third marks. It becomes. Therefore, according to this optimized alignment condition, even when a pattern is formed on an object using the double patterning method, it is possible to realize a high overlay accuracy of the pattern.

  According to a third aspect of the present invention, there is provided a pattern formation in which a pattern is formed by superimposing a pattern on a target layer through a plurality of lithography steps including exposure and development on a target layer, overlaid on a base pattern already formed on an object. A first and second pattern formed on the target layer by a first exposure and a second exposure on the target layer on the object; and on the object prior to the target layer. A step of optimizing the alignment condition with the base pattern formed on the reference layer, which is a reference for pattern superposition, using the first or second alignment condition optimization method of the present invention; A first exposure and a second exposure on the target layer on the object by aligning the first and second patterns with respect to the base pattern formed on the object. To form the first and second patterns on the target layer, and at least one of the first exposure and the second exposure on the target layer on the object, the optimized alignment condition is satisfied. And performing the alignment step.

  According to this, it is possible to realize high overlay accuracy of the pattern of the target layer with respect to the base pattern.

  According to a fourth aspect of the present invention, there is provided a step of forming a mask layer by exposing the first pattern and the second pattern to a target layer on an object by the pattern forming method of the present invention; And using the target layer to process the device.

According to a fifth aspect of the present invention, there is provided a ground pattern formed on a reference layer serving as a reference for pattern superimposition prior to the target layer on the object, and exposure to the target layer superimposed on the ground pattern. An overlay accuracy evaluation method for evaluating overlay accuracy with a pattern formed through a plurality of lithography steps including development,
When the first pattern is formed over the base pattern formed on the reference layer on the object, the base layer is detected together with the base pattern detected for alignment of the first pattern with respect to the base pattern. When forming the second pattern on the target layer where the first pattern on the object and the first detection result of at least some of the formed first marks and the first pattern on the object are formed. And the second detection result of the at least some of the first marks detected for alignment of the second pattern with respect to the base pattern, and the first pattern and the second with respect to the base pattern This is an overlay accuracy evaluation method for evaluating overlay accuracy with a pattern.

  According to this, it is possible to accurately evaluate the overlay accuracy of the first pattern and the second pattern with respect to the base pattern and the alignment accuracy of the first pattern and the second pattern.

  According to a sixth aspect of the present invention, a pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object, and formed on the object prior to the target layer. An alignment condition optimization system for optimizing alignment conditions with an underlying pattern formed on a reference layer serving as a reference for superimposing the patterns, the underlying pattern formed on the reference layer on the object A plurality of first marks formed together with the base pattern on the reference layer detected for alignment of the first pattern with respect to the base pattern. The first detection result of at least a part of the first marks and the target on which the first pattern on the object is formed A second detection result of at least some of the plurality of first marks detected for alignment of the second pattern with respect to the base pattern when forming the second pattern on And a first alignment condition optimization system comprising an optimization device that optimizes the alignment condition of the pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object. is there.

  According to this, the alignment condition is optimized using the first and second detection results of the first mark. Therefore, by following this optimized alignment condition, even when the pattern is formed on the object using the double patterning method, the overlay accuracy of the pattern of the target layer with respect to the base pattern and the first pattern and the first pattern are increased. It is possible to achieve high alignment accuracy with the two patterns.

  According to a seventh aspect of the present invention, a pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object, and formed on the object prior to the target layer. An alignment condition optimization system for optimizing alignment conditions with a base pattern formed on a reference layer serving as a reference for superposition of the formed patterns, wherein the alignment condition optimization system is formed on the object together with the base pattern. A first mark, a second mark formed on the target layer with the first pattern on the first layer, and a second mark formed on the first and second marks on the target layer. A mark detection system for detecting a third mark formed together with the second pattern formed at the time of exposure; and a detection result by the mark detection system And an optimization device for optimizing the alignment condition of the pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object, and a second alignment condition optimization system comprising: .

  According to this, the first mark formed with the base pattern on the object by the mark detection system, and the second mark formed with the first pattern on the target layer for the first exposure on the first mark. And a third mark formed on the target layer together with the second pattern formed in the second exposure on the first and second marks. Then, a pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object, using the detection result obtained by detecting the first to third marks with the mark detection system by the optimization device The alignment conditions are optimized. Therefore, according to this optimized alignment condition, even when a pattern is formed on an object using the double patterning method, it is possible to realize a high overlay accuracy of the pattern.

From an eighth aspect, the present invention is an exposure apparatus for forming a pattern by superimposing a plurality of layers on an object,
First and second patterns formed on the target layer by a first exposure and a second exposure on the target layer on the object, and a pattern formed on the object prior to the target layer The exposure apparatus includes any one of the first and second alignment condition optimization systems of the present invention that optimizes the alignment condition with the base pattern formed on the reference layer serving as a reference for the superposition of the first and second layers.

  According to this, it is possible to realize high overlay accuracy of the pattern of the target layer with respect to the base pattern.

  According to the ninth aspect of the present invention, there is provided a pattern formation in which a pattern is formed by superimposing a pattern on a target layer through a plurality of lithography processes including exposure and development, overlaid on a base pattern already formed on an object. A first and second pattern formed on the target layer by a first exposure and a second exposure on the target layer on the object; and on the object prior to the target layer. Either of the first and second alignment condition optimization systems of the present invention for optimizing the alignment condition with the underlying pattern formed on the reference layer that is formed and used as a reference for pattern superposition; First and second exposures of the target layer on the object are performed by aligning the first and second patterns with respect to the base pattern formed on the object. Performing the light to form the first and second patterns on the target layer, and at least one of the first exposure and the second exposure on the target layer on the object, the optimized alignment condition; And a pattern forming system comprising: an exposure apparatus that performs the alignment.

  According to this, it is possible to realize high overlay accuracy of the pattern of the target layer with respect to the base pattern.

  According to a tenth aspect of the present invention, the pattern formation system of the present invention forms a mask layer on the target layer on the object by exposing the first pattern and the second pattern; and And processing the target layer using a device manufacturing method.

According to an eleventh aspect of the present invention, there is provided a ground pattern formed on a reference layer serving as a reference for pattern superimposition prior to a target layer on an object, and exposure of the target layer superimposed on the ground pattern. An overlay accuracy evaluation system that evaluates overlay accuracy with a pattern formed through a plurality of lithography processes including development,
When the first pattern is formed over the base pattern formed on the reference layer on the object, the base layer is detected together with the base pattern detected for alignment of the first pattern with respect to the base pattern. When forming the second pattern on the target layer where the first pattern on the object and the first detection result of at least some of the formed first marks and the first pattern on the object are formed. And the second detection result of the at least some of the first marks detected for alignment of the second pattern with respect to the base pattern, and the first pattern and the second with respect to the base pattern This is an overlay accuracy evaluation system for evaluating overlay accuracy with a pattern.

  According to this, it is possible to accurately evaluate the overlay accuracy of the first pattern and the second pattern with respect to the base pattern and the alignment accuracy of the first pattern and the second pattern.

It is a figure showing a schematic structure of a device manufacturing system concerning one embodiment of the present invention. It is a figure which shows an example of a schematic structure of the exposure apparatus of FIG. 3A is a diagram showing an example of an arrangement of shot areas on a wafer, FIG. 3B is a diagram showing an example of the type and arrangement of wafer marks, and FIG. 3C is an example of an overlay error measurement mark. FIG. It is a flowchart which shows the flow of a process in a device manufacturing process. FIG. 5A to FIG. 5J are diagrams for explaining the formation process of the pattern formed on the wafer, and are enlarged sectional views showing a part of one shot region on the wafer. It is. It is a flowchart (the 1) corresponding to the EGA optimization simulation performed by an analyzer. It is a flowchart (the 2) corresponding to the EGA optimization simulation performed by an analyzer. It is a flowchart (the 3) corresponding to the EGA optimization simulation performed by an analyzer. It is a flowchart (the 4) corresponding to the EGA optimization simulation performed by an analyzer. It is a flowchart corresponding to the overlay optimization simulation performed by the analysis apparatus.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a schematic configuration of a device manufacturing system according to an embodiment. The device manufacturing system 1000 is a system constructed in a device manufacturing factory for processing a substrate, for example, a semiconductor wafer (hereinafter referred to as “wafer”) and manufacturing a micro device. As shown in FIG. 1, a device manufacturing system 1000 includes an exposure apparatus 100, a track 200 disposed adjacent to the exposure apparatus 100, an analysis apparatus 500, and a host computer (hereinafter abbreviated as “host”). 600) and a device manufacturing processing apparatus group 900. In FIG. 1, the bold arrows indicate the flow (movement) of the wafer, and the other solid arrows indicate the data flow.

  Here, the exposure apparatus 100 is a step-and-scan projection exposure apparatus (that is, a scanner). FIG. 2 shows a schematic configuration of the exposure apparatus 100. The exposure apparatus 100 includes an illumination system IOP, a reticle stage RST that holds a reticle R, a projection optical system PL, a wafer stage WST on which a wafer W is placed, a control system for these, and the like.

  The illumination system IOP includes a light source and an illumination optical system connected to the light source via a light transmission optical system. The illumination optical system includes, for example, an illumination uniformizing optical system including an optical integrator, a beam splitter, a reticle blind, and the like (all not shown) as disclosed in, for example, US Patent Application Publication No. 2003/0025890. . Illumination system IOP uses illumination light IL to illuminate a slit-like illumination area defined by a reticle blind on reticle R on which a circuit pattern or the like is drawn (a long and narrow rectangular shape extending in the X-axis direction (the direction perpendicular to the plane of FIG. 2)). Illuminate with almost uniform illumination. As the illumination light IL, for example, ArF excimer laser light (wavelength 193 nm) (or KrF excimer laser light (wavelength 248 nm)) is used.

  Reticle stage RST is arranged below illumination system IOP in FIG. 2 (on the −Z side). On reticle stage RST, reticle R on which a pattern is formed is fixed, for example, by vacuum suction. Here, reticle stage RST can be finely driven in a horizontal plane (XY plane) by a reticle stage drive system 22 including a linear motor and the like, and also has a scanning direction (here, the Y axis in the horizontal direction in FIG. 2). Driving at a scanning speed specified in a predetermined stroke range. Position information (including rotation information about the Z axis) of the reticle stage RST in the XY plane is, for example, about 0.25 nm by a reticle laser interferometer (hereinafter referred to as “reticle interferometer”) 16 via a movable mirror 15. Is always detected with a resolution of. Position information of reticle stage RST from reticle interferometer 16 is sent to main controller 50, which drives reticle stage RST via reticle stage drive system 22 based on the position information of reticle stage RST. (Control.

  Projection optical system PL is arranged below reticle stage RST in FIG. 2 (on the −Z side), and the direction of optical axis AX is the Z-axis direction. As the projection optical system PL, for example, a bilateral telecentric refraction system including a plurality of lens elements arranged at a predetermined interval along the Z-axis direction parallel to the optical axis AX is used. The projection magnification β of the projection optical system PL is, for example, ¼ (or ５). For this reason, when the reticle R is illuminated by the illumination light IL from the illumination system IOP, the illumination light IL that has passed through the reticle R passes through the projection optical system PL and is within the illumination area (illumination area) of the illumination light IL. A reduced image (partial inverted image) of the reticle R pattern is formed in an area (exposure area) conjugated to the illumination area on the wafer W coated with a photoresist (sensitive agent; hereinafter abbreviated as resist). (A latent image of the pattern is formed on the resist).

  The exposure apparatus 100 is provided with an imaging characteristic correction device for correcting imaging characteristics of the projection optical system PL, for example, various aberrations. This imaging characteristic correction apparatus corrects changes in the imaging characteristics of the projection optical system PL itself due to changes in atmospheric pressure, absorption of illumination light, and the like, and applies to a shot area of a preceding specific layer (for example, the previous layer) on the wafer W. The projection image of the pattern of the reticle R is distorted in accordance with the distortion of the transferred pattern. Imaging characteristics of the projection optical system PL include spherical aberration (aberration at the imaging position), coma aberration (magnification aberration), astigmatism, field curvature, distortion aberration (distortion), and the like. The imaging characteristic correction device has a function of correcting these various aberrations.

  A plurality of lens elements (movable lenses) constituting a part of the projection optical system PL can be arbitrarily tilted with respect to a plane orthogonal to the optical axis AX and moved in a direction parallel to the optical axis AX. ing. Each movable lens is independently controlled by the image characteristic control unit 12.

  Wafer stage WST is arranged below projection optical system PL in FIG. 2 (on the −Z side). On wafer stage WST, wafer W is held by vacuum suction or the like via wafer holder 9.

  Wafer stage WST is driven with a predetermined stroke in the X-axis direction and Y-axis direction by wafer stage drive system 24 including a linear motor and the like, and also rotates in the Z-axis direction and the Z-axis rotation direction (θz direction). It is finely driven in a rotating direction (θx direction) around and a rotating direction around the Y axis (θy direction). That is, the wafer holder 9 can be tilted in any direction with respect to the best imaging plane of the projection optical system PL by the wafer stage drive system 24, and can be finely moved in the optical axis AX direction (Z-axis direction). It is configured to be rotatable around a Z axis parallel to the axis AX.

  Position information (including yawing (rotation in the θz direction) information) and tilt information (pitching (rotation in the θx direction) information and rolling (rotation in the θy direction) information) of the wafer stage WST in the XY plane are the wafer laser. An interferometer (hereinafter abbreviated as a wafer interferometer) 18 is constantly detected through a movable mirror 17 with a resolution of, for example, about 0.25 nm. The position information (or speed information) of wafer stage WST is sent to main controller 50, and main controller 50 determines the position of wafer stage WST in the XY plane (in the θz direction) based on the position information (or speed information). (Including rotation) is controlled via the wafer stage drive system 24.

  Further, a reference mark plate FM having a surface set substantially at the same height as the surface of wafer W is fixed to the upper surface of wafer stage WST. On the surface of the fiducial mark plate FM, a first fiducial mark for reticle alignment and a second fiducial mark for baseline measurement of the alignment system 8 described later are formed in a predetermined positional relationship.

On the side surface of the projection optical system PL, alignment marks (wafer marks) (MX _p , MY _p ) and overlay error measurement marks MO (see FIG. 3B) attached to each shot area on the wafer W, and An off-axis alignment system 8 is provided for detecting a second reference mark on the reference mark plate FM. The alignment system 8 uses an internal optical system to illuminate the wafer surface including the wafer mark (MX _p , MY _p ) or the overlay error measurement mark MO, and reflects the reflected light from the wafer surface to the optical system. Is guided to an alignment sensor provided inside, and a signal corresponding to the reflected light is photoelectrically detected using the alignment sensor. The detected signal has, for example, a waveform corresponding to the unevenness or reflectance distribution of the wafer surface. In the alignment system, a waveform (mark waveform) corresponding to the mark is extracted from the detected waveform data, and the position coordinate of the mark waveform in the detection field of the alignment sensor is detected based on the extraction result. In the alignment system, the position of the wafer mark (MX _p , MY _p ) and the overlay error measurement mark MO in the XY coordinate system based on the position coordinates of the detected mark waveform and the position coordinates of the detection visual field itself of the alignment sensor. Is calculated. The detection result of the alignment system 8 is sent to the main controller 50 via an alignment signal processing system (not shown).

  Further, in the vicinity of the lower end portion of the projection optical system PL, position information (surface position information) regarding the Z-axis direction of the surface of the wafer W at a plurality of detection points in the exposure area and in the vicinity thereof is detected. An oblique incidence type multi-point focal position detection system (13, 14) disclosed in the specification of No. 5,448,332 and the like is provided. The multipoint focal position detection system includes an irradiation optical system 13 that emits an imaged light beam obliquely with respect to the optical axis AX toward the best image formation plane of the projection optical system PL, and a reflected light beam from the surface of the wafer W as a slit. And a light receiving optical system 14 for receiving light through The wafer surface position information detected by the multipoint focus position detection system (13, 14) is supplied to the main controller 50 for focus / leveling control of the wafer W.

  In addition, the exposure apparatus 100 is provided with a pair of reticle alignment systems (not shown) as disclosed in, for example, US Pat. No. 5,646,413 above the reticle stage RST. The reticle alignment system is composed of a TTR (Through The Reticle) alignment system using light having the same wavelength as the illumination light IL. The detection signal of the reticle alignment system is supplied to main controller 50 via an alignment signal processing system (not shown).

  The main controller 50 is composed of, for example, a microcomputer (or workstation), and comprehensively controls each part of the exposure apparatus 100.

  Next, the operation of the exposure process in the exposure apparatus 100 will be briefly described.

  Prior to exposure, main controller 50 causes wafer W to be loaded onto wafer holder 9 using a wafer transfer system (not shown), reticle alignment, baseline measurement of alignment system 8, and wafer alignment (for example, EGA (described later) Preparation work such as Enhanced Global Alignment) or multi-point EGA within shot) is performed. The above reticle alignment, baseline measurement, and the like are disclosed in detail in the aforementioned US Pat. No. 5,646,413.

  Main controller 50 sequentially performs reticle exposure on all shot areas on wafer W based on the results of reticle alignment and baseline measurement, and the results of wafer alignment (which will be described later). The pattern is transferred.

  In scanning exposure for each shot area on wafer W, main controller 50 monitors reticle stage RST and wafer stage WST while monitoring measurement information (position information) by reticle interferometer 16 and wafer interferometer 18. Move to scan start position (acceleration start position). Then, main controller 50 relatively drives both stages RST and WST in the Y-axis direction, but in opposite directions. Here, when both stages RST and WST reach their respective target speeds, the pattern area of reticle R starts to be illuminated by illumination light IL, and scanning exposure is started.

  Main controller 50 determines that the speed Vr of reticle stage RST in the Y-axis direction and the movement speed Vw of wafer stage WST in the Y-axis direction at a speed ratio corresponding to the projection magnification of projection optical system PL, particularly during the above-described scanning exposure. The reticle stage RST and wafer stage WST are synchronously controlled so as to be maintained. At this time, main controller 50 adjusts the synchronous drive of both stages RST and WST, or drives the movable lens via the imaging characteristic correction device, so that the projection image of the pattern on reticle R onto wafer W is displayed. Correct distortion.

  Then, different areas of the pattern area of the reticle R are sequentially illuminated with the illumination light IL, and the illumination of the entire pattern area is completed, thereby completing the scanning exposure of the first shot area on the wafer W. Thereby, the circuit pattern of the reticle R is reduced and transferred to the first shot area via the projection optical system PL.

  When the scanning exposure for the first shot area is completed, main controller 50 moves (steps) wafer stage WST to the scanning start position (acceleration start position) for the next second shot area. Then, similarly to the above, scanning exposure is performed on the second shot area. Thereafter, the same operation is performed for the third shot area and thereafter. In this way, the stepping operation between the shot areas and the scanning exposure operation for the shot areas are repeated, and the pattern of the reticle R is transferred to all the shot areas on the wafer W by the step-and-can method.

Next, the wafer alignment according to the present embodiment will be further described. FIG. 3A shows an example of a wafer W (a substrate used for device manufacture) to be exposed in the exposure apparatus 100. As shown in FIG. 3A, on the wafer W, a plurality of shot areas SA _p in which device patterns are formed are already formed by exposure to the previous layer. In each shot area SA _p , as shown in FIG. 3B, alignment marks (wafer marks) transferred at the time of exposure of a reference layer (also referred to as an underlayer, for example, a front layer) serving as a reference for overlaying are provided. ) (MX _p , MY _p ). The wafer marks (MX _p , MY _p ) are marks whose position information can be detected from their shapes and the like. For example, in FIG. 3B, the wafer marks (MX _p , MY _p ) are shown as line and space marks. In addition to the shape of the wafer mark, a box mark, a cross mark, or the like may be employed.

In exposure apparatus 100, with respect to the shot area SA _p on this the wafer W, a device pattern on the reticle R, it is necessary to expose by accurately superimposed. In order to realize accurate overlay, it is necessary to accurately grasp the position of each shot area SA _p on the wafer W. Wafer marks (MX _p , MY _p ) are provided to grasp the position of each shot area SA _p (for example, the position of its center C _p in FIG. 3B). Since the wafer mark (MX _p , MY _p ) is transferred and formed together with the device pattern of the shot area SA _p to which the wafer mark (MX _p , MY _p ) is attached, the wafer mark (MX _p , MY _p ) on the wafer W and the device pattern If the position of the wafer mark (MX _p , MY _p ) is known, the center position C _p of the shot area can be recognized.

Further, as shown in FIG. 3B, in each shot area SA _p , an overlay error measurement mark MO ₀ is transferred and formed together with the device pattern when the reference layer is exposed. Here, as an example, four overlay error measurement marks MO ₀ are arranged at four corners in each shot area SA _p .

In FIG. 3C, the overlay error measurement mark MO ₀ is formed on the target layer by the first and second exposures in the double patterning method employed in the device manufacturing process of this embodiment. Shown with MO ₁ and MO ₂ . In this case, as an example of the overlay error measurement marks MO ₀ , MO ₁ , and MO ₂ , Bar in Bar marks are used.

As can be seen from FIG. 3C, the overlay error measurement mark MO ₀ includes a pair of line patterns having the X-axis direction as a longitudinal direction and arranged in parallel at a predetermined distance in the Y-axis direction, and the X-axis direction. A substantially square rectangular mark (Box mark) that includes four line patterns including a pair of line patterns that are arranged in parallel at a predetermined distance and whose longitudinal direction is the Y-axis direction, and lacks four corner portions as a whole. It has such a shape.

The overlay error measurement mark MO ₁ has a shape like a substantially square rectangular mark (Box mark) lacking four corner portions as a whole, and is almost similar to the overlay error measurement mark MO ₀ and slightly smaller. It is. Moreover, overlay error measuring mark MO ₂ has a shape such as rectangular marks substantially square four corners are missing as a whole (Box Mark), slightly almost similar to the overlay error measuring mark MO ₀ It is a big mark.

These three overlay error measurement marks have a positional relationship in which MO ₀ , MO ₁ , and MO ₂ are positioned so that the centers of the reference layer and the target layer substantially coincide with each other when exposure is performed without overlay errors. Designed.

Accordingly, by measuring the gap dimensions dx ₁ , dy ₁ and dx ₂ , dy ₂ between the overlay error measurement mark MO ₀ and the overlay error measurement marks MO ₁ , MO ₂ , the first and the first with respect to the reference layer pattern are measured. The overlay error of the first and second patterns formed on the target layer by the second exposure can be measured. In this case, the positional relationship between the overlay error measurement marks MO ₀ , MO ₁ , and MO _{2 is} measured at least at two locations for one shot region.

3A to 3C, the wafer W, shot area SA _p , wafer mark (MX _p , MY _p ), overlay error measurement mark MO (MO ₀ , MO ₁ , MO _2). ) Is merely an example, and the size, the number per shot area, the position of the wafer mark and the overlay error measurement mark, the shape, and the like can be changed as appropriate. Therefore, for example, a Box in Box mark may be used as the overlay error measurement mark.

In exposure apparatus 100, in order to perform accurate superposition of the device pattern may be measure the positional information of all shot areas SA _p on the wafer, but then, there is a possibility that the effect on throughput exits. Therefore, in exposure apparatus 100, limit the alignment marks to be actually measured, the position of the alignment mark measured, global alignment technique of statistically estimating the sequence of the shot areas SA _p on the wafer has been adopted. In the exposure apparatus 100, as this global alignment, the deviation of the actual shot area arrangement from the designed shot area arrangement is parallel to the X axis and Y axis, respectively, for example, a coordinate axis (Wx , represented by a polynomial of Wy) and / or such coordinate axes of the center of the shot area SA _p origin (Sx, Sy), determine the appropriate coefficients in the polynomial by performing the statistical calculation, the wafer alignment of the so-called EGA method It has been adopted. The wafer alignment by the EGA method, first, some selected shot areas SA _p which measures the alignment mark. The selected shot area is called a sample shot. Main controller 50 uses alignment system 8 to measure the position of sample marks (wafer marks MX _p and MY _p and overlay measurement mark MO ₀ ) attached to the sample shot. Such a measurement operation is hereinafter referred to as EGA measurement.

  In the EGA measurement, it is determined whether or not the measured waveform data is appropriate as data for extracting the mark waveform. Specifically, how accurately the mark waveform can be detected from the waveform data is obtained from the shape of the waveform data, and the degree is digitized and calculated as a detection result score. If the detection result score is better than a predetermined threshold, it is assumed that the sample mark has been detected, the mark detection result of the sample mark is OK, and otherwise, the mark detection result of the sample mark is NG. .

The wafer alignment by the EGA method, the results of the EGA measurement, i.e. by statistical calculation based on the position information of several sample marks, estimates the correction amount of the XY coordinates of each shot area SA _p. Such an operation is hereinafter referred to as an EGA operation. The EGA wafer alignment is disclosed in detail in, for example, US Pat. No. 4,780,617 and US Pat. No. 6,876,946. The latter method disclosed in US Pat. No. 6,876,946 and the like is also referred to as in-shot multipoint EGA. Here, the multipoint EGA in the shot uses the least square method disclosed in, for example, the above-mentioned US Pat. No. 6,876,946 using the position detection data of a plurality of wafer alignment marks in the shot area. It means an alignment method of obtaining the and shot area SA _p linear components of the deformation of itself (the linear component of the array of shot areas SA _p) sequence coordinates of all shot areas SA _p on the wafer W using a statistical technique.

  The XY correction amount at the position of each shot area obtained by the above EGA calculation is referred to as an EGA correction amount. Since the coefficient of the polynomial obtained by the EGA wafer alignment is obtained by the least square method, a deviation remains between the measured value of the mark position and the mark position corrected by the EGA correction amount. This deviation is called EGA residual error (or residual). Of course, it is desirable that the EGA residual error be smaller from the viewpoint of overlay accuracy.

One of the means for reducing the EGA residual error is higher order EGA polynomial model. For example, the EGA polynomial model, the scaling of the wafer W when with respect to the center of the linear component (wafer W of the arrangement of shot areas SA _p, rotation (X-axis of the array of shot areas corresponding orthogonal components of corresponding Y-axis rotation in consideration of the degrees), the components of the offset), the shot area SA _p linear components of the deformation of itself (the shot area SA _p scaling center of the shot area SA _p on the basis of the corresponding X-axis of rotation (shot area , Rotation considering also the orthogonality of the component corresponding to the Y axis), and each component of the offset), not the linear expression of (Wx, Wy) or (Sx, Sy), but of the arrangement of the shot area SA _p The EGA residual error is more effective when the quadratic expression (Wx, Wy) considering the second order component or the third order formula (Wx, Wy) considering the third order component of the shot region array is used. Small to. In general, the higher the EGA polynomial model, the smaller the overall EGA residual error, but care must be taken not to overcorrect. In order to increase the order of the EGA polynomial model, it is necessary to increase the number of sample marks accordingly. Of course, it is possible to adopt a model that also takes into consideration higher-order components of (Sx, Sy).

Further, when the measurement result of some sample marks is significantly deviated from the actual shot region arrangement, the overall residual tends to increase. Therefore, it is desirable to reject the measurement result of the position of the sample mark so that it is not used for the EGA calculation. That is, some of the position information of the sample marks measured by the EGA measurement, so as not to use the EGA calculation, it is possible to continue to improve the position estimation accuracy of the shot area SA _p. Thus, the selection of the number and / or arrangement of sample marks is an important factor for EGA wafer alignment.

  The exposure apparatus 100 can parameterize several factors that define operations related to the EGA wafer alignment performed by the alignment system 8 and set the set values as alignment-related parameters. The alignment-related parameters are roughly classified into waveform processing parameters that do not require remeasurement by the alignment system and adjustment parameters that require remeasurement in order to adjust the values.

As the waveform processing parameter, for example, there is a combination of sample marks (number and / or position of sample marks) selected from sample marks already measured and actually used for EGA calculation. That is, when all the measured sample marks are not used for the EGA calculation, but the EGA calculation is performed using an appropriate combination of the sample marks therein, the combination becomes the waveform processing parameter. In addition, the waveform processing parameters include the designation of sample mark rejection in mark units and shot area units, the rejection limit value at the time of mark detection (a threshold value for determining whether or not to reject a sample mark from EGA calculation), and the like. .

  In addition, when the alignment system 8 includes a plurality of types of alignment sensors and performs mark detection with all the sensors, the type of alignment sensor (FIA (FIA ()) that has detected the waveform data used to detect the actual mark position. Whether it is a field image alignment (LSA) method or an LSA (laser step alignment) method) is also included in the waveform processing parameters. Further, processing conditions for waveform data, that is, signal processing conditions (signal processing algorithms (edge extraction method, template matching method, aliasing autocorrelation method, slice level, etc.)) are also included in the waveform processing parameters.

  Also, types of EGA polynomial models (6 parameter model, 10 parameter model, in-shot averaging model, shot factor indirect application model, higher order EGA processing conditions (usage order and use correction coefficient), etc.), weighted EGA processing conditions, EGA Waveform processing parameters such as extended EGA processing conditions for optional functions (multi-point EGA execution conditions in shots, EGA calculation model, shot component correction conditions, etc.), correction amounts to be added to the measurement positions of measured marks (alignment correction values, etc.) include.

  In addition, the actual measurement parameters include the type of sample mark (including the case where the mark shape is different), the number and / or arrangement (when measuring a new sample point), and the illumination conditions when illuminating the mark during mark measurement ( Illumination wavelength, bright / dark field, illumination intensity, presence / absence of phase difference illumination, etc.), focus state at the time of mark detection (focus offset, etc.), specification of alignment sensor when changing the alignment sensor used for mark detection, etc. .

  In the exposure apparatus 100, control system parameters can be set as apparatus parameters in addition to alignment-related parameters. In the exposure apparatus 100, some of the factors that define the operation of each control system are converted into control system parameters, and these values can be set freely. The control system parameters are disclosed in detail in, for example, US Patent Application Publication No. 2008/0294280. The control system parameters and the alignment-related parameters are basically all variable, but some of the alignment-related parameters may be unchanged (fixed) without making all the alignment-related parameters variable. At this time, the user can appropriately select which alignment-related parameter is fixed.

  These set values need to be adjusted to some extent so that the device pattern on the reticle can be satisfactorily transferred onto the wafer.

  Returning to FIG. 1, in the track 200, a composite measurement / inspection instrument 120 capable of performing various measurement / inspections on the wafer before and after exposure of the wafer by the exposure apparatus 100, and a resist ( A coater / developer (hereinafter abbreviated as C / D) 110 is provided for applying the photosensitive agent) and developing the exposed wafer.

  The measurement / inspection instrument 120 can operate independently of the exposure apparatus 100 and the C / D 110. Further, the measurement / inspection instrument 120 can output the measurement / inspection results to the outside via a communication network in the system. In the present embodiment, the measurement / inspection instrument 120 performs a post-measurement inspection that is mainly a measurement inspection after exposure.

  In the post-measurement inspection of the measurement / inspection instrument 120, in addition to the defect / foreign particle inspection on the wafer W, the device pattern on the wafer W after the exposure (post-exposure) transferred by the exposure apparatus 100 and developed by the C / D 110 is superimposed. Measure the error. In a predetermined region on the reticle R (here, a pattern region where a device pattern is formed), overlay error measurement marks are formed at a plurality of different points. The overlay error measurement mark (also referred to as a registration mark) is not limited to the inside of the pattern area, but is also formed in an area around the pattern area as long as it can be transferred onto the wafer by the exposure apparatus 100 (exposure). However, in the following, it is assumed that it is formed in the pattern region for convenience of explanation.

The overlay error measurement mark is transferred onto the wafer W together with the device pattern by the exposure apparatus 100 during exposure. The measurement / inspection instrument 120 measures the positional relationship (relative displacement amount) of the overlay error measurement marks (for example, MO ₀ , MO ₁ , MO ₂ ) of each layer, and the shot area on the wafer W that is a transfer area of the device pattern. Measure the overlay error at each point. From this measurement result, it is possible to obtain the overlay error distribution of the pattern elements in the shot area.

  The analysis apparatus 500 is an apparatus that operates independently of the exposure apparatus 100, the C / D 110, and the measurement / inspection instrument 120. The analysis apparatus 500 collects various data (for example, processing data of the apparatus) from various apparatuses, and analyzes data relating to a series of processes for the wafer W. As hardware for realizing such an analysis apparatus 500, for example, a personal computer (hereinafter, abbreviated as “PC” as appropriate) can be employed. In this case, the analysis process is realized by executing an analysis program executed by a CPU (not shown) of the analysis apparatus 500. This analysis program is recorded on a medium (information recording medium) such as a CD-ROM, and is executed in a state where it is installed on the PC from the medium.

  The analysis apparatus 500 performs a simulation on wafer alignment of the exposure apparatus 100 based on the measurement results of the exposure apparatus 100 and the measurement / inspection instrument 120, and performs alignment-related parameters, correction parameters for synchronous scanning control, adjustment parameters for the projection optical system, and the like. To optimize.

  Incidentally, the exposure apparatus 100, the C / D 110, and the measurement / inspection instrument 120 are connected in-line to each other. Here, the in-line connection means that the apparatuses and the processing units in each apparatus are connected via a transfer apparatus that automatically transfers the wafer W such as a robot arm and / or a slider. By the in-line connection, the transfer time of the wafer W between the exposure apparatus 100 and the C / D 110 can be remarkably shortened.

  The exposure apparatus 100, the C / D 110, and the measurement / inspection instrument 120 connected in-line can be regarded as one substrate processing apparatus (100, 110, 120) as a unit. The substrate processing apparatus (100, 110, 120) has an application process for applying a sensitive agent such as a resist to the wafer W, and an exposure process for transferring a mask or reticle pattern onto the wafer W to which the sensitive agent has been applied. In addition, a developing process for developing the wafer after the exposure process is performed.

  In the device manufacturing system 1000, a plurality of exposure apparatuses 100, C / Ds 110, and measurement / inspection instruments 120 are provided. Each substrate processing apparatus (100, 110, 120) and device manufacturing processing apparatus group 900 is installed in a clean room in which temperature and humidity are controlled. In addition, data communication can be performed between devices via a predetermined communication network (for example, LAN: Local Area Network). This communication network is a so-called intranet communication network provided for a customer's factory, business office or company.

  In the substrate processing apparatus (100, 110, 120), a plurality of wafers (for example, 25 or 50) are processed as one unit (referred to as a lot). In the device manufacturing system 1000, wafers are processed and commercialized using one lot as a basic unit.

  In this device manufacturing system 1000, the measurement / inspection instrument 120 is placed in the track 200 and connected inline with the exposure apparatus 100 and the C / D 110. However, the measurement / inspection instrument 120 is disposed outside the track 200, Adjacent inline connection may be used, or the exposure apparatus 100 and C / D 110 may be configured offline.

  The device manufacturing system 1000 includes a CVD (Chemical Vapor Deposition) apparatus 910, an etching apparatus 920, a CMP (Chemical Mechanical Polishing) apparatus 930, an oxidation / ion implantation apparatus 940, and the like as the device manufacturing processing apparatus group 900. The CVD apparatus 910 is an apparatus that generates a thin film on a wafer. The etching apparatus 920 is an apparatus that performs etching on the developed wafer. In this embodiment, the etching apparatus 920 is provided with an ashing apparatus that removes resist and the like. The CMP apparatus 930 is a polishing apparatus that planarizes the surface of a wafer by chemical mechanical polishing. The oxidation / ion implantation apparatus 940 is an apparatus for forming an oxide film on the surface of the wafer or implanting impurities into a predetermined position on the wafer. Similarly to the exposure apparatus 100, the CVD apparatus 910, the etching apparatus 920, the CMP apparatus 930, and the oxidation / ion implantation apparatus 940 are also provided with a transfer path for enabling transfer of wafers between them. The device manufacturing processing apparatus group 900 includes various apparatuses that perform dicing processing, packaging processing, bonding processing, and the like, although not shown.

  The host 600 manages and manages the entire device manufacturing system 1000. Therefore, the host 600 controls and manages the exposure process performed in the exposure apparatus 100 and manages the scheduling of the exposure apparatus 100. A management controller for the exposure apparatus 100 may be provided separately from the host 600.

  Next, a device manufacturing process in the device manufacturing system 1000 will be described with reference to FIGS. 4 and 5A to 5J. FIG. 4 shows the flow of processing in the device manufacturing process. The processing flow in the device manufacturing process in the device manufacturing system 1000 is scheduled and managed by the host 600. The wafers W are processed in units of lots, but FIG. 4 shows a series of processes for one wafer W. Actually, a series of processing shown in FIG. 4 is repeated for each wafer in lot units. 5A to 5J are enlarged cross-sectional views of a part of one shot area on the wafer W. FIG.

  In this embodiment, the line width of the target layer 31 on the wafer W (see FIG. 5A, etc.) having a pitch P in the X-axis direction and a line width of P / 2 (that is, a space width of P / 2) The goal is to form a line-and-space pattern (hereinafter abbreviated as L / S pattern) having a ratio to the space width of 1: 1 by using a double process method (double patterning method). As an example, the pitch P is 64 nm, and at this time, the line width P / 2 is 32 nm. The resolution limit in the dry exposure of the exposure apparatus 100 is about 60 nm in the line width when the phase shift reticle is used, and the line width of the L / S pattern formed on the target layer 31 is the resolution limit. It is almost 1/2. Further, the dimensions of the pattern used in the description of the present embodiment are dimensions at the stage of the projection image. When the projection magnification β from the reticle R of the projection optical system PL to the wafer W is used, the reticle R of the pattern is used. The above dimensions are 1 / β times (4 times when β = 1/4).

[Film formation]
First, as a film formation process, a CVD apparatus 910 generates (deposits) a target layer 31 made of an interlayer insulating film such as an organic polymer on the wafer W as shown in FIG. On the target layer 31, a hard mask layer 32 made of ceramics such as a silicon oxide film or a silicon nitride film and having different reactivity to etching with both the target layer 31 and the resist is laminated. Instead of using the hard mask layer 32, a bi-layer (two-layer) resist can be used.

[Resist coating]
Next, the wafer W on which the target layer 31 and the hard mask layer 32 are formed is transferred to the C / D 110, and the surface (hard mask layer) of the wafer W is transferred to the C / D 110 as shown in FIG. A resist is applied to the upper surface 32) (the resist layer 33 is laminated). Here, a positive resist is used as an example.

[First exposure process]
Next, wafer W on which resist layer 33 is formed is transferred to exposure apparatus 100 and loaded onto wafer stage WST in exposure apparatus 100. Then, the exposure apparatus 100 performs a first exposure process on the wafer W.

  Here, as an example, the reticle R on the reticle stage RST of the exposure apparatus 100 includes a Y axis having a width P in the periodic direction (this is taken in the X axis direction) (the dimension at the stage of the projected image as described above, and so on). Phase shifter (phase shift unit) so that light shielding patterns elongated in the direction and transmission parts having a width P in the X-axis direction are arranged at a pitch of 2P in the X-axis direction, and the phase is alternately inverted to a series of adjacent transmission parts It is assumed that the phase shift type L / S pattern provided with is formed and the alignment of the reticle R has already been performed.

  In this case, for example, the exposure apparatus 100 sets the numerical aperture NA of the projection optical system PL to a large value (for example, 0.92) and the coherence factor (σ value) of the illumination optical system to a small value (for example, 0.2). The pattern of the reticle R is projected onto the wafer W by dry exposure. Note that the phase shift reticle is not limited to the spatial frequency modulation type, and may be another type such as a halftone type, or may be used in combination with modified illumination (for example, annular illumination or multipolar illumination). In addition, a normal reticle may be used instead of the phase shift reticle, and the illumination condition may be dipole illumination that illuminates the reticle with illumination light that is symmetrically inclined in the X-axis direction.

The main controller 50 performs the first wafer alignment (EGA measurement) on the wafer W using the alignment system 8, and performs a step-and-scan exposure operation based on the result, and the pitch of the reticle R An image of the 2P L / S pattern is transferred to each shot area on the wafer W. As a result, the exposed portion of the resist (the portion irradiated with light) increases the solubility in the developer (causes such a change), and as a result, as shown in FIG. It consists portions which were not exposed to the layer 33, a latent image corresponding to the device patterns having a line portion 33 ₂ is formed. Here, prior to the first wafer alignment (EGA measurement), an EGA optimization simulation, which will be described later, is performed, and the resulting optimized alignment conditions are sent from the analysis apparatus 500 to the exposure apparatus 100. The first wafer alignment is executed under the optimized alignment condition.

Exposure in the first exposure process, in FIG. 5 (B), the line width of the line portion 33 ₂ of the resulting device pattern in P, the width of the space portion is set to be P. Thus, when the exposure amount is set so that the ratio of the line width to the space width is 1: 1, the change in the exposure amount (light intensity) of the L / S pattern image near the sensitivity of the resist. Since the change amount of the position is small and the tolerance of the exposure amount error is large, the resist pattern can be easily formed with high accuracy.

[Development processing]
Next, the exposed wafer W is transferred to the C / D 110, and the wafer W (resist layer 33) is developed by the C / D 110. After development, as shown in FIG. 5 (B), the wafer W resist image of (hard mask layer 32) line portion 33 ₂ on (hereinafter, the resist image 33 using the resist image by using a line portion the same reference numerals ₂ ).

[First etching process]
Next, the wafer W is transferred to the etching apparatus 920, and in the etching apparatus 920,
A first resist slimming process and a subsequent etching process are performed. The first resist slimming treatment, etching the etching time, by setting so that the resist image 33 ₂ of the width P is a resist image 33 ₁ of a width P / 2 shown in FIG. 5 (C), a resist image 33 ₂ It is processing to do. As a result, on the hard mask layer 32, a resist image 33 ₁ having a width P / 2 (that is, a space width of 3P / 2) is arranged in a pitch 2P in the X-axis direction. A resist pattern with a ratio of 1: 3 is formed. In this case, it is possible that only manage the etching time, readily form a resist image 33 ₁ of a width P / 2.

Then, the etching of the hard mask layer 32 is performed using the resist image ₃₃₁ as a mask. After etching, as shown in FIG. 5 (D), a hard mask pattern (first pattern) 32 ₁ is obtained by arranging the hard mask portion 32 having a width P / 2 in the X-axis direction at a pitch 2P. Thereafter, the resist layer 33 (resist image 33 ₁ ) is peeled off from the wafer W by an ashing device (not shown).

[Resist coating]
Then, the wafer W hard mask pattern 32 ₁ on the target layer 31 is formed is transported to the C / D110, the C / D110, as shown in FIG. 5 (E), the surface of the wafer W (Hard resist is applied to the mask pattern 32 ₁ above) (resist layer 34 is formed).

[Second exposure process]
Next, the wafer W on which the resist layer 34 is formed is transferred to the exposure apparatus 100, and the exposure apparatus 100 performs a second exposure process on the wafer W. That is, the main controller 50 performs the second wafer alignment (EGA measurement) on the wafer W using the alignment system 8. In the second EGA, the same reference layer (underlayer) mark (the same number of marks and mark arrangement) as in the first EGA is detected in the same procedure. Thereby, when optimizing alignment-related parameters, which will be described later, development after the first exposure → etching → (antireflection film formation) → change in alignment mark signal shape due to the influence of wafer processing such as resist coating, Optimization of waveform signal acquisition parameters such as alignment focus, illumination wavelength, and NA (the above-mentioned actual measurement parameters required), and waveform processing parameters for the acquired waveform, such as mark detection parameters (algorithms, edge detection methods, tolerances, etc.) Can be optimized.

  For the same purpose, it is desirable to specify the EGA calculation model in common. In this way, after optimization of waveform signal acquisition parameters (alignment focus, illumination wavelength, NA, etc.) and optimization of mark detection parameters for the acquired waveform, the number of marks, mark arrangement, and EGA calculation are performed. It is possible to compare the results when the model conditions are changed. Also in this case, when the optimized alignment condition is sent from the analysis apparatus 500 to the exposure apparatus 100 prior to the alignment, the second wafer alignment is performed under the optimized alignment condition. Executed.

Based on the second alignment result, the main controller 50 performs a step-and-scan exposure operation to transfer the device pattern on the reticle R onto the wafer W. At this time, the positional relationship in the X-axis direction between the L / S pattern image of the pitch 2P on the reticle R and each shot area of the wafer W is 180 ° different from that in the case of the first exposure. In addition, exposure is performed while adjusting the positional relationship between the reticle R and the wafer W. As a result, the exposed portion of the resist (the portion irradiated with light) increases the solubility in the developer (causes such a change), and as a result, as shown in FIG. latent image corresponding to the device patterns having a line portion 34 ₂ formed of a portion not exposed to the layer 34 is formed.

Exposure amount in the second exposure also in FIG. 5 (F), the line width of the resist line 34 ₂ to be obtained by P, the width of the space portion is set to be P. Thus, a resist pattern having a ratio of line width to space width of 1: 1 can be easily formed with high accuracy. Furthermore, the resist image 34 ₂ is disposed on the two intermediate hard mask pattern 32 ₁ adjacent which are arranged at a pitch 2P in the X-axis direction, respectively.

[Development processing]
Next, the exposed wafer W is transferred to the C / D 110, and the wafer W (resist layer 34) is developed by the C / D 110. After development, as shown in FIG. 5 (F), the wafer W hard mask pattern (first pattern) is formed on (the target layer 31) 32 resist image of the line portion 34 ₂ with ₁ (hereinafter, the line of this resist image referred to as resist image 34 ₂ using parts the same reference numerals) is formed.

[Second etching process]
Next, the wafer W is transferred to the etching apparatus 920, and a second resist slimming process and a subsequent etching process are performed in the etching apparatus 920. Second resist slimming treatment, etching the etching time, by setting so that the resist image 34 ₂ of the width P is a resist image 34 ₁ of a width P / 2 shown in FIG. 5 (G), a resist image 34 ₂ It is processing to do. As a result, on the target layer 31, the ratio between the line width and the space width of 1: 3 of width P / 2 of the registration unit 34 ₁ from become the first periodic pattern (second pattern), the line width and the space width A mask layer 35 composed of a second periodic pattern (first pattern) composed of the hard mask pattern 32 _{1 having} a width P / 2 of 1: 3 is formed. Since the first periodic pattern and the second periodic pattern have a phase difference of 180 °, the mask layer 35 is regarded as a periodic pattern in which the ratio of the line width to the space width of the pitch P in the X-axis direction is 1: 1. be able to. Again, it is possible that only manage the etching time, readily form a resist image 34 ₁ of a width P / 2.

Next, the target layer 31 is etched using the periodic pattern of the mask layer 35 as a mask. After the etching, as shown in FIG. 5H, a pattern in which target portions 31 having a width P / 2 corresponding to the periodic pattern of the mask layer 35 used as a mask on the wafer W are arranged at the pitch P in the X-axis direction. Is obtained. Thereafter, the resist image 34 ₁ is peeled off from the wafer W by an ashing device (not shown), and then the hard mask pattern 32 _{1 shown} in FIG. Thus, as shown in FIG. 5 (J), the ratio of the target portion 31 ₁ of the width P / 2 formed by arranging the X-axis direction at a pitch P, a line width and a space width of 1: 1 L / S pattern is formed. In this case, when the pitch P is 64 nm, the target portion 31 ₁ of the width (line width) is 32 nm.

[Measurement inspection process]
Then, the wafer W L / S pattern of the target portion 31 ₁ and the line portion is formed is conveyed to the measuring test device 120, the measurement test instrument 120, the measurement inspection processing for the wafer W, i.e., formed on the target layer devices pattern error measuring mark _MO 0 overlay overlay error (shot area SA _p of (a target portion 31 ₁ and the line section to the L / S pattern) with a device pattern of the reference _layer, MO 1, MO ₂ (the relative displacement amount of FIG. 3C) is measured. Specifically, the gap dimensions dx ₁ , dy ₁ and dx ₂ , dy _{2 for} at least two overlay error measurement marks MO ₀ , MO ₁ , MO ₂ selected from four corners in the shot area SA _p . Is measured (measured), and the amount of relative displacement is calculated based on the measurement result. In response to a transfer request from the analysis device 500, the measurement result (overlay error measurement result) of the measurement / inspection instrument 120 is sent to the analysis device 500. In addition, the measurement / inspection instrument 120 also inspects foreign matters and defects on the pattern of the wafer W.

[Analysis processing]
Next, the analysis apparatus 500 analyzes the alignment-related parameters of the exposure apparatus 100 based on the overlay error measurement result sent from the measurement / inspection instrument 120. The analysis apparatus 500 sends the analysis result (analysis information) to the exposure apparatus 100. The exposure apparatus 100 performs processing such as updating apparatus parameters as necessary based on the information. Details of the analysis processing will be described later.

[Impurity diffusion, aluminum vapor deposition wiring processing]
In parallel with or subsequent to the analysis process, impurity diffusion to the etched wafer W, aluminum vapor deposition wiring process, film formation by the CVD apparatus 910, planarization by the CMP apparatus 930, oxidation / ion implantation apparatus 940 Ion implantation is performed as necessary. Thereby, the patterning process for the target layer 31 of the wafer W is completed.

  Next, the host 600 determines whether all the processes have been completed and all the patterns have been formed on the wafer W. If this determination is denied, the process returns to the film forming process, and if affirmed, the process proceeds to the next process. As described above, a series of patterning processes are repeatedly executed for the number of steps, whereby the device patterns are stacked on the wafer W to form semiconductor devices.

  After the repetition process is completed, the probing process and the repair process are executed in the device manufacturing processing apparatus group 900. When a defect is detected in the probing process, for example, a process of replacing with a redundant circuit is performed in the repair process. The analysis apparatus 500 can also send information such as the detected location where the overlay abnormality has occurred to an apparatus that performs the probing process and the repair process. In the inspection apparatus (not shown), the portion where the line width abnormality has occurred on the wafer W can be excluded from the processing target for the probing process and the repair process in units of chips. Thereafter, dicing processing, packaging processing, and bonding processing are executed, and a product chip is finally completed.

  Next, two analysis processes performed by the analysis apparatus 500, that is, a double patterning EGA optimization simulation and a double patterning overlay optimization simulation will be described.

  6 to 9 show flowcharts corresponding to the EGA optimization simulation. FIG. 10 shows a flowchart corresponding to the overlay optimization simulation performed following the EGA optimization simulation as necessary.

  First, EGA optimization simulation will be described.

  In the following, the reference layer is [layer 1], the layer corresponding to the first exposure process (double patterning first time) in the target layer is [Layer 2-1], and the second exposure process (second patterning second time) described above. It is expressed as a layer [Layer2-2] corresponding to. In the following, for convenience of explanation, when at least one of [Layer 2-1] and [Layer 2-2] is not optimized for the waveform processing parameter in the base EGA measurement, It is assumed that an EGA measurement simulation for parameter optimization (hereinafter abbreviated as EGA simulation as appropriate) itself is not performed. Moreover, as a premise, it is assumed that flags F1 to F6 described later are all lowered (reset).

  First, a base EGA measurement result file in [Layer 2-1] is acquired from the exposure apparatus 100 in the first step S1. Here, the base EGA measurement result file is a measurement file that becomes the base (base) of the EGA optimization simulation, and is an EGA calculation performed under predetermined reference alignment conditions (reference alignment related parameters) set by default. This file consists of a collection of raw data of results (reference calculation results). Here, the reference alignment conditions (reference alignment-related parameters) include the identification of the sample shot to be measured, the illumination conditions when measuring the mark, the waveform processing algorithm for the obtained mark signal, the EGA calculation model, etc. The conditions (parameters) set as predetermined conditions by default (including waveform processing parameters and actual measurement parameters required) are alignment conditions actually applied by the exposure apparatus 100. In step S1, a base EGA measurement result file in [Layer 2-1] is acquired from the EGA log data in the first exposure process described above in the target layer.

  In the next step S2, it is determined whether or not to optimize the waveform processing parameters in [Layer2-1] -based EGA measurement by waveform simulation. If the operator (user) has previously made a setting for optimizing the waveform processing parameters in the [Layer2-1] -based EGA measurement by waveform simulation, the determination in step S2 is affirmed, and step S3 Then, the waveform signal file of the [Layer2-1] base EGA measurement mark is acquired from the exposure apparatus 100. Here, the waveform signal file of the base EGA measurement mark is acquired from the EGA log data in the first exposure process described above in the target layer. Then, the process proceeds to step S4, the flag F1 is set (F1 ← 1), and then the process proceeds to step S5.

  In step S5, it is determined whether or not to acquire the [Layer2-1] comparison target EGA measurement result file from the exposure apparatus 100. Here, the comparison target EGA measurement result file is a file to be compared with the base EGA measurement result file, and part or all of the reference alignment conditions (for example, waveform signal acquisition conditions such as alignment focus, illumination wavelength, NA) This file consists of the raw data of the EGA calculation results (comparison calculation results) performed by changing (the above-mentioned actual measurement parameters required), and the operator cannot adjust the alignment focus, illumination wavelength, NA, etc. If the setting to acquire the [Layer2-1] comparison target EGA measurement result file has been made in advance for the purpose of optimizing the parameters that affect the waveform signal (waveform signal acquisition parameter or actual measurement parameter required) The determination in step S5 is affirmed, and the process proceeds to step S6. The [Layer 2-1] comparison target EGA measurement result file in which the waveform signal acquisition conditions (waveform signal acquisition parameters) such as alignment focus, illumination wavelength, and NA are changed is acquired from the exposure apparatus 100. Then, the process proceeds to step S7, and the flag After setting F2 (F2 ← 1), the process proceeds to step S8.

  In step S8, it is determined whether or not the optimization of waveform processing parameters in [Layer2-1] comparison target EGA measurement is performed by waveform simulation. If the operator has previously made a setting for optimizing the waveform processing parameters in the [Layer2-1] comparison target EGA measurement by waveform simulation, the determination in step S8 is affirmed and the process proceeds to step S9. Then, the waveform signal file of the [Layer 2-1] comparison target EGA measurement mark in which the waveform signal acquisition condition is changed is acquired from the exposure apparatus 100. Then, the process proceeds to step S10, and after setting the flag F3 (F3 ← 1), the process proceeds to step S11. On the other hand, if the determination in step S8 is negative, the process proceeds to step S11.

  On the other hand, if the operator has not made the setting for acquiring the [Layer 2-1] comparison target EGA measurement result file in advance, the determination in step S5 is denied, and the process jumps to step S11. If the determination in step S2 is negative, the process jumps to step S5 to determine whether or not to obtain a comparison target EGA measurement result file for the EGA simulation of [Layer2-1].

  In step S11, a base EGA measurement result file in [Layer2-2] is obtained from the exposure apparatus 100. Here, the base EGA measurement result file in [Layer 2-2] is acquired from the EGA log data in the second exposure process described above in the target layer.

  In the next step S12, it is determined whether or not waveform processing parameters in [Layer 2-2] based EGA measurement are optimized by waveform simulation. If the operator has previously made a setting for optimizing the waveform processing parameters in the [Layer2-2] -based EGA measurement by waveform simulation, the determination in step S12 is affirmed and the process proceeds to step S13. The waveform signal file of the [Layer2-2] base EGA measurement mark is acquired from the exposure apparatus 100. Here, the waveform signal file of the base EGA measurement mark is acquired from the EGA log data in the second exposure process described above in the target layer. Then, the process proceeds to step S14, the flag F4 is set (F4 ← 1), and then the process proceeds to step S15 in FIG.

  In step S15, it is determined whether or not to acquire the [Layer2-2] comparison target EGA measurement result file from the exposure apparatus 100. Then, for the purpose of optimizing the waveform signal acquisition parameters such as alignment focus, illumination wavelength, NA, etc. that cannot be handled by the waveform simulation, the operator sets [Layer 2-2] to acquire the comparison target EGA measurement result file. If it has been performed in advance, the determination in step S15 is affirmed, and the process proceeds to step S16 to expose the [Layer2-2] comparison target EGA measurement result file in which the waveform signal acquisition conditions such as alignment focus, illumination wavelength, and NA are changed. Obtained from the device 100. Then, the process proceeds to step S17, and after setting the flag F5 (F5 ← 1), the process proceeds to step S18.

  In step S18, it is determined whether or not the optimization of waveform processing parameters in [Layer 2-2] comparison target EGA measurement is performed by waveform simulation. If the operator has previously made a setting for optimizing the waveform processing parameter in [Layer 2-1] comparison target EGA measurement by waveform simulation, the determination in step S18 is affirmed and the process proceeds to step S19. Then, the waveform signal file of the [Layer 2-2] comparison target EGA measurement mark whose waveform signal acquisition condition is changed is acquired from the exposure apparatus 100. Then, the process proceeds to step S20, and after setting the flag F6 (F6 ← 1), the process proceeds to step S21. On the other hand, if the determination in step S18 is negative, the process proceeds to step S21.

  On the other hand, if the operator has not made the setting for acquiring the [Layer2-2] comparison target EGA measurement result file in advance, the determination in step S15 is negative, and the process jumps to step S21. If the determination in step S12 is negative, the process jumps to step S15 to determine whether to obtain a comparison target EGA measurement result file for the EGA simulation of [Layer2-2].

In Step S21, (1) [Layer2-1] threshold T1 and weight W1 for 3σ of EGA residual error,
(2) [Layer2-2] threshold T2 and weight W2 for 3σ of EGA residual error,
In addition, (3) the threshold T3 and the weight W3 are set for 3σ of the difference between the [Layer 2-1] EGA residual error and the [Layer 2-2] EGA residual error.

  In step S22, the number of marks, the mark arrangement, and the EGA calculation model are designated. The designation in step S22 is performed according to the designation contents of the designation condition file prepared in advance. The specified content may be set by an operator, a default setting, or a setting by a learning function based on experience. Here, the mark to be optimized is selected from a plurality of sample marks (measurement marks) measured by EGA in [Layer 2-1] and [Layer 2-2] performed in the exposure apparatus 100. That is, by rejecting an arbitrary measurement mark from among the plurality of sample marks (measurement marks) at the time of simulation, the number of marks and mark arrangement are designated and changed.

  In the next step S23, it is determined whether or not the waveform signal file of the [Layer2-1] base EGA measurement mark has been acquired by determining whether or not the flag F1 is set (F1 = 1). To do. If the determination in step S23 is affirmative, the process proceeds to step S24, and the optimization target, such as mark detection parameters, reject values, etc., for the [Layer2-1] base EGA measurement result file and the corresponding waveform signal file. Are changed by a predetermined procedure, and [Layer2-1] EGA simulation is executed. Thereafter, the process proceeds to step S25 in FIG.

  In the next step S25, it is determined whether or not the [Layer 2-1] comparison target EGA measurement result file is acquired by determining whether or not the flag F2 is set (F2 = 1). If this determination is affirmed, the process proceeds to step S26. In step S26, it is determined whether or not the waveform signal file of the [Layer 2-1] comparison target EGA measurement mark has been acquired by determining whether or not the flag F3 is set (F3 = 1). . If the determination in step S26 is affirmed, the process proceeds to step S27, and the [Layer2-1] comparison target EGA measurement result file and the [Layer2-1] comparison target EGA measurement mark waveform signal file are marked. [Layer2-1] EGA simulation is executed by changing parameters to be optimized, such as detection parameters and reject values. On the other hand, when the determination in step S26 is negative, that is, the [Layer2-1] comparison target EGA measurement result file is acquired, but the [Layer2-1] comparison target EGA measurement mark waveform signal file is not acquired. In this case, the process proceeds to step S28, and the [Layer2-1] EGA simulation is executed by changing the optimization target parameters such as the reject value for the [Layer2-1] comparison target EGA measurement result file. And in any case of step S27 and step S28, after simulation execution, it transfers to step S29.

  On the other hand, if the determination in step S25 is negative, that is, if the [Layer2-1] comparison target EGA measurement result file has not been acquired, the process proceeds to step S29.

  In step S29, the [Layer2-1] EGA simulation result that satisfies the threshold value T1 for 3σ of the [Layer2-1] EGA residual error set in step S21 is stored, and then the process proceeds to step S30.

  On the other hand, if the determination in step S23 is negative, that is, if the waveform signal file of the [Layer2-1] base EGA measurement mark is not acquired, the EGA simulation for optimizing the waveform processing parameters is not performed. Then, step S24 is skipped, and the process proceeds to determination of execution of the EGA simulation for optimizing the actual measurement parameter required.

  In the next step S30, it is determined whether or not the waveform signal file of the [Layer2-2] base EGA measurement mark has been acquired by determining whether or not the flag F4 is set (F4 = 1). To do. If the determination in step S30 is affirmative, the process proceeds to step S31, and the optimization target, such as mark detection parameters, reject values, etc., for the [Layer2-2] base EGA measurement result file and the corresponding waveform signal file. Are changed by a predetermined procedure, and [Layer2-2] EGA simulation is executed. Thereafter, the process proceeds to step S32.

  In the next step S32, it is determined whether or not the [Layer2-2] comparison target EGA measurement result file has been acquired by determining whether or not the flag F5 is set (F5 = 1). If this determination is affirmed, the process proceeds to step S33. In step S33, it is determined whether or not the waveform signal file of the [Layer 2-2] comparison target EGA measurement mark has been acquired by determining whether or not the flag F6 is set (F6 = 1). . If the determination in step S33 is affirmed, the process proceeds to step S34, where the [Layer2-2] comparison target EGA measurement result file and the waveform signal file of the [Layer2-2] comparison target EGA measurement mark are marked. [Layer2-2] EGA simulation is executed by changing parameters to be optimized, such as detection parameters and reject values. On the other hand, if the determination in step S33 is negative, that is, the [Layer2-2] comparison target EGA measurement result file is acquired, but the [Layer2-2] comparison target EGA measurement mark waveform signal file is not acquired. In such a case, the process proceeds to step S35, and the [Layer2-2] EGA simulation is executed for the [Layer2-2] comparison target EGA measurement result file by changing the optimization target parameters such as the reject value. And in any case of step S34 and step S35, it transfers to step S36 after simulation execution.

  On the other hand, if the determination in step S32 is negative, that is, if the [Layer2-2] comparison target EGA measurement result file has not been acquired, the process proceeds to step S36.

  In step S36, the [Layer2-2] EGA simulation result satisfying the threshold value T1 for the 3Layer of [Layer2-2] EGA residual error set in step S21 is stored, and then the process proceeds to step S37.

  On the other hand, if the determination in step S30 is negative, that is, if the waveform signal file of the [Layer 2-2] base EGA measurement mark is not acquired, the EGA simulation for optimizing the waveform processing parameters is not performed. Then, step S31 is skipped, and the process proceeds to determination of execution of the EGA simulation for optimizing the actual measurement parameter required.

  In step S37, it is determined whether or not the flags F1 ≠ 1 and F2 ≠ 1 are satisfied, or the flags F4 ≠ 1 and F5 ≠ 1 are satisfied, so that [Layer2-1] and [Layer2 -2], it is determined whether an EGA simulation has been performed. If the determination in step S37 is affirmative, that is, if EGA simulation is not performed for at least one of [Layer 2-1] and [Layer 2-2], the process is forcibly terminated.

  On the other hand, if the determination in step S37 is negative, the process proceeds to step S38, and the [Layer2-1] EGA simulation result saved in step S29 and the [Layer2-2] EGA simulation result saved in step S36. Thus, 3σ of the difference between the [Layer2-1] EGA residual error and the [Layer2-2] EGA residual error is obtained, and the 3σ of this difference satisfies the threshold value T3 set in step S21. [Layer2-1] EGA simulation result And all the combinations of [Layer2-2] EGA simulation results.

In the next step S39, the evaluation value represented by the following expression (1) among all the combinations of the [Layer2-1] EGA simulation result and the [Layer2-2] EGA simulation result stored in the step S38. The combination of the [Layer2-1] EGA simulation result and the [Layer2-2] EGA simulation result that minimizes the EV is determined as the optimum condition.
EV = ([Layer2-1] 3σ of EGA residual error) × W1
+ ([Layer2-2] EGA residual error 3σ) × W2
+ (3σ of difference between [Layer2-1] EGA residual error and [Layer2-2] EGA residual error) × W3 (1)
In the above equation (1), W1, W2, and W3 are set in step S21.
[Layer 2-1] EGA residual error 3σ, [Layer 2-2] EGA residual error 3σ, and [Layer 2-1] EGA residual error and [Layer 2-2] EGA residual error 3σ respectively.

  In the next step S40, for the number of marks and / or the mark arrangement and / or the EGA calculation model, for example, it is determined whether or not the optimization simulation has been executed for all the conditions specified in the above-mentioned specified condition file. . If the determination is affirmed, the process proceeds to step S41. If the determination is negative, the process returns to step S22, and the processes in and after step S22 are repeatedly executed until the determination in step S40 is affirmed. That is, the optimization simulation is continued with the number of marks and / or the mark arrangement and / or the EGA calculation model as an optimization target.

  In step S41, it is determined whether it is necessary to continue the repeated optimization simulation by changing at least one of the threshold values T1 to T3 and the weights W1 to W3. In this step S41, for example, it is determined whether or not an EGA simulation result satisfying the respective threshold values T1, T2, and T3 could not be saved in at least one of steps S29, S36, and S38. However, the present invention is not limited to this, and the operator may be allowed to set the continuation of the optimization simulation repeatedly. In this case, the setting contents are followed.

  If the determination in step S41 is negative, the process proceeds to step S42. If the determination is positive, the process returns to step S21, and the processes in and after step S21 are repeatedly executed until the determination in step S41 is negative. That is, the optimization simulation is continued by changing at least one of the threshold values T1 to T3 and the weights W1 to W3.

  In step S42, the above-described optimized EGA simulation result (a combination of the [Layer2-1] EGA simulation result and the [Layer2-2] EGA simulation result determined as the optimum condition in step S39) and the base EGA measurement result are expressed by the above equation. The evaluation value EV represented by (1) is compared.

  In the next step S43, an optimized EGA simulation result in which the evaluation value EV is smaller than the base EGA measurement result and the evaluation value EV is minimum is determined (selected) as the double patterning optimization EGA condition. In this case, a plurality of conditions (optimized EGA simulation results) may be determined (selected) as the double patterning optimization EGA conditions.

  Thereby, the EGA optimization simulation is terminated (step S44). For example, when there is one determined optimized EGA simulation result, the result is sent from the analysis apparatus 500 to the exposure apparatus 100. The exposure apparatus 100 sets the alignment-related parameters according to the optimized EGA simulation result for the first and second exposure processes of the subsequent double patterning (from the next wafer, the wafer of the next lot, or the next layer on the same wafer). Commonly applied to wafer alignment.

  Next, a double patterning overlay optimization simulation will be described. This double patterning overlay optimization simulation is performed, for example, when a plurality of conditions (optimized EGA simulation results) are determined (selected) as a result of the above-described optimized EGA simulation.

  After execution of the EGA optimization simulation, a double patterning overlay optimization simulation is started in step S44 of FIG.

  After the start, in step S45, the base overlay measurement result file is acquired from the measurement / inspection instrument 120 or the exposure apparatus 100. Here, the base overlay measurement result file is a measurement file that becomes the base (base) of the overlay optimization simulation.

In step S46, [Layer2-1], [Layer2-2], and [Layer2-1] between the optimized EGA simulation result determined in (selected) in step S43 and the base EGA measurement result as the optimized EGA condition are For each difference from [Layer2-2], change Δ [Layer2-1], Δ [Layer2-2], and Δ ([Layer2-1]-[Layer2-2]) As a result, the optimization simulation similar to the above-described EGA optimization simulation is performed on the overlay measurement result when the optimization target alignment-related parameters (including exposure conditions and alignment correction values) are changed. In this optimization simulation, a deviation 1 between [Layer 1] and [Layer 2-1], a deviation 2 between [Layer 1] and [Layer 2-2], and a deviation 3 between [Layer 2-1] and [Layer 2-2] The overlay simulation results satisfying the respective threshold values are selected and stored. Here, shift 1, shift 2, shift 3, for example, the design distance between the marks MO ₀ and mark _{MO 1 (dx 10, dy 10} ), the measurement interval _(dx 1, _dy 1), and the mark MO ₀ When the design interval between the mark MO ₂ and the mark MO ₂ is (dx ₂₀ , dy ₂₀ ) and the measurement interval is (dx ₂ , dy ₂ ), a superposition error (a plurality of overlay errors) between [Layer 1] and [Layer 2-1] Dx ₁ -dx ₁₀ , dy ₁ -dy ₁₀ ) for measurement marks, and overlay error between [Layer 1] and [Layer 2-2] (dx ₂ -dx ₂₀ , dy _2- for multiple overlay error measurement marks) dy ₂₀ ), overlay error between [Layer 2-1] and [Layer 2-2] ((dx ₁ + dx ₂ ) − (dx ₁₀ + dx ₂₀ ), (dy ₁ + dy ₂ ) for a plurality of overlay error measurement marks) _{- (dy 10 + dy 20)} ) Is (mean + 3σ) for respectively.

In the optimization simulation, the overlay simulation result that minimizes the evaluation value EV ′ represented by the following equation (2) is determined as the optimum condition (optimum overlay simulation result).
EV ′ = (deviation 1 between [Layer1] and [Layer2-1]) × W1
+ (Difference between [Layer1] and [Layer2-2] 2) x W2
+ (Difference 3 between [Layer2-1] and [Layer2-2] 3) x W3 (2)
In the next step S47, the evaluation value EV ′ represented by the above equation (2) is compared between the optimum overlay simulation result and the base overlay measurement result.

  Then, in the next step S48, the overlay simulation result (corresponding to the optimized EGA simulation result) in which the evaluation value EV ′ is smaller than the base overlap measurement result and the evaluation value EV ′ is minimum is used as the double patterning optimum. The alignment conditions are determined. Then, the determined optimized alignment condition is sent from the analysis apparatus 500 to the exposure apparatus 100. The exposure apparatus 100 applies the optimized alignment conditions in common to the wafer alignment in the subsequent double patterning first and second exposure processes (next wafer, wafer of the next lot, or subsequent layers for the same wafer). To do.

  In addition, the deviation 1 to the deviation 3 in the above formula (2) may be set so that the superposition error 3σ or the average value can be designated.

  In this embodiment, the EGA optimization simulation and the overlay optimization simulation are performed for each wafer W. However, for example, every few wafers or at regular time intervals (every hour, every other day, every week). It is also possible to perform it at every other). This interval may be fixed or variable. For example, based on the execution history of the EGA optimization simulation and the overlay optimization simulation, the frequency may be decreased when the overlay accuracy is stable, and may be increased when the overlay accuracy is lowered. good.

  Further, if all of the above-described alignment processing parameters are to be optimized as alignment processing parameters to be optimized, the amount of calculation becomes enormous and the time required for optimization becomes long. Therefore, in the present embodiment, parameters to be optimized are limited by user setting or automatic setting. In the automatic setting, for example, an alignment processing parameter optimized by a past EGA optimization simulation (or greatly changed by optimization) may be automatically set as an optimization target.

  As described above in detail, according to the EGA optimization simulation (the alignment-related parameter optimization method, that is, the alignment condition optimization method) performed by the analysis apparatus 500 of the present embodiment, the first wafer alignment (EGA The results (step S29) of the EGA simulation (steps S24, S27, S28) using the measurement results of (measurement) and the EGA simulations (steps S31, S34, S35) using the measurement results of the second wafer alignment The alignment process parameters are optimized using the result (step S36) (steps S38, 39, 42, 43). Therefore, by following this optimized alignment condition (positioning condition), even when a pattern is formed on the wafer W by using the double patterning method, a high overlay accuracy of the pattern of the target layer with respect to the base pattern and It is possible to achieve high alignment accuracy between the first pattern formed in the first lithography process and the second pattern formed in the second lithography process with respect to the target layer.

In the EGA optimization simulation according to the present embodiment, the alignment condition is optimized using an index EV (see Expression (1)) obtained from the EGA residual error. Accordingly, by appropriately determining the weights W ₁ , W ₂ , and W ₃ , the second pattern comprising the first pattern of the target layer (for example, the hard mask pattern 32 _{1 in} FIG. 5D) with respect to the pattern of the reference layer (underlying layer). periodic pattern) of overlay accuracy, the reference layer overlay accuracy (the second pattern of the target layer for the pattern of the underlying layer) (e.g., Fig. 5 (H) a first periodic pattern made of a resist portion 34 ₁ shown in), It is possible to optimize the alignment condition by focusing on any one or any two or all of the overlay accuracy of the second pattern with respect to the first pattern of the target layer 31.

Further, according to the overlay optimization simulation in the present embodiment, the overlay error measurement mark (MO ₀ ) formed together with the pattern of the reference layer (underlayer) and the first pattern (second period pattern) of the target layer. Using the detection results of the overlay error measurement mark (MO ₁ ) formed together with the overlay error measurement mark (MO ₂ ) formed together with the second pattern (first periodic pattern) of the target layer. Conditions and alignment conditions are optimized (steps S46 to S48). Therefore, according to this optimized alignment condition, even when a pattern is formed on the wafer W using the double patterning method, it is possible to realize a high overlay accuracy of the pattern.

  In the above embodiment, the case where the overlay optimization simulation (step 45 to step S48) is performed after the EGA optimization simulation (step S1 to step S44) has been described, but only the EGA optimization simulation is performed alone. It is good to do. In that case, for example, an EGA optimization simulation can be performed after the second exposure process. Furthermore, the overlay optimization simulation (step 45 to step S48) may be performed independently of the EGA optimization simulation (step S1 to step S44) or independently. In that case, the initial setting similar to the initial setting of the EGA optimization simulation is performed within a necessary limit in step S45 or prior thereto. In steps S47 and S48, the analysis apparatus 500 obtains the index EV ′ for each of the designated overlay conditions, and determines the overlay condition that gives the minimum value of the index EV ′ as the optimized overlay condition.

  In addition, according to the device manufacturing system 1000 of the present embodiment, after the above-described step S44 or step S48 is completed, an optimization EGA simulation result (corresponding optimization alignment condition) or optimization alignment condition is applied from the analysis apparatus 500 to the exposure apparatus 100. In the device manufacturing process, the optimized alignment condition is set by the exposure apparatus 100 in the first exposure process and the second exposure process for forming a pattern on the target layer on the wafer W. The wafer alignment applied in common is performed. Accordingly, after the optimized EGA simulation result (corresponding optimized alignment condition) or the optimized alignment condition is sent from the analysis apparatus 500 to the exposure apparatus 100, for example, the next wafer, the wafer of the next lot, or the subsequent layer for the same wafer. Thus, it is possible to achieve high overlay accuracy of the pattern of the target layer with respect to the base pattern and high alignment accuracy of the first pattern and the second pattern. The optimized alignment condition may be applied only in either the first exposure process or the second exposure process. Even in such a case, it is possible to realize high overlay accuracy of the pattern of the target layer with respect to the base pattern.

  In the device manufacturing process performed in the device manufacturing system 1000 of the present embodiment, the mask layer (35) is exposed to the target layer (31) on the wafer W by exposing the first pattern and the second pattern by the pattern forming method described above. The target layer (31) is etched using the mask layer (35) as a mask. Therefore, for example, even a line width pattern that is less than the resolution limit of the projection optical system can be formed with high accuracy.

  In the above embodiment, in steps S2, S5, S8, S12, S15, S18 and the like, various files are acquired according to the operator's presetting. However, the present invention is not limited to this, (steps S2, S5 , S8) and / or (Steps S12, S15, S18) are omitted, and for at least one of [Layer2-1] and [Layer2-2], the base EGA measurement result file and the comparison EGA measurement result file The waveform signal file of the comparison target EGA measurement mark may be automatically (always) acquired. Alternatively, any determination step of steps S2, S5, S8, S12, S15, and S18 so that a file having a high frequency of acquisition is automatically acquired based on the past execution history of the optimization simulation. May be omitted.

  In the above embodiment, for convenience of explanation, when optimization of waveform processing parameters in base EGA measurement is not performed for at least one of [Layer 2-1] and [Layer 2-2], at least one of them is not performed. For the layers, the EGA measurement simulation itself for parameter optimization was not performed. However, the present invention is not limited to this, and a file necessary for the optimization simulation may be arbitrarily acquired from the various files described above. However, when the comparison target EGA measurement result file is not acquired, it is not necessary to be able to acquire the waveform signal file of the comparison target EGA measurement mark corresponding thereto.

  In the above embodiment, the [Layer2-1] EGA simulation result is stored in step S29, and the [Layer2-2] EGA simulation result is stored in step S36, that is, [Layer2-1] and [Layer-2] The double patterning optimization EGA condition is determined only when the EGA optimization simulation is performed with both of the layers 2-2 and the first and second exposure processes of the subsequent double patterning. Optimized EGA conditions that are commonly applied to wafer alignment (EGA measurement) for each are obtained. However, the present invention is not limited to this, and it is also possible to individually obtain optimized EGA conditions for the first and second exposure processes after the next layer. In this case, for example, a set of alignment processing parameters that gives the minimum value of the EGA residual error is determined as an optimized EGA condition for wafer alignment (EGA measurement) in the first exposure processing, and an EGA optimization simulation is performed using the result. , And a set of alignment processing parameters that gives the minimum value of EGA residual error may be determined as an optimized EGA condition for wafer alignment (EGA measurement) in the second exposure processing.

  In the above embodiment, when obtaining the overlay optimization alignment condition, (shift 1 between [Layer 1] and [Layer 2-1] 1), (shift 2 between [Layer 1] and [Layer 2-2]), ( The case has been described where the evaluation value EV ′ represented by Expression (2) including the deviation 3) between [Layer 2-1] and [Layer 2-2] is used. However, the present invention is not limited to this, and any one or two of the deviation 1, the deviation 2, and the deviation 3 in the above formula (2) are set to 0, or any one or two of the weights W1, W2, and W3. It is also possible to obtain the overlay optimization alignment condition using an evaluation value where one is zero.

It is also possible to evaluate the pattern overlay accuracy using the EGA optimization simulation in this embodiment. Here, by appropriately determining the weights W ₁ , W ₂ , and W ₃ , the overlay accuracy of the first pattern of the target layer with respect to the pattern of the reference layer (underlayer) using the index EV obtained from the EGA residual error Emphasis is placed on either or any two or all of the overlay accuracy of the second pattern of the target layer with respect to the pattern of the reference layer (underlayer), the overlay accuracy of the second pattern with respect to the first pattern of the target layer Thus, the overlay accuracy of the pattern can be accurately evaluated.

  In the device manufacturing system 1000, the analysis apparatus 500 is a separate apparatus independent of various device manufacturing processing apparatuses, but the present invention is not limited to this. For example, any device manufacturing processing apparatus in the system may of course have the analysis function of the analysis apparatus 500. For example, the main controller 50, the measurement / inspection instrument 120, or the host 600 of the exposure apparatus 100 may be provided with analysis functions such as the above-described EGA optimization simulation and overlay optimization simulation.

  In the above embodiment, a double patterning method including a resist trimming process for forming a resist image having a desired line width (a line width less than the resolution limit of the exposure apparatus) and a desired pitch is used. Although the case where the invention is applied has been described, the present invention is not limited to this. For example, a double patterning method including a sidewall coating process (Sidewall Process), a pitch splitting type without resist trimming, and other types of double patterning methods. Also, the present invention can be preferably applied.

  In the device manufacturing process of the present embodiment, prior to each of the first and second exposure processes, a pre-measurement / inspection process may be performed on the wafer W to be exposed by the measurement / inspection instrument 120. As the pre-measurement inspection process, a part of the analysis process (EGA optimization simulation and overlay optimization simulation) may be included, and the process may be performed immediately before the first exposure process and the second exposure process.

  Further, according to the present embodiment, the analysis device 500 is a computer, and the analysis function is realized by a program that causes the computer to execute the analysis function. Since this program is downloaded from the Internet or installed from a state recorded on an information recording medium such as a CD-ROM, the analysis function itself can be easily added, changed, or modified.

  In the present embodiment, the exposure apparatus 100 is a step-and-scan type exposure apparatus, but is not limited thereto, and may be a step-and-repeat type or other type of exposure apparatus. As represented by this, the various apparatuses are not limited to those types. The present invention is not limited to a semiconductor manufacturing process, and can be applied to a manufacturing process of a display including a liquid crystal display element. In addition to the process of transferring the device pattern onto the glass plate, the manufacturing process of the thin film magnetic head, and the manufacturing process of the imaging device (CCD, etc.), micromachine, organic EL, DNA chip, etc. Of course, the present invention can be applied to management.

  In the above embodiment, the analysis apparatus 500 is a personal computer, for example. That is, the analysis processing in the analysis apparatus 500 is realized by executing an analysis program on a PC. As described above, the analysis program may be installable on the PC via the medium as described above, or may be downloaded to the PC via the Internet or the like. Of course, the analysis apparatus 500 may be configured by hardware.

  As described above, the alignment condition optimization method and overlay accuracy evaluation method of the present invention are suitable for managing overlay accuracy when the double patterning method is employed. The pattern forming method and device manufacturing method of the present invention are suitable for manufacturing a microdevice.

100 ... exposure apparatus, 110 ... C / D, 120 ... measuring test device, 500 ... analysis device, 900 ... device manufacturing processing apparatus group, 1000 ... device manufacturing system, W ... wafer, _MO 0 ~MO 2 _... overlay error measurement mark.

Claims (62)

A reference that is a reference for superimposing a pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object and the pattern formed on the object prior to the target layer. An alignment condition optimization method for optimizing alignment conditions with an underlying pattern formed on a layer,
When the first pattern is formed on the target layer so as to overlap the base pattern formed on the reference layer on the object, the reference layer detected for alignment of the first pattern with respect to the base pattern A first detection result of at least some of the first marks formed with the base pattern and a second pattern on the target layer on which the first pattern is formed on the object. When forming, using a second detection result of at least some of the plurality of first marks detected for alignment of the second pattern with respect to the base pattern, and An alignment condition including a step of optimizing an alignment condition of a pattern formed on the target layer with respect to a base pattern formed on the reference layer on the object; Optimization method.   In the step of optimizing, a first alignment error of the first pattern with respect to the base pattern is obtained using the first detection result, and the second alignment with respect to the base pattern is performed using the second detection result. A second alignment error of the pattern is obtained, and the alignment of the pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object is obtained using the first and second alignment errors. The alignment condition optimization method according to claim 1, wherein the condition is optimized.   The alignment condition optimization method according to claim 2, wherein in the optimization step, the first and second alignment errors are obtained using a plurality of model equations for obtaining an alignment error.   In the step of optimizing, at least one of a variation in the first alignment error and a variation in the second alignment error, a variation in a difference between the first alignment error and the second alignment error, The alignment condition optimization method according to claim 2 or 3, wherein the alignment condition is optimized on the basis of.   In the step of optimizing, based on the variation in the first alignment error, the alignment condition for aligning the first pattern with the base pattern is optimized, and the variation in the second alignment error. The alignment condition optimization method according to claim 4, wherein alignment conditions for aligning the second pattern with the base pattern and the first pattern are optimized based on the difference variation.   5. The optimization step includes optimizing the alignment condition using an index value as a sum of a variation in the first alignment error, a variation in the second alignment error, and a variation in the difference. Or the alignment condition optimization method according to 5.   The alignment according to claim 6, wherein the sum is obtained by adding weights determined for each of the first alignment error variation, the second alignment error variation, and the difference variation. Condition optimization method.   The alignment condition optimization method according to claim 6 or 7, wherein, in the optimization step, the alignment condition that gives a variation in the first alignment error equal to or less than a predetermined first threshold is extracted.   The alignment condition according to any one of claims 6 to 8, wherein in the optimization step, the alignment condition that gives a variation in the second alignment error equal to or less than a predetermined second threshold is extracted. Optimization method.   10. The alignment step according to claim 6, wherein in the optimization step, the alignment condition that gives a variation in the difference equal to or less than a predetermined third threshold is extracted from the extracted alignment conditions. The alignment condition optimization method according to item.   The alignment condition optimization according to any one of claims 8 to 10, wherein in the optimization step, the alignment condition that minimizes the index value is extracted from the extracted alignment conditions. Method.   In the optimization step, among the extracted alignment conditions, alignment conditions for forming the first pattern and alignment conditions for forming the second pattern, which are optimization criteria, are used. The alignment condition optimization method according to claim 11, wherein the alignment condition corresponding to an index value smaller than the index value corresponding to is extracted.   In the step of optimizing, the first mark, the second mark formed with the first pattern on the first mark, and the second pattern formed with the first and second marks are formed. The alignment condition optimization method according to claim 8, wherein an optimum condition is extracted from the extracted alignment conditions by using a third detection result obtained by detecting the third mark.   The optimization step includes evaluating the overlay accuracy of the base pattern, the first pattern, and the second pattern using the third detection result, and extracting the optimum condition that gives the best overlay accuracy. Item 14. The alignment condition optimization method according to Item 13.   The alignment condition optimization method according to claim 14, wherein the overlay accuracy of the ground pattern, the first pattern, and the second pattern is given by a sum of variations in overlay errors between the patterns.   The alignment condition optimization method according to claim 15, wherein the sum is obtained in consideration of a weight determined for an overlay error between patterns.   The alignment condition optimization method according to claim 1, wherein the alignment condition includes at least one of a condition related to the exposure and a condition related to detection of the first mark. The first mark is detected by imaging,
Each of the first and second detection results includes an imaging result of the first mark,
The alignment condition optimization method according to claim 17, wherein the alignment condition includes a processing condition for an imaging result of the first mark. A pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object, and a reference for overlaying the pattern formed on the object prior to the target layer An alignment condition optimization method for optimizing alignment conditions with an underlying pattern formed on a reference layer,
A first mark formed with the base pattern on the object; a second mark formed with the first pattern on the target layer upon the first exposure; The reference on the object is detected using a detection result obtained by detecting a third mark formed together with a second pattern formed in the second exposure on the target layer over the second mark. An alignment condition optimization method including a step of optimizing an alignment condition of a pattern formed on the target layer with respect to a base pattern formed on the layer.   The optimization step includes evaluating the overlay accuracy of the base pattern, the first pattern, and the second pattern using the detection result, and optimizing the alignment condition using the overlay accuracy. 20. The alignment condition optimization method according to 19.   21. The alignment condition optimization method according to claim 20, wherein the overlay accuracy of the ground pattern, the first pattern, and the second pattern is given by a sum of overlay error variations between the patterns.   The alignment condition optimization method according to claim 21, wherein the sum is obtained in consideration of a weight determined for an overlay error between patterns.   The alignment condition optimization method according to any one of claims 19 to 22, wherein the alignment condition includes a condition related to the exposure. A pattern forming method in which a pattern is overlaid on a target layer by superimposing a pattern through a plurality of lithography steps including exposure and development, overlaid on a base pattern already formed on an object,
First and second patterns formed on the target layer by a first exposure and a second exposure on the target layer on the object, and a pattern formed on the object prior to the target layer A step of optimizing the alignment condition with the base pattern formed on the reference layer serving as a reference for the superposition using the alignment condition optimization method according to any one of claims 1 to 23. ;
The first and second exposures are performed on the target layer on the object by aligning the first and second patterns with respect to the base pattern formed on the object, thereby performing the first and second exposures. Forming two patterns on the target layer, and performing the alignment under the optimized alignment condition at least one of a first exposure and a second exposure on the target layer on the object; A pattern forming method. A step of forming a mask layer by exposing the first pattern and the second pattern to a target layer on an object by the pattern forming method according to claim 24;
Processing the target layer using the mask layer;
A device manufacturing method including: Formed multiple times through a lithography process including a base pattern formed on a reference layer that is a reference for pattern superimposition prior to a target layer on an object, and exposure and development on the target layer superimposed on the base pattern. An overlay accuracy evaluation method for evaluating overlay accuracy with a pattern to be performed,
When the first pattern is formed over the base pattern formed on the reference layer on the object, the base layer is detected together with the base pattern detected for alignment of the first pattern with respect to the base pattern. When forming the second pattern on the target layer where the first pattern on the object and the first detection result of at least some of the formed first marks and the first pattern on the object are formed. And the second detection result of the at least some of the first marks detected for alignment of the second pattern with respect to the base pattern, and the first pattern and the second with respect to the base pattern An overlay accuracy evaluation method for evaluating overlay accuracy with a pattern.   A first alignment error of the first pattern with respect to the background pattern is obtained using the first detection result, and a second alignment of the second pattern with respect to the background pattern is determined using the second detection result. 27. The overlay accuracy evaluation method according to claim 26, wherein an error is obtained and the overlay accuracy is evaluated using the first and second alignment errors.   28. The overlay accuracy evaluation method according to claim 27, wherein the first and second alignment errors are obtained using a plurality of models for obtaining the alignment error.   Based on at least one of the variation in the first alignment error and the variation in the second alignment error and the variation in the difference between the first alignment error and the second alignment error. The overlay accuracy evaluation method according to claim 27 or 28, wherein the alignment accuracy is evaluated.   The sum of the variation in the first alignment error, the variation in the second alignment error, and the variation in the difference between the first alignment error and the second alignment error is used as an index value. 30. The overlay accuracy evaluation method according to claim 29, wherein the alignment accuracy is evaluated. A reference that is a reference for superimposing a pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object and the pattern formed on the object prior to the target layer. An alignment condition optimization system that optimizes alignment conditions with a base pattern formed in a layer,
When the first pattern is formed on the target layer so as to overlap the base pattern formed on the reference layer on the object, the reference layer detected for alignment of the first pattern with respect to the base pattern A first detection result of at least some of the first marks formed with the base pattern and a second pattern on the target layer on which the first pattern is formed on the object. When forming, using a second detection result of at least some of the plurality of first marks detected for alignment of the second pattern with respect to the base pattern, and A position comprising an optimization device for optimizing the alignment condition of the pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object Align condition optimizing system. The optimization device includes:
A first alignment error of the first pattern with respect to the background pattern is obtained using the first detection result, and a second alignment of the second pattern with respect to the background pattern is determined using the second detection result. An error is obtained, and an alignment condition of a pattern formed on the target layer with respect to a base pattern formed on the reference layer on the object is optimized using the first and second alignment errors. 31. The alignment condition optimization system according to 31.   33. The alignment condition optimization system according to claim 32, wherein the optimization device calculates the first and second alignment errors using a plurality of model equations for determining the alignment error.   The optimization device includes at least one of a variation in the first alignment error and a variation in the second alignment error, a variation in a difference between the first alignment error and the second alignment error, 34. The alignment condition optimization system according to claim 32 or 33, wherein the alignment condition is optimized based on the information.   The optimization apparatus optimizes alignment conditions for aligning the first pattern with the base pattern based on the variation in the first alignment error, and determines the variation in the second alignment error. 35. The alignment condition optimization system according to claim 34, wherein alignment conditions for aligning the second pattern with the base pattern and the first pattern are optimized based on the variation in the difference.   35. The optimization apparatus optimizes the alignment condition using an index value as a sum of a variation in the first alignment error, a variation in the second alignment error, and a variation in the difference. 35. The alignment condition optimization system according to 35.   37. The optimization apparatus calculates the sum by adding weights determined for each of the first alignment error variation, the second alignment error variation, and the difference variation. The alignment condition optimization system described in 1.   38. The alignment condition optimization system according to claim 36 or 37, wherein the optimization apparatus extracts the alignment condition that gives a variation in the first alignment error equal to or less than a predetermined first threshold value.   The alignment condition optimization according to any one of claims 36 to 38, wherein the optimization apparatus extracts the alignment condition that gives a variation in the second alignment error that is equal to or less than a predetermined second threshold value. System.   The said optimization apparatus extracts the said alignment conditions which give the dispersion | variation in the said difference below a predetermined 3rd threshold value from the said extracted alignment conditions. The alignment condition optimization system described in 1.   The alignment condition optimization system according to any one of claims 38 to 40, wherein the optimization apparatus extracts the alignment condition that minimizes the index value from the extracted alignment conditions. .   The optimization apparatus uses, as the reference for optimization, the alignment condition when forming the first pattern and the alignment condition when forming the second pattern, out of the extracted alignment conditions. The alignment condition optimization system according to claim 41, wherein the alignment condition corresponding to an index value smaller than the corresponding index value is extracted.   The optimization device includes the first mark, a second mark formed on the first mark with the first pattern, and formed with the second pattern on the first and second marks. The alignment condition according to any one of claims 38 to 42, wherein an optimum condition is extracted from the extracted alignment conditions using a third detection result obtained by detecting the third mark. Optimization system.   The optimization apparatus evaluates the overlay accuracy of the base pattern, the first pattern, and the second pattern using the third detection result, and extracts the optimum condition that gives the best overlay accuracy. 43. The alignment condition optimization system according to 43.   45. The alignment condition optimization according to claim 44, wherein the optimization device evaluates the overlay accuracy of the base pattern, the first pattern, and the second pattern based on a sum of variations in overlay errors between the patterns. System.   46. The alignment condition optimization system according to claim 45, wherein the optimization apparatus obtains the sum in consideration of a weight determined for an overlay error between patterns.   47. The alignment condition optimization system according to any one of claims 31 to 46, wherein the alignment condition includes at least one of a condition regarding the exposure and a condition regarding detection of the first mark. The first mark is detected by imaging,
Each of the first and second detection results includes an imaging result of the first mark,
48. The alignment condition optimization system according to claim 47, wherein the alignment condition includes a processing condition for an imaging result of the first mark. A pattern formed on the target layer through a plurality of lithography processes including exposure and development on the target layer on the object, and a reference for overlaying the pattern formed on the object prior to the target layer An alignment condition optimization system that optimizes alignment conditions with a base pattern formed on a reference layer,
A first mark formed with the base pattern on the object; a second mark formed with the first pattern on the target layer upon the first exposure; A mark detection system for detecting a third mark formed together with a second pattern formed in the second exposure on the target layer over the second mark;
And an optimization device that optimizes the alignment condition of the pattern formed on the target layer with respect to the base pattern formed on the reference layer on the object, using the detection result of the mark detection system. Condition optimization system.   50. The optimization apparatus evaluates the overlay accuracy of the base pattern, the first pattern, and the second pattern using the detection result, and optimizes the alignment condition using the overlay accuracy. The alignment condition optimization system described in 1.   The alignment condition optimization according to claim 50, wherein the optimization apparatus evaluates the overlay accuracy of the base pattern, the first pattern, and the second pattern based on a sum of variations in overlay errors between the patterns. System.   52. The alignment condition optimization system according to claim 51, wherein the optimization device calculates the sum in consideration of a weight determined for an overlay error between the patterns.   53. The alignment condition optimization system according to any one of claims 49 to 52, wherein the alignment condition includes a condition related to the exposure. An exposure apparatus for forming a pattern by superimposing patterns on a plurality of layers on an object,
First and second patterns formed on the target layer by a first exposure and a second exposure on the target layer on the object, and a pattern formed on the object prior to the target layer 54. An exposure apparatus comprising the alignment condition optimization system according to any one of claims 31 to 53, wherein the alignment condition with the base pattern formed on a reference layer serving as a reference for superimposing the alignment is optimized.   The first and second exposures are performed on the target layer on the object by aligning the first and second patterns with respect to the base pattern formed on the object, thereby performing the first and second exposures. And forming two patterns on the target layer, and performing the alignment under the optimized alignment condition at least one of a first exposure and a second exposure of the target layer on the object. 54. The exposure apparatus according to 54. A pattern forming system that overlaps a base pattern already formed on an object and forms a pattern by overlapping a target layer with a lithography process including exposure and development a plurality of times.
First and second patterns formed on the target layer by a first exposure and a second exposure on the target layer on the object, and a pattern formed on the object prior to the target layer The alignment condition optimization system according to any one of claims 31 to 55, wherein the alignment condition with the base pattern formed on a reference layer serving as a reference for overlaying is optimized.
The first and second exposures are performed on the target layer on the object by aligning the first and second patterns with respect to the base pattern formed on the object, thereby performing the first and second exposures. An exposure apparatus that forms two patterns on the target layer and performs the alignment under the optimized alignment condition at least one of a first exposure and a second exposure of the target layer on the object And a pattern forming system. 57. A pattern formation system according to claim 56, wherein a mask layer is formed on the target layer on the object by exposure of the first pattern and the second pattern;
Processing the target layer using the mask layer;
A device manufacturing method including: Formed multiple times through a lithography process including a base pattern formed on a reference layer that is a reference for pattern superimposition prior to a target layer on an object, and exposure and development on the target layer superimposed on the base pattern. An overlay accuracy evaluation system for evaluating overlay accuracy with a pattern to be formed,
When the first pattern is formed over the base pattern formed on the reference layer on the object, the base layer is detected together with the base pattern detected for alignment of the first pattern with respect to the base pattern. When forming the second pattern on the target layer where the first pattern on the object and the first detection result of at least some of the formed first marks and the first pattern on the object are formed. And the second detection result of the at least some of the first marks detected for alignment of the second pattern with respect to the base pattern, and the first pattern and the second with respect to the base pattern An overlay accuracy evaluation system that evaluates overlay accuracy with patterns.   A first alignment error of the first pattern with respect to the background pattern is obtained using the first detection result, and a second alignment of the second pattern with respect to the background pattern is determined using the second detection result. 59. The overlay accuracy evaluation system according to claim 58, wherein an error is obtained and the overlay accuracy is evaluated using the first and second alignment errors.   60. The overlay accuracy evaluation system according to claim 59, wherein the first and second alignment errors are obtained using a plurality of models for obtaining the alignment error.   Based on at least one of the variation in the first alignment error and the variation in the second alignment error and the variation in the difference between the first alignment error and the second alignment error. The overlay accuracy evaluation system according to claim 59 or 60, wherein the alignment accuracy is evaluated. The sum of the variation in the first alignment error, the variation in the second alignment error, and the variation in the difference between the first alignment error and the second alignment error is used as an index value. 64. The overlay accuracy evaluation system according to claim 61, wherein the alignment accuracy is evaluated.

Images