JP2013254849A - Pattern formation optimization method and system, exposure method and device, detector, and device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize a formation position of a device pattern.SOLUTION: In a Spacer Process method for forming a fine pattern that exceeds a resolution limit of an exposure device by forming a resist pattern 33on wafer W by exposure, transferring the resist pattern 33to a hard mask layer 32, forming a spacer 34on a side wall of the hard mask pattern 32formed by the transfer, and finally removing the hard mask pattern 32, a device pattern formed on the wafer W is detected, and a formation condition of a resist pattern for adjusting at least one between line width and an interval of a spacer formed on a side wall of the resist pattern is calculated on the basis of the detection result. A formation position of the device pattern can be optimized by forming a resist pattern by exposure according to the formation condition.

Description

  The present invention relates to a pattern formation optimizing method and system, an exposure method and apparatus, and a device manufacturing method. More specifically, the first pattern is formed by exposure, and a spacer is formed on a side wall of the first pattern. Pattern formation optimization method and system for optimizing the formation position of the second pattern formed on the object by removing the first pattern, and reference layer on the object using the pattern formation optimization method and system An exposure method and apparatus for forming a first pattern on the target layer on the object by exposure, overlapping the underlying pattern formed on the object, and an interval between the first pattern and the second pattern using the pattern formation optimization system The present invention relates to a detection apparatus that measures at least one of line widths, and a device manufacturing method that uses the exposure method of the present invention.

  Electronic devices (microdevices) such as semiconductor elements and liquid crystal display elements are manufactured by hierarchically stacking device patterns (patterns) on a substrate using an exposure apparatus or the like. Conventionally, in order to appropriately manage overlay accuracy, for example, as disclosed in Patent Document 1, prior exposure to a test wafer prior to an actual process, measurement of overlay error and line width error of the exposure result, Adjustment of alignment related parameters, exposure amount, synchronization accuracy, and focus control related control system parameters in the exposure apparatus based on the measurement result is performed.

  On the other hand, in response to the miniaturization of patterns of semiconductor elements and the like, the exposure apparatus used in the lithography process shortens the exposure wavelength, increases the numerical aperture NA of the projection optical system in order to increase the resolving power, so-called Optimization of illumination conditions such as modified illumination and development of mask technologies such as phase shift reticles are being carried out. Recently, in order to substantially increase the numerical aperture NA while ensuring a wide focal depth, an exposure apparatus using an immersion method has been developed.

  Further, an exposure apparatus is formed by forming a resist pattern by exposure, transferring the resist pattern to a hard mask, forming a spacer on the side wall of the hard mask pattern formed thereby, and finally removing the hard mask pattern. A spacer process (Spacer Process) method has been proposed that forms a fine device pattern that exceeds the resolution limit. However, there is no appropriate overlay accuracy management method for this spacer process method, and the overlay accuracy has not been adequately managed yet.

US Patent Application Publication No. 2008/0294280

  According to the first aspect of the present invention, a first pattern is formed by exposure, a spacer is formed on a side wall of the first pattern, and the first pattern is removed to form a second pattern formed on the object. A pattern formation optimization method for optimizing a pattern formation position, wherein the second pattern formed on the object is detected, and formed on a sidewall of the first pattern based on the detection result. Obtaining a first pattern formation condition in order to adjust at least one of the spacer spacing and the line width.

  According to this, the formation condition of the first pattern for adjusting at least one of the line width and the interval of the spacer formed on the side wall of the first pattern is obtained based on the detection result of the second pattern. By forming the first pattern by exposure according to the formation conditions of the first pattern, the formation position of the second pattern can be optimized.

  From a second viewpoint, the present invention obtains the first pattern formation condition using the pattern formation optimization method of the present invention, and exposes the first pattern on the object according to the formation condition. Forming an exposure method.

  According to this, high overlay accuracy of the second pattern is realized by forming the first pattern on the object by exposure according to the first pattern formation condition obtained by using the pattern formation optimization method of the present invention. It becomes possible to do.

  From a third aspect, the present invention includes forming a mask on a target layer on an object using the exposure method of the present invention, and processing the target layer using the mask. It is a device manufacturing method.

  According to a fourth aspect of the present invention, a second pattern is formed on an object by forming a first pattern by exposure, forming a spacer on a side wall of the first pattern, and removing the first pattern. A pattern formation optimizing system for optimizing a pattern formation position, wherein a detection device that detects the second pattern formed on the object, and formed on a side wall of the first pattern based on the detection result And an optimization device for obtaining a formation condition of the first pattern in order to adjust at least one of an interval and a line width of the spacers.

  According to this, the formation condition of the first pattern for adjusting at least one of the line width and the interval of the spacer formed on the side wall of the first pattern is obtained based on the detection result of the second pattern. By forming the first pattern by exposure according to the formation conditions of the first pattern, the formation position of the second pattern can be optimized.

  According to a fifth aspect of the present invention, there is provided the pattern formation optimization system according to the present invention that obtains the formation condition of the first pattern, and exposure that forms the first pattern on the object by exposure according to the formation condition. Device.

  According to this, high overlay accuracy of the second pattern can be realized by forming the first pattern on the object by exposure in accordance with the first pattern formation conditions required by the pattern formation optimization system of the present invention. Is possible.

  From a sixth aspect, the present invention includes the pattern formation optimization system according to the present invention for obtaining the formation condition of the first pattern, and the line width of the first pattern formed on the object according to the formation condition And a detection device that measures at least one of the positions.

  According to a seventh aspect of the present invention, there is provided the pattern formation optimization system according to the present invention for obtaining a formation condition of the first pattern, and the second pattern formed on the object according to the formation condition is provided. This is a detection device that measures at least one of the interval and the line width.

  According to this, at least one of the interval and the line width of the first pattern or the second pattern formed on the object is accurately measured according to the formation condition of the first pattern obtained by the pattern formation optimization system of the present invention. can do.

It is a figure showing a schematic structure of a device manufacturing system concerning one embodiment of the present invention. It is a figure which shows an example of a schematic structure of the exposure apparatus of FIG. FIG. 3A is a diagram showing an example of an arrangement of shot areas on a wafer, and FIG. 3B is a diagram showing an example of the types and arrangement of wafer marks. It is a flowchart which shows the flow of the process in a device manufacturing process. FIG. 5A to FIG. 5J are diagrams for explaining the formation process of the pattern formed on the wafer, and are enlarged sectional views showing a part of one shot region on the wafer. It is. FIGS. 6A and 6B are enlarged cross-sectional views for explaining an example of a pattern formed on the wafer when a line width error occurs.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a schematic configuration of a device manufacturing system according to an embodiment. The device manufacturing system 1000 is a system constructed in a device manufacturing factory for processing a substrate, for example, a semiconductor wafer (hereinafter referred to as “wafer”) and manufacturing a micro device. As shown in FIG. 1, a device manufacturing system 1000 includes an exposure apparatus 100, a track 200 disposed adjacent to the exposure apparatus 100, an analysis apparatus 500, and a host computer (hereinafter abbreviated as “host”). 600) and a device manufacturing processing apparatus group 900. In FIG. 1, the bold arrows indicate the flow (movement) of the wafer, and the other solid arrows indicate the data flow.

  Here, the exposure apparatus 100 is a step-and-scan projection exposure apparatus (that is, a scanner). FIG. 2 shows a schematic configuration of the exposure apparatus 100. The exposure apparatus 100 includes an illumination system IOP, a reticle stage RST that holds a reticle R, a projection optical system PL, a wafer stage WST on which a wafer W is placed, a control system for these, and the like.

  The illumination system IOP includes a light source and an illumination optical system connected to the light source via a light transmission optical system. The illumination optical system includes, for example, an illumination uniformizing optical system including an optical integrator, a beam splitter, a reticle blind, and the like (all not shown) as disclosed in, for example, US Patent Application Publication No. 2003/0025890. . Illumination system IOP uses illumination light IL to illuminate a slit-like illumination area defined by a reticle blind on reticle R on which a circuit pattern or the like is drawn (a long and narrow rectangular shape extending in the X-axis direction (the direction perpendicular to the plane of FIG. 2)). Illuminate with almost uniform illumination. As the illumination light IL, for example, ArF excimer laser light (wavelength 193 nm) (or KrF excimer laser light (wavelength 248 nm)) is used.

  Reticle stage RST is arranged below illumination system IOP in FIG. 2 (on the −Z side). On reticle stage RST, reticle R on which a pattern is formed is fixed, for example, by vacuum suction. Here, reticle stage RST can be finely driven in a horizontal plane (XY plane) by a reticle stage drive system 22 including a linear motor and the like, and also has a scanning direction (here, the Y axis in the horizontal direction in FIG. 2). Driving at a scanning speed specified in a predetermined stroke range. Position information (including rotation information about the Z axis) of the reticle stage RST in the XY plane is, for example, about 0.25 nm by a reticle laser interferometer (hereinafter referred to as “reticle interferometer”) 16 via a movable mirror 15. Is always detected with a resolution of. Position information of reticle stage RST from reticle interferometer 16 is sent to main controller 50, which drives reticle stage RST via reticle stage drive system 22 based on the position information of reticle stage RST. (Control.

  Projection optical system PL is arranged below reticle stage RST in FIG. 2 (on the −Z side), and the direction of optical axis AX is the Z-axis direction. As the projection optical system PL, for example, a bilateral telecentric refraction system including a plurality of lens elements arranged at a predetermined interval along the Z-axis direction parallel to the optical axis AX is used. The projection magnification β of the projection optical system PL is, for example, ¼ (or ５). For this reason, when the reticle R is illuminated by the illumination light IL from the illumination system IOP, the illumination light IL that has passed through the reticle R passes through the projection optical system PL and is within the illumination area (illumination area) of the illumination light IL. A reduced image (partial inverted image) of the reticle R pattern is formed in an area (exposure area) conjugated to the illumination area on the wafer W coated with a photoresist (sensitive agent; hereinafter abbreviated as resist). (A latent image of the pattern is formed on the resist).

  The exposure apparatus 100 is provided with an imaging characteristic correction device for correcting imaging characteristics of the projection optical system PL, for example, various aberrations. This imaging characteristic correction apparatus corrects changes in the imaging characteristics of the projection optical system PL itself due to changes in atmospheric pressure, absorption of illumination light, etc. The projection image of the pattern of the reticle R is distorted in accordance with the distortion of the transferred pattern. Imaging characteristics of the projection optical system PL include spherical aberration (aberration at the imaging position), coma aberration (magnification aberration), astigmatism, field curvature, distortion aberration (distortion), and the like. The imaging characteristic correction device has a function of correcting these various aberrations.

  A plurality of lens elements (movable lenses) constituting a part of the projection optical system PL can be arbitrarily tilted with respect to a plane orthogonal to the optical axis AX and moved in a direction parallel to the optical axis AX. ing. Each movable lens is independently controlled by the image characteristic control unit 12.

  Wafer stage WST is arranged below projection optical system PL in FIG. 2 (on the −Z side). On wafer stage WST, wafer W is held by vacuum suction or the like via wafer holder 9.

  Wafer stage WST is driven with a predetermined stroke in the X-axis direction and Y-axis direction by wafer stage drive system 24 including a linear motor and the like, and also rotates in the Z-axis direction and the Z-axis rotation direction (θz direction). It is finely driven in a rotating direction (θx direction) around and a rotating direction around the Y axis (θy direction). That is, the wafer holder 9 can be tilted in any direction with respect to the best imaging plane of the projection optical system PL by the wafer stage drive system 24, and can be finely moved in the optical axis AX direction (Z-axis direction). It is configured to be rotatable around a Z axis parallel to the axis AX.

  Position information (including yawing (rotation in the θz direction) information) and tilt information (pitching (rotation in the θx direction) information and rolling (rotation in the θy direction) information) of the wafer stage WST in the XY plane are the wafer laser. An interferometer (hereinafter abbreviated as a wafer interferometer) 18 is constantly detected through a movable mirror 17 with a resolution of, for example, about 0.25 nm. The position information (or speed information) of wafer stage WST is sent to main controller 50, and main controller 50 determines the position of wafer stage WST in the XY plane (in the θz direction) based on the position information (or speed information). (Including rotation) is controlled via the wafer stage drive system 24.

  Further, a reference mark plate FM having a surface set substantially at the same height as the surface of wafer W is fixed to the upper surface of wafer stage WST. On the surface of the fiducial mark plate FM, a first fiducial mark for reticle alignment and a second fiducial mark for baseline measurement of the alignment system 8 described later are formed in a predetermined positional relationship.

On the side surface of the projection optical system PL, alignment marks (wafer marks) (MX _p , MY _p ) and overlay error measurement marks MO (see FIG. 3B) attached to each shot area on the wafer W, and An off-axis alignment system 8 is provided for detecting a second reference mark on the reference mark plate FM. The alignment system 8 uses an internal optical system to illuminate the wafer surface including the wafer mark (MX _p , MY _p ) or the overlay error measurement mark MO, and reflects the reflected light from the wafer surface to the optical system. Is guided to an alignment sensor provided inside, and a signal corresponding to the reflected light is photoelectrically detected using the alignment sensor. The detected signal has, for example, a waveform corresponding to the unevenness or reflectance distribution of the wafer surface. In the alignment system, a waveform (mark waveform) corresponding to the mark is extracted from the detected waveform data, and the position coordinate of the mark waveform in the detection field of the alignment sensor is detected based on the extraction result. In the alignment system, the position of the wafer mark (MX _p , MY _p ) and the overlay error measurement mark MO in the XY coordinate system based on the position coordinates of the detected mark waveform and the position coordinates of the detection visual field itself of the alignment sensor. Is calculated. The detection result of the alignment system 8 is sent to the main controller 50 via an alignment signal processing system (not shown).

  Further, in the vicinity of the lower end portion of the projection optical system PL, position information (surface position information) regarding the Z-axis direction of the surface of the wafer W at a plurality of detection points in the exposure area and in the vicinity thereof is detected. An oblique incidence type multi-point focal position detection system (13, 14) disclosed in the specification of No. 5,448,332 and the like is provided. The multipoint focal position detection system includes an irradiation optical system 13 that emits an imaged light beam obliquely with respect to the optical axis AX toward the best image formation plane of the projection optical system PL, and a reflected light beam from the surface of the wafer W as a slit. And a light receiving optical system 14 for receiving light through The wafer surface position information detected by the multipoint focus position detection system (13, 14) is supplied to the main controller 50 for focus / leveling control of the wafer W.

  In addition, the exposure apparatus 100 is provided with a pair of reticle alignment systems (not shown) as disclosed in, for example, US Pat. No. 5,646,413 above the reticle stage RST. The reticle alignment system is composed of a TTR (Through The Reticle) alignment system using light having the same wavelength as the illumination light IL. The detection signal of the reticle alignment system is supplied to main controller 50 via an alignment signal processing system (not shown).

  The main controller 50 is composed of, for example, a microcomputer (or workstation), and comprehensively controls each part of the exposure apparatus 100.

  Next, the operation of the exposure process in the exposure apparatus 100 will be briefly described.

  Prior to exposure, main controller 50 causes wafer W to be loaded onto wafer holder 9 using a wafer transfer system (not shown), reticle alignment, baseline measurement of alignment system 8, and wafer alignment (for example, EGA (described later) Preparation work such as Enhanced Global Alignment) or multi-point EGA within shot) is performed. The above reticle alignment, baseline measurement, and the like are disclosed in detail in the aforementioned US Pat. No. 5,646,413.

  Main controller 50 sequentially performs reticle exposure on all shot areas on wafer W based on the results of reticle alignment and baseline measurement, and the results of wafer alignment (which will be described later). The pattern is transferred.

  In scanning exposure for each shot area on wafer W, main controller 50 monitors reticle stage RST and wafer stage WST while monitoring measurement information (position information) by reticle interferometer 16 and wafer interferometer 18. Move to scan start position (acceleration start position). Then, main controller 50 relatively drives both stages RST and WST in the Y-axis direction, but in opposite directions. Here, when both stages RST and WST reach their respective target speeds, the pattern area of reticle R starts to be illuminated by illumination light IL, and scanning exposure is started.

  Main controller 50 determines that the speed Vr of reticle stage RST in the Y-axis direction and the movement speed Vw of wafer stage WST in the Y-axis direction at a speed ratio corresponding to the projection magnification of projection optical system PL, particularly during the above-described scanning exposure. The reticle stage RST and wafer stage WST are synchronously controlled so as to be maintained. At this time, main controller 50 adjusts the synchronous drive of both stages RST and WST, or drives the movable lens via the imaging characteristic correction device, so that the projection image of the pattern on reticle R onto wafer W is displayed. Correct distortion.

  Then, different areas of the pattern area of the reticle R are sequentially illuminated with the illumination light IL, and the illumination of the entire pattern area is completed, thereby completing the scanning exposure of the first shot area on the wafer W. Thereby, the circuit pattern of the reticle R is reduced and transferred to the first shot area via the projection optical system PL.

  When the scanning exposure for the first shot area is completed, main controller 50 moves (steps) wafer stage WST to the scanning start position (acceleration start position) for the next second shot area. Then, similarly to the above, scanning exposure is performed on the second shot area. Thereafter, the same operation is performed for the third shot area and thereafter. In this manner, the stepping operation between the shot areas and the scanning exposure operation for the shot areas are repeated, and the pattern of the reticle R is transferred to all the shot areas on the wafer W by the step-and-scan method.

Next, the wafer alignment according to the present embodiment will be further described. FIG. 3A shows an example of a wafer W (a substrate used for device manufacture) to be exposed in the exposure apparatus 100. As shown in FIG. 3A, on the wafer W, a plurality of shot areas SA _p in which device patterns are formed are already formed by exposure to the previous layer. In each shot area SA _p , as shown in FIG. 3B, alignment marks (wafer marks) transferred at the time of exposure of a reference layer (also referred to as an underlayer, for example, a front layer) serving as a reference for overlaying are provided. ) (MX _p , MY _p ). The wafer marks (MX _p , MY _p ) are marks whose position information can be detected from their shapes and the like. For example, in FIG. 3B, the wafer marks (MX _p , MY _p ) are shown as line and space marks. In addition to the shape of the wafer mark, a box mark, a cross mark, or the like may be employed.

In exposure apparatus 100, with respect to the shot area SA _p on this the wafer W, a device pattern on the reticle R, it is necessary to expose by accurately superimposed. In order to realize accurate overlay, it is necessary to accurately grasp the position of each shot area SA _p on the wafer W. Wafer marks (MX _p , MY _p ) are provided to grasp the position of each shot area SA _p (for example, the position of its center C _p in FIG. 3B). Since the wafer mark (MX _p , MY _p ) is transferred and formed together with the device pattern of the shot area SA _p to which the wafer mark (MX _p , MY _p ) is attached, the wafer mark (MX _p , MY _p ) on the wafer W and the device pattern If the position of the wafer mark (MX _p , MY _p ) is known, the center position C _p of the shot area can be recognized.

Further, as shown in FIG. 3 (B), within each shot area SA _p, error measuring mark MO overlapped with the device pattern during exposure of the reference layer is transferred are formed. Here, as an example, four overlay error measuring mark MO has been the one located at the four corners of each shot area SA _p.

In exposure apparatus 100, in order to perform accurate superposition of the device pattern may be measure the positional information of all shot areas SA _p on the wafer, but then, there is a possibility that the effect on throughput exits. Therefore, in exposure apparatus 100, limit the alignment marks to be actually measured, the position of the alignment mark measured, global alignment technique of statistically estimating the sequence of the shot areas SA _p on the wafer has been adopted. In the exposure apparatus 100, as this global alignment, the deviation of the actual shot area arrangement from the designed shot area arrangement is parallel to the X axis and Y axis, respectively, for example, a coordinate axis (Wx , represented by a polynomial of Wy) and / or such coordinate axes of the center of the shot area SA _p origin (Sx, Sy), determine the appropriate coefficients in the polynomial by performing the statistical calculation, the wafer alignment of the so-called EGA method It has been adopted. The wafer alignment by the EGA method, first, some selected shot areas SA _p which measures the alignment mark. The selected shot area is called a sample shot. Main controller 50 uses alignment system 8 to measure the position of sample marks (wafer marks MX _p and MY _p and overlay error measurement mark MO) attached to the sample shot. Such a measurement operation is hereinafter referred to as EGA measurement.

The wafer alignment by the EGA method, the results of the EGA measurement, i.e. by statistical calculation based on the position information of several sample marks, estimates the correction amount of the XY coordinates of each shot area SA _p. Such an operation is hereinafter referred to as an EGA operation. The EGA wafer alignment is disclosed in detail in, for example, US Pat. No. 4,780,617 and US Pat. No. 6,876,946. The latter method disclosed in US Pat. No. 6,876,946 and the like is also referred to as in-shot multipoint EGA. Here, the multipoint EGA in the shot uses the least square method disclosed in, for example, the above-mentioned US Pat. No. 6,876,946 using the position detection data of a plurality of wafer alignment marks in the shot area. It means an alignment method of obtaining the and shot area SA _p linear components of the deformation of itself (the linear component of the array of shot areas SA _p) sequence coordinates of all shot areas SA _p on the wafer W using a statistical technique.

  The XY correction amount at the position of each shot area obtained by the above EGA calculation is referred to as an EGA correction amount. Since the coefficient of the polynomial obtained by the EGA wafer alignment is obtained by the least square method, a deviation remains between the measured value of the mark position and the mark position corrected by the EGA correction amount. This deviation is called EGA residual error (or residual). Of course, it is desirable that the EGA residual error be smaller from the viewpoint of overlay accuracy.

One of the means for reducing the EGA residual error is higher order EGA polynomial model. For example, the EGA polynomial model, the scaling of the wafer W when with respect to the center of the linear component (wafer W of the arrangement of shot areas SA _p, rotation (X-axis of the array of shot areas corresponding orthogonal components of corresponding Y-axis rotation in consideration of the degrees), the components of the offset), the shot area SA _p linear components of the deformation of itself (the shot area SA _p scaling center of the shot area SA _p on the basis of the corresponding X-axis of rotation (shot area , Rotation considering also the orthogonality of the component corresponding to the Y axis), and each component of the offset), not the linear expression of (Wx, Wy) or (Sx, Sy), but of the arrangement of the shot area SA _p The EGA residual error is more effective when the quadratic expression (Wx, Wy) considering the second order component or the third order formula (Wx, Wy) considering the third order component of the shot region array is used. Small to. In general, the higher the EGA polynomial model, the smaller the overall EGA residual error, but care must be taken not to overcorrect. In order to increase the order of the EGA polynomial model, it is necessary to increase the number of sample marks accordingly. Of course, it is possible to adopt a model that also takes into consideration higher-order components of (Sx, Sy).

Further, when the measurement result of some sample marks is significantly deviated from the actual shot region arrangement, the overall residual tends to increase. Therefore, it is desirable to reject the measurement result of the position of the sample mark so that it is not used for the EGA calculation. That is, some of the position information of the sample marks measured by the EGA measurement, so as not to use the EGA calculation, it is possible to continue to improve the position estimation accuracy of the shot area SA _p. Thus, the selection of the number and / or arrangement of sample marks is an important factor for EGA wafer alignment.

  Returning to FIG. 1, in the track 200, a composite measurement / inspection instrument 120 capable of performing various measurement / inspections on the wafer before and after the exposure of the wafer by the exposure apparatus 100, and a resist ( A coater / developer (hereinafter abbreviated as C / D) 110 is provided for applying the photosensitive agent) and developing the exposed wafer.

  The measurement / inspection instrument 120 can operate independently of the exposure apparatus 100 and the C / D 110. Further, the measurement / inspection instrument 120 can output the measurement / inspection results to the outside via a communication network in the system. In the present embodiment, the measurement / inspection instrument 120 performs a post-measurement inspection that is mainly a measurement inspection after exposure.

In the post-measurement inspection of the measurement / inspection instrument 120, in addition to the defect / foreign particle inspection on the wafer W, the overlay error of the device pattern on the wafer W after exposure (post-event) transferred by the exposure apparatus 100 and developed by the C / D 110. Measure the alignment error, line width error, etc. In a predetermined area on the reticle R (here, a pattern area in which a device pattern is formed), a plurality of marks for measuring these errors (for example, the device pattern at the time of exposure) by the exposure apparatus 100 (for example, , Overlay error measurement marks MO ₀ , MO ₁ , MO ₂ ) are formed. The measurement / inspection instrument 120 measures the positional relationship (relative displacement) between the overlay error measurement marks of each layer, and measures the overlay error at each point in the shot area on the wafer W, which is the transfer area of the device pattern. To do. From this measurement result, it is possible to obtain the overlay error distribution of the pattern elements in the shot area.

  The analysis apparatus 500 is an apparatus that operates independently of the exposure apparatus 100, the C / D 110, and the measurement / inspection instrument 120. The analysis apparatus 500 collects various data (for example, processing data of the apparatus) from various apparatuses, and analyzes data relating to a series of processes for the wafer W. For example, the analysis apparatus 500 performs a simulation on the wafer alignment of the exposure apparatus 100 based on the measurement results of the exposure apparatus 100 and the measurement / inspection instrument 120. As hardware for realizing such an analysis apparatus 500, for example, a personal computer (hereinafter, abbreviated as “PC” as appropriate) can be employed. In this case, the analysis process is realized by executing an analysis program executed by a CPU (not shown) of the analysis apparatus 500. This analysis program is recorded on a medium (information recording medium) such as a CD-ROM, and is executed in a state where it is installed on the PC from the medium.

  Incidentally, the exposure apparatus 100, the C / D 110, and the measurement / inspection instrument 120 are connected in-line to each other. Here, the in-line connection means that the apparatuses and the processing units in each apparatus are connected via a transfer apparatus that automatically transfers the wafer W such as a robot arm and / or a slider. By the in-line connection, the transfer time of the wafer W between the exposure apparatus 100 and the C / D 110 can be remarkably shortened.

  The exposure apparatus 100, the C / D 110, and the measurement / inspection instrument 120 connected in-line can be regarded as one substrate processing apparatus (100, 110, 120) as a unit. The substrate processing apparatus (100, 110, 120) has an application process for applying a sensitive agent such as a resist to the wafer W, and an exposure process for transferring a mask or reticle pattern onto the wafer W to which the sensitive agent has been applied. In addition, a developing process for developing the wafer after the exposure process is performed.

  In the device manufacturing system 1000, a plurality of exposure apparatuses 100, C / Ds 110, and measurement / inspection instruments 120 are provided. Each substrate processing apparatus (100, 110, 120) and device manufacturing processing apparatus group 900 is installed in a clean room in which temperature and humidity are controlled. In addition, data communication can be performed between devices via a predetermined communication network (for example, LAN: Local Area Network). This communication network is a so-called intranet communication network provided for a customer's factory, business office or company.

  In the substrate processing apparatus (100, 110, 120), a plurality of wafers (for example, 25 or 50) are processed as one unit (referred to as a lot). In the device manufacturing system 1000, wafers are processed and commercialized using one lot as a basic unit.

  In this device manufacturing system 1000, the measurement / inspection instrument 120 is placed in the track 200 and connected inline with the exposure apparatus 100 and the C / D 110. However, the measurement / inspection instrument 120 is disposed outside the track 200, Adjacent inline connection may be used, or the exposure apparatus 100 and C / D 110 may be configured offline.

  The device manufacturing system 1000 includes a CVD (Chemical Vapor Deposition) apparatus 910, an etching apparatus 920, a CMP (Chemical Mechanical Polishing) apparatus 930, an oxidation / ion implantation apparatus 940, and the like as the device manufacturing processing apparatus group 900. The CVD apparatus 910 is an apparatus that generates a thin film on a wafer. The etching apparatus 920 is an apparatus that performs etching on the developed wafer. In this embodiment, the etching apparatus 920 is provided with an ashing apparatus that removes resist and the like. The CMP apparatus 930 is a polishing apparatus that planarizes the surface of a wafer by chemical mechanical polishing. The oxidation / ion implantation apparatus 940 is an apparatus for forming an oxide film on the surface of the wafer or implanting impurities into a predetermined position on the wafer. Similarly to the exposure apparatus 100, the CVD apparatus 910, the etching apparatus 920, the CMP apparatus 930, and the oxidation / ion implantation apparatus 940 are also provided with a transfer path for enabling transfer of wafers between them. The device manufacturing processing apparatus group 900 includes various apparatuses that perform dicing processing, packaging processing, bonding processing, and the like, although not shown.

  The host 600 manages and manages the entire device manufacturing system 1000. Therefore, the host 600 controls and manages the exposure process performed in the exposure apparatus 100 and manages the scheduling of the exposure apparatus 100. A management controller for the exposure apparatus 100 may be provided separately from the host 600.

  Next, a device manufacturing process in the device manufacturing system 1000 will be described with reference to FIGS. 4 and 5A to 5J.

  FIG. 4 shows the flow of processing in the device manufacturing process. The processing flow in the device manufacturing process in the device manufacturing system 1000 is scheduled and managed by the host 600. The wafers W are processed in units of lots, but FIG. 4 shows a series of processes for one wafer W. Actually, a series of processing shown in FIG. 4 is repeated for each wafer in lot units. 5A to 5J are enlarged cross-sectional views of a part of one shot area on the wafer W. FIG.

[Film formation]
First, as a film formation process, a CVD apparatus 910 generates (deposits) a target layer 31 made of an interlayer insulating film such as an organic polymer on the wafer W as shown in FIG. On the target layer 31, a hard mask layer 32 made of ceramics such as a silicon oxide film or a silicon nitride film and having different reactivity to etching with both the target layer 31 and the resist is laminated. Instead of using the hard mask layer 32, a bi-layer (two-layer) resist can be used.

[Resist coating]
Next, the wafer W on which the target layer 31 and the hard mask layer 32 are formed is transferred to the C / D 110, and the surface (hard mask layer) of the wafer W is transferred to the C / D 110 as shown in FIG. A resist is applied to the upper surface 32) (the resist layer 33 is laminated). Here, as an example, a positive resist is used.

[Exposure processing]
Next, wafer W on which resist layer 33 is formed is transferred to exposure apparatus 100 and loaded onto wafer stage WST in exposure apparatus 100. Then, the exposure apparatus 100 performs an exposure process on the wafer W. The main controller 50 performs wafer alignment (EGA measurement) on the wafer W using the alignment system 8, and performs a step-and-scan exposure operation based on the result, so that an image of the pattern on the reticle R is obtained. Transferred to each shot area on the wafer W. Here, the exposure apparatus 100 controls the exposure line width using the above-described imaging characteristic correction apparatus or the like according to a line width correction map described later. As a result, the exposed portion of the resist (the portion irradiated with light) increases the solubility in the developer (causes such a change), and as a result, as shown in FIG. a latent image having a line portion 33 ₂ formed of a portion not exposed to the layer 33 is formed.

[Development processing]
Next, the exposed wafer W is transferred to the C / D 110, and the wafer W (resist layer 33) is developed by the C / D 110. After development, as shown in FIG. 5 (B), the wafer W resist image of (hard mask layer 32) line portion 33 ₂ on (hereinafter, the resist image 33 using the resist image by using a line portion the same reference numerals ₂ ).

[Etching treatment]
Next, the wafer W is transferred to the etching apparatus 920, and a resist slimming process and an etching process subsequent thereto are performed in the etching apparatus 920. Resist slimming treatment, the etching time, by setting so that the resist image 33 ₂ of the width _{P 2} is a resist image 33 ₁ of the width _P 1 shown in FIG. 5 (C) (= S) , a resist image 33 ₂ This is an etching process. As a result, a resist pattern in which resist images 33 ₁ having a width P ₁ are arranged in the X-axis direction is formed on the hard mask layer 32.

Then, the etching of the hard mask layer 32 is performed using the resist image ₃₃₁ as a mask. After the etching, as shown in FIG. 5D, a hard mask pattern 32 _{1 in} which hard mask portions having a width P ₁ are arranged in the X-axis direction is obtained. Thereafter, the resist layer 33 (resist image 33 ₁ ) is peeled off from the wafer W by an ashing device (not shown) as shown in FIG.

[Silicon oxide film deposition]
Next, as shown in FIG. 5 (F), the wafer W hard mask pattern 32 ₁ is formed on the target layer 31 is conveyed to a CVD apparatus 910, in the CVD apparatus 910, the wafer W surface (hard mask A silicon oxide film (SiO ₂ film) 34 is laminated on the pattern 32 ₁ by the CVD method.

[Etching process and hard mask removal]
Then, the wafer W is transported to the etching apparatus 920, an etching process is performed in the etching apparatus 920, as shown in FIG. 5 (G), the hard mask pattern 32 ₁ and on the hard mask pattern 32 between ₁ (space portion ) SiO ₂ film 34 is removed. As a result, the spacer 34 ₁ is formed on the side wall of the hard mask pattern 32 ₁ . Further, by removing the hard mask pattern 32 _1, as shown in FIG. 5 (H), the spacers 34 ₁ of width L on the target layer 31 are arranged at a pitch P (distance S) in the X-axis direction A pattern is formed.

[Etching treatment and mask removal]
Then, the wafer W is conveyed into the etching apparatus 920, in the etching apparatus 920, as shown in FIG. 5 (I), the etching of the target layer 31 is performed using spacer 34 ₁ as a mask. Pattern after etching, it is removed the mask (spacer 34 _1), which are arranged depicted As the target portion 31 ₁ of width L on the wafer W in the X-axis direction at a pitch P (distance S) in FIG. 5 (J) Is obtained.

[Measurement inspection process]
Then, the conveyed target portion 31 ₁ (referred to as a base pattern or spacer pattern) pattern with a line unit wafer W is formed within the measurement test instrument 120, the measurement test instrument 120, the measurement inspection processing for the wafer W is Done. That is, the position of the alignment mark (wafer mark) (MX _p , MY _p ) attached to the base pattern formed on the target layer in the wafer surface is detected. In response to a transfer request from the analysis device 500, the detection result of the measurement / inspection instrument 120 is sent to the analysis device 500.

[Analysis processing]
Next, based on the detection result of the alignment marks (wafer marks) (MX _p , MY _p ) sent from the measurement / inspection instrument 120 by the analysis apparatus 500, the underlying pattern formed on the wafer W is applied to the underlying pattern. The wafer W (hard mask layer 32) is subjected to the next exposure process (including the subsequent development process and etching process) so that the alignment error of the pattern formed on the next target layer is minimized by repeating the above steps. ) The optimum line width condition of the resist pattern formed on the surface is obtained. Here, the line width condition is obtained as a variation ΔCD _{0 with} respect to the line width determined by design.

  Normally, the exposure apparatus optimizes the alignment and exposure line width control parameters so that the evaluation scale E given by the following equation is minimized.

E = (EGA residual _{error) × W 1 + (ΔCD 0} /2) × W 2 ... (1)
Here, as described above, (EGA residual error) is an EGA correction amount (XY correction amount at the position of each shot area) obtained by EGA calculation from the detection result of the alignment mark (wafer mark) (MX _p , MY _p ). The average absolute value of the number of measurement marks with respect to the deviation between the mark position corrected by the above and the mark actual measurement position is + 3σ. σ indicates variation (standard deviation). (ΔCD _0/2), the the absolute value + 3 [sigma] of the average measurement pattern a few minutes for the half of the deviation of the line width design value and the line width measured value of the first pattern. σ indicates variation (standard deviation). W ₁ and W ₂ are weighting factors determined according to the optimization levels of the alignment correction control and the line width correction control, respectively, and are usually set to W ₁ = W ₂ = 1. That is, by adjusting the exposure position and the line width of the resist pattern (exposure line width), the spacer pattern formed in the next target layer is aligned with the base pattern.

Laminating a result of the subsequent etching of the SiO ₂ film 34, when there is no wafer surface variations of the laminated and etching properties of the SiO ₂ film, as described above, the target portion 31 ₁ of width L on the wafer W pitch P Thus, an ideal pattern arranged in the X-axis direction can be obtained. However, in the case of the spacer process method, the line width accuracy of the spacer pattern depends on the pattern formation process. For example, as shown in FIG. 6 (A), SiO ₂ wafer surface variations of the laminated and etching characteristics of the film occurs and the line width of the spacers 34 ₁ [Delta] CD ₁ deviates from the line width L of the design, Fig. 6 As shown in (B), the spacer 34 ₁ interval is narrowed from the designed interval S (see FIG. 5H) to the interval S ′ = S−2ΔCD ₁ .

In such a case, in the measurement process, the measurement inspector 120 further measures the in-wafer variation ΔCD _{1 of} the spacer pattern (or the base pattern). The measurement result is sent to the analyzer 500 together with the alignment mark detection result by the measurement / inspection instrument 120. The analysis apparatus 500 optimizes the evaluation scale E ′ given by the following equation to be minimum, and obtains the line width condition ΔCD ₀ . After adjusting the wafer in-plane variation ΔCD ₁ , ΔCD ₀ may be optimized for the variation in which ΔCD ₁ could not be adjusted. The optimization of the evaluation scale E ′ may be performed for each shot in the wafer, for each shot in the wafer, and for each region in the shot.

E ′ = (EGA residual error) × W ₁ + ((ΔCD ₀ + ΔCD ₁ ) / 2) × W ₂ (2)
Here, as described above, (EGA residual error) is an EGA correction amount (XY correction amount at the position of each shot area) obtained by EGA calculation from the detection result of the alignment mark (wafer mark) (MX _p , MY _p ). The average absolute value of the number of measurement marks with respect to the deviation between the mark position corrected by the above and the mark actual measurement position + 3σ. σ indicates variation (standard deviation). ((ΔCD ₀ + ΔCD ₁ ) / 2) is the difference between the line width design value of the first pattern and the line width measurement value ΔCD ₀ and the line width design value and line width measurement value of the second pattern (spacer pattern). The average absolute value of the number of measurement patterns with respect to ½ of the sum of the deviation ΔCD ₁ + 3σ. σ indicates variation (standard deviation). W ₁ and W ₂ are weighting factors determined according to the optimization levels of the alignment correction control and the line width correction control, respectively, and are usually set to W ₁ = W ₂ = 1. When the SiO ₂ film stack and the etching characteristics vary in the wafer surface and the interval of the second pattern (spacer pattern) becomes 2 × ΔCD ₁ narrower (wider), that is, the line of the second pattern (spacer pattern) When the deviation from the width design value becomes larger (thinner) by ΔCD _1, when the exposure apparatus 100 exposes the wafer W, the line width is controlled to the deviation ΔCD ₀ from the line width design value of the first pattern. , ΔCD ₁ minute (thick), (ΔCD ₀ + ΔCD ₁ ) / 2 = 0, and the center position of the spacer pattern in which the line width varies can be adjusted to the design position. Thereby, even if the line width of the spacer pattern varies, the interval between the spacer patterns can be made uniform, which can contribute to the improvement of the yield. However, an upper limit value and a lower limit value of deviation are set for ΔCD ₀ and ΔCD ₁ , respectively.

The line width condition ΔCD ₀ can be obtained in common for all shot areas, individually for each shot, or individually for each area in a shot. The obtained line width condition ΔCD ₀ is fed back to the exposure apparatus 100 as a line width correction map for each shot, for example. The exposure apparatus 100 controls the exposure line width according to the line width correction map. Here, not the line width correction map but the variation in the wafer plane is fitted with a high-order polynomial (3) for each shot center position (Xs, Ys) in the wafer coordinate system, and each correction coefficient C in this high-order polynomial is May be fed back to the exposure apparatus 100. Equation (3) below shows a calculation model when the fitting order is 7th.

[Impurity diffusion, aluminum vapor deposition wiring processing]
In parallel with or subsequent to the analysis process, impurity diffusion to the etched wafer W, aluminum vapor deposition wiring process, film formation by the CVD apparatus 910, planarization by the CMP apparatus 930, oxidation / ion implantation apparatus 940 Ion implantation is performed as necessary. Thereby, the patterning process for the target layer 31 of the wafer W is completed.

  Next, the host 600 determines whether all the processes have been completed and all the patterns have been formed on the wafer W. If this determination is denied, the process returns to the film forming process, and if affirmed, the process proceeds to the next process. As described above, a series of patterning processes are repeatedly executed for the number of steps, whereby the device patterns are stacked on the wafer W to form semiconductor devices.

  After the repetition process is completed, the probing process and the repair process are executed in the device manufacturing processing apparatus group 900. When a defect is detected in the probing process, for example, a process of replacing with a redundant circuit is performed in the repair process. The analysis apparatus 500 can also send information such as the detected location where the overlay abnormality has occurred to an apparatus that performs the probing process and the repair process. In the inspection apparatus (not shown), the portion where the line width abnormality has occurred on the wafer W can be excluded from the processing target for the probing process and the repair process in units of chips. Thereafter, dicing processing, packaging processing, and bonding processing are executed, and a product chip is finally completed.

  As described above in detail, in the device manufacturing system 1000 according to the present embodiment, a resist pattern is formed on the wafer W by exposure using the exposure apparatus 100, and the resist pattern is transferred to a hard mask. In a spacer process (Spacer Process) method in which a fine device pattern exceeding the resolution limit of an exposure apparatus is formed by forming a spacer on the side wall of the hard mask pattern and finally removing the hard mask pattern. The device pattern formed above is detected, and based on the detection result, a resist pattern forming condition for adjusting at least one of the line width and interval of the spacer formed on the side wall of the resist pattern is required. By forming a resist pattern by exposure according to the resist pattern forming conditions, it is possible to optimize the position where the device pattern is formed.

  Further, in the device manufacturing system 1000 of the present embodiment, it is possible to realize high overlay accuracy of the device pattern with respect to the base pattern by forming the resist pattern on the wafer W by exposure according to the resist pattern formation conditions described above. It becomes.

  In the device manufacturing system 1000 of this embodiment, the in-plane variation (line width error) of the base pattern is measured, and using the result, the alignment of the pattern formed on the next target layer is optimized. As described above, the line width condition of the resist pattern formed on the wafer W (hard mask layer 32) is determined by the next exposure process (including the subsequent development process and etching process). Accordingly, it is possible to realize high overlay accuracy of the target layer device pattern with respect to the base pattern and high alignment accuracy of the base pattern and the device pattern.

  In the device manufacturing process in the device manufacturing system 1000 of the present embodiment, the line width condition may be obtained and updated each time the wafers W in the lot are processed or each time a plurality of wafers W are processed. . Accordingly, it is possible to efficiently realize high overlay accuracy of the target layer device pattern with respect to the base pattern and high alignment accuracy between the base pattern and the device pattern.

Further, in the equation (1) or (2) Scale E or E given by ', (EGA residual error), and the line width error (([Delta] CD _0/2), or, ([Delta] CD ₀ + [Delta] CD ₁₎ / 2) is the absolute value of the average + 3σ, but in addition to this, the absolute value of the average, the absolute value of the sum, the absolute value of the average + variation, or the absolute value of the sum + variation or variation Also good. Here, as the variation, in addition to 3σ (three times the standard deviation), any integer multiple of σ (standard deviation) may be used.

  Further, in the device manufacturing process in the device manufacturing system 1000 of the present embodiment, the process wafer is used to detect the alignment mark attached to the device pattern, and the line width of the device pattern is measured. Not only, but especially when processing the first wafer in a lot, the alignment mark formed by the test exposure using the test wafer is detected, and the line width of the pattern formed by the test exposure is measured. Also good.

  In the device manufacturing system 1000, the analysis apparatus 500 is a separate apparatus independent of various device manufacturing processing apparatuses, but the present invention is not limited to this. For example, any device manufacturing processing apparatus in the system may of course have the analysis function of the analysis apparatus 500. For example, the main controller 50, the measurement / inspection instrument 120, or the host 600 of the exposure apparatus 100 may be provided with analysis functions such as the above-described EGA optimization simulation and overlay optimization simulation.

  Further, according to the present embodiment, the analysis device 500 is a computer, and the analysis function is realized by a program that causes the computer to execute the analysis function. Since this program is downloaded from the Internet or installed from a state recorded on an information recording medium such as a CD-ROM, the analysis function itself can be easily added, changed, or modified.

  In the present embodiment, the exposure apparatus 100 is a step-and-scan type exposure apparatus, but is not limited thereto, and may be a step-and-repeat type or other type of exposure apparatus. As represented by this, the various apparatuses are not limited to those types. The present invention is not limited to a semiconductor manufacturing process, and can be applied to a manufacturing process of a display including a liquid crystal display element. In addition to the process of transferring the device pattern onto the glass plate, the manufacturing process of the thin film magnetic head, and the manufacturing process of the imaging device (CCD, etc.), micromachine, organic EL, DNA chip, etc. Of course, the present invention can be applied to management.

  In the above embodiment, the analysis apparatus 500 is a personal computer, for example. That is, the analysis processing in the analysis apparatus 500 is realized by executing an analysis program on a PC. As described above, the analysis program may be installable on the PC via the medium as described above, or may be downloaded to the PC via the Internet or the like. Of course, the analysis apparatus 500 may be configured by hardware.

100 ... exposure apparatus, 110 ... C / D, 120 ... measuring test (detection device), 500 ... analysis device, 900 ... device manufacturing processing apparatus group, 1000 ... device manufacturing system, W ... wafer, MX _p, MY _p ... Alignment mark (wafer mark).

Claims (19)

The first pattern is formed by exposure, the spacer is formed on the side wall of the first pattern, and the first pattern is removed to optimize the formation position of the second pattern formed on the object. A method of
Detecting the second pattern formed on the object;
Determining a formation condition of the first pattern in order to adjust at least one of an interval and a line width of the spacer formed on the side wall of the first pattern based on the detection result. Method. The second pattern includes a line and space pattern,
The pattern formation optimization method according to claim 1, wherein in the detection, at least one of an interval and a line width of the second pattern is detected. In the detection, a plurality of marks formed together with the second pattern are further detected,
3. The method according to claim 1, wherein in the obtaining, an alignment error of the second pattern is obtained using detection results of the plurality of marks, and a formation condition of the first pattern is obtained further based on the alignment error. The pattern formation optimization method as described.   3. The pattern formation optimization method according to claim 1, wherein an alignment error at the time of the first pattern exposure is obtained, and a formation condition of the first pattern is obtained based on the alignment error.   The pattern formation optimization method according to claim 1, wherein the first pattern formation condition includes at least one of a line width and a position.   6. The determination according to claim 1, wherein in the determination, the formation condition of the first pattern is determined for each shot region on the object on which the second pattern is formed or for each region in the shot. The pattern formation optimizing method described in 1. Using the pattern formation optimization method according to any one of claims 1 to 6, obtaining the formation conditions of the first pattern;
Forming the first pattern on the object by exposure according to the formation conditions;
An exposure method comprising: In the forming, the first pattern is sequentially formed on a plurality of objects by the exposure,
The exposure method according to claim 7, wherein in the obtaining, the forming condition of the first pattern is obtained every time the exposure is performed on at least one of the plurality of objects. Using the exposure method of claim 7 or 8 to form a mask on the target layer on the object;
Processing the target layer using the mask. The first pattern is formed by exposure, the spacer is formed on the side wall of the first pattern, and the first pattern is removed to optimize the formation position of the second pattern formed on the object. System
A detection device for detecting the second pattern formed on the object;
An optimization device for obtaining a formation condition of the first pattern in order to adjust at least one of an interval and a line width of the spacer formed on the sidewall of the first pattern based on the detection result;
A pattern formation optimization system comprising: The second pattern includes a line and space pattern,
The pattern formation optimization system according to claim 10, wherein the detection device detects at least one of an interval and a line width of the second pattern. A mark detection system for detecting a plurality of marks formed together with the second pattern;
The optimization device obtains an alignment error of the second pattern using detection results of the plurality of marks, and obtains a formation condition of the first pattern further based on the alignment error. The pattern formation optimization system described in 1.   12. The pattern formation optimization system according to claim 10, wherein an alignment error at the time of the first pattern exposure is obtained, and a formation condition of the first pattern is obtained based on the alignment error.   The pattern formation optimization system according to any one of claims 10 to 13, wherein the formation condition of the first pattern includes at least one of a line width and a position.   The said optimization apparatus calculates | requires the formation conditions of the said 1st pattern for every shot area on the said object in which the said 2nd pattern is formed, or for every area | region in a shot. The pattern formation optimization system according to item. The pattern formation optimizing system according to any one of claims 10 to 15 for obtaining a formation condition of the first pattern,
An exposure apparatus that forms the first pattern on the object by exposure according to the formation conditions. The pattern formation optimizing system according to any one of claims 10 to 15 for obtaining a formation condition of the first pattern,
A detection device that measures at least one of a line width and a position of the first pattern formed on the object in accordance with the formation condition. The pattern formation optimizing system according to any one of claims 10 to 15 for obtaining a formation condition of the first pattern,
A detection device that measures at least one of an interval and a line width of the second pattern formed on the object according to the formation condition. By the exposure, the first pattern is sequentially formed on a plurality of objects,
The exposure apparatus according to claim 16, wherein the pattern formation optimization system obtains a formation condition of the first pattern every time the exposure is performed on at least one of the plurality of objects.

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