CN102856164B - A kind of method improving alignment mark definition - Google Patents
A kind of method improving alignment mark definition Download PDFInfo
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- CN102856164B CN102856164B CN201210329883.1A CN201210329883A CN102856164B CN 102856164 B CN102856164 B CN 102856164B CN 201210329883 A CN201210329883 A CN 201210329883A CN 102856164 B CN102856164 B CN 102856164B
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- alignment mark
- epitaxial loayer
- column surface
- crystal column
- photoetching
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Abstract
The invention provides a kind of method improving alignment mark definition, described method comprises: at crystal column surface etching alignment mark; Described wafer carries out the growth of epitaxial loayer; Remove the epitaxial loayer grown above alignment mark, the alignment mark of crystal column surface is exposed.The method by increasing a photoetching and etching after outer layer growth, the epitaxial part of alignment mark is had by bottom to be etched away, the mark of bottom is revealed, for follow-up lithography step provides apparent alignment mark, eliminates the problem of contraposition failure.
Description
Technical field
The present invention relates to semiconductor device processing technology field, particularly a kind of method improving alignment mark definition.
Background technology
Manufacture at semiconductor device in the process of leading portion, the process of wafer is needed through laser mark first (ZeroMark), the growth (EPI) of epitaxial loayer, the processing steps such as the photoetching (SDGPHOTO) of fleet plough groove isolation structure.Wherein, utilize laser that alignment mark is set at crystal column surface and can provide the mark of front layer contraposition for the lithography step of follow-up fleet plough groove isolation structure.In the process of photoetching, if forbidden due to contraposition and cause dislocation, figure can be caused to distort or alignment misalignment, finally have influence on the electrical characteristics of manufactured semiconductor device.Therefore, in whole wafer manufacturing process flow process, keep the definition of alignment mark to have very important meaning.
But, with regard to the technological process generally adopted at present, after outer layer growth, due to the translucent characteristic of epitaxial loayer, the alignment mark of bottom can be made to become very unintelligible, thus cause the frequent contraposition failure of follow-up photoetching.Fig. 1 is in prior art after laser marking, the wafer schematic diagram before outer layer growth, and Fig. 2 is in prior art after laser marking, wafer schematic diagram after outer layer growth, as shown in Figure 1 and Figure 2,101 is the alignment marks before outer layer growth, and 201 is the alignment marks after outer layer growth.As seen from the figure, after outer layer growth, alignment mark definition obviously reduces.In order to the alignment mark of bottom can be seen clearly, the degree of depth of laser mark first can only be increased, but, so also have other negative effect a lot.
Summary of the invention
The technical problem to be solved in the present invention there is provided a kind of method improving alignment mark definition, to overcome the impact of epitaxial loayer on bottom laser labelling definition, avoids the problem of follow-up lithography step contraposition failure.
The invention discloses a kind of method improving alignment mark definition, comprising:
At crystal column surface etching alignment mark;
Described wafer carries out the growth of epitaxial loayer;
Remove the epitaxial loayer covering alignment mark part, the alignment mark of crystal column surface is exposed.
Preferably, the described epitaxial loayer removing covering alignment mark part, makes the alignment mark of crystal column surface expose, comprising:
According to the position of described alignment mark, photoetching is carried out to described epitaxial loayer;
Carry out the etching of the epitaxial loayer after photoetching to described, the epitaxial loayer covering alignment mark part is etched away, the alignment mark of crystal column surface is revealed.
Preferably, described method etches alignment mark by laser ablation at crystal column surface.
Preferably, described method, after crystal column surface etching alignment mark, also comprises:
Carry out photoetching and ion implantation to form buried regions at crystal column surface.
Preferably, described alignment mark is used for providing the reference with front layer contraposition for fleet plough groove isolation structure lithography step.
Preferably, describedly lithographic definition is carried out to described epitaxial loayer to cover the region of alignment mark be the region needing to remove epitaxial loayer.
Preferably, the epitaxial loayer area removed is identical with area shared by alignment mark.
The embodiment of the present invention is by after outer layer growth processing step, photoetching and etching is utilized to remove the epitaxial loayer of alignment mark position, the alignment mark of bottom is revealed, lithography step for follow-up fleet plough groove isolation structure provides alignment mark clearly, thus significantly improve the accuracy of photoetching contraposition, eliminate the problem of contraposition failure.
Accompanying drawing explanation
Below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is after in prior art, alignment mark is formed, the wafer schematic top plan view before outer layer growth;
Fig. 2 be in prior art alignment mark formed after and outer layer growth complete after wafer schematic top plan view;
Fig. 3 is the flow chart of the method for the raising alignment mark definition that first embodiment of the invention provides;
Fig. 4 is through the wafer schematic top plan view after the process of first embodiment of the invention method;
Fig. 5 is through the wafer schematic cross-section after the process of first embodiment of the invention method;
Fig. 6 is the flow chart of the method for the raising alignment mark cleaning degree that second embodiment of the invention provides;
Fig. 7 is through the schematic cross-section of the wafer after the second embodiment method process.
Embodiment
Technical scheme of the present invention is further illustrated by embodiment below in conjunction with accompanying drawing.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only step related to the present invention in accompanying drawing but not all processes.
Fig. 3 is the flow chart of the method for the raising alignment mark definition that first embodiment of the invention provides.As shown in Figure 3, described method comprises:
Step 301, crystal column surface etching alignment mark.
In an embodiment of the invention, the etching of alignment mark can be carried out as shown in Figure 1 with laser, respectively get a criss-cross alignment mark by laser in the precalculated position up and down of wafer.Certainly, the form of mark and position are not limited to the form shown in figure and position, as long as can provide bit function for subsequent step.Described alignment mark is used to as follow-up fleet plough groove isolation structure lithography step provides front layer contraposition.
Step 302, on described wafer, carry out the growth of epitaxial loayer.
In one embodiment of the invention, the thickness of outer layer growth is approximately 20K dust, because silicon epitaxy layer is translucent, so make bottom alignment mark definition reduce, can see after accompanying drawing 2 laser marking, and the wafer schematic diagram after outer layer growth.
Photoetching is the technique removed by crystal column surface part film, film with micrographics structure can be left at crystal column surface after photoetching, its target of producing produces accurate in size feature pattern according to the requirement of circuit design, it requires correct positioning pattern, also namely pattern in the position of crystal column surface accurately, is also wanted accurately with associating of other parts.Photoetching determines critical size and the characteristic of device, is therefore high to the precise requirements of contraposition during photoetching.So the definition of alignment mark is extremely important to subsequent step.In the production process of reality, photoetching will complete plurality of layers, and owing to being covered by the thin layer newly grown, the definition of alignment mark can be more and more lower with the increase of the number of plies.Although can improve by the degree of depth increasing mark the definition marked in subsequent step, the performance of made device can be affected so on the one hand, bring very large negative effect; On the other hand, increasing with the number of plies, the problem that definition reduces can become remarkable, can not tackle the problem at its root.The embodiment of the present invention is when not changing the etching depth of alignment mark, and the alignment mark step exposing crystal column surface by increasing the epitaxial loayer be etched on alignment mark solves the problem of alignment mark definition in subsequent step.
Step 303, removal cover the epitaxial loayer of alignment mark part, and the alignment mark of crystal column surface is exposed.
Remove the epitaxial loayer covering alignment mark part in described step 303 to be realized by photoetching and etching two steps, specific as follows:
Step 303A, position according to described alignment mark, carry out photoetching to described epitaxial loayer.
First the present embodiment adds a photoetching, the described lithographic definition mark position of described laser marking.The processing step of a typical photoetching is: be first evenly coated with skim photoresist at crystal column surface, the thickness of glue is approximately 0.5 ~ 1.5 μm, and uniformity is ± 0.01 μm, then cures photoresist, solvent content in photoresist is evaporated, but photoresist still keep the state of " soft ".Required figure will be located on the wafer surface and aim at after curing, and make whole figure correctly be positioned crystal column surface, on figure, the relative position of every part must be correct.Figure location is carried out exposure imaging, is made to be dissolved away the photoresist of telltale mark position after aiming at.
It should be noted that, the photoetching process that the present invention relates to is not limited only to above-mentioned concrete technology flow process, said method is only the description for typical photoetching process, and other photoetching process well-known to those skilled in the art also all can be applicable to the method for the embodiment of the present invention.
Step 303B, to described carry out the epitaxial loayer after photoetching etching, the epitaxial loayer covering alignment mark part is etched away, the alignment mark of crystal column surface is revealed.
In order to the figure on photoresist is transferred in epitaxial film materials further, to come through over etching.Etching technics is by being sprayed on crystal column surface etching liquid, and etch away being exposed to outside epitaxial loayer, thus the alignment mark of bottom is revealed, effect can see the wafer schematic diagram of Fig. 5.If subsequent step to carry out shallow trench isolation from photoetching, so after above-mentioned process, just can carry out aligning location according to alignment mark clearly.And, only open in scribe line because the present invention increases step newly the narrow regions having alignment mark, so any harmful effect can not be produced to chip.
Fig. 4 is the wafer schematic top plan view of the present invention after the process of first embodiment of the invention method.Fig. 5 is through the wafer schematic cross-section after the process of first embodiment of the invention method.As shown in Figure 4 and Figure 5, the wafer after the process of first embodiment of the invention method comprises silicon substrate 502, is etched away the epitaxial loayer 503 of a part and is positioned at the alignment mark 501 of crystal column surface.As can be seen here, by after outer layer growth step, increase the step removing the superstructure covering alignment mark part, alignment mark is exposed, fundamentally solve and cause the unclear problem of alignment mark because epitaxial loayer covers.After schematic cross-section gets rid of by photoetching and etching the epitaxial loayer that alignment mark covers, alignment mark is appeared.And newly-increased epitaxial loayer removal step removing only the narrow regions covering alignment mark in wafer epitaxial loayer, can not produce any impact by the manufacturing process follow-up on wafer.
In addition; it should be noted that; although the figure showing the epitaxial loayer got rid of in Fig. 4 is rectangle, it will be appreciated by those skilled in the art that; it is only an example of the present invention; in other cases, as long as finally expose alignment mark, the photoetching carrying out epitaxial loayer with other shape any can both solve with etching the technical problem that the present invention improves alignment mark cleaning degree; therefore, also all should be included in protection scope of the present invention.
Fig. 6 is the flow chart of the method for the raising alignment mark cleaning degree that second embodiment of the invention provides.Second embodiment for be the situation being generated one deck buried regions in wafer fabrication processes before outer layer growth by ion implantation at crystal column surface in advance, as shown in Figure 6, described method comprises:
Step 601, crystal column surface etching alignment mark.
Step 602, carry out photoetching and ion implantation to form buried regions at crystal column surface.
Step 603, on described wafer, carry out the growth of epitaxial loayer.
In one embodiment of the invention, the thickness of outer layer growth is approximately 20K dust, because silicon epitaxy layer is translucent, so make bottom alignment mark definition reduce.
The epitaxial loayer grown above step 604, removal alignment mark, makes the alignment mark of crystal column surface expose.
Similar with first embodiment of the invention, described removal step also can comprise the position according to described alignment mark, photoetching is carried out to described epitaxial loayer, and, the etching of the epitaxial loayer after photoetching is carried out to described, the epitaxial loayer covering alignment mark part is etched away, makes the step that the alignment mark of crystal column surface reveals.
Fig. 7 is the wafer schematic cross-section of the present invention after the process of second embodiment of the invention method.As shown in Figure 7, the wafer after the process of second embodiment of the invention method comprises silicon substrate 702, the buried regions 704 formed by step 602, is etched away the epitaxial loayer 703 of a part and is positioned at the alignment mark 701 of crystal column surface.As can be seen here, by after outer layer growth step, increase the step removing the superstructure covering alignment mark part, alignment mark is exposed, fundamentally solve and cause the unclear problem of alignment mark because epitaxial loayer covers.And newly-increased epitaxial loayer removal step removing only the narrow regions covering alignment mark in wafer epitaxial loayer, can not produce any impact by the manufacturing process follow-up on wafer.
Known according to a second embodiment of the present invention, for the wafer manufacturing process flow process manufacturing buried regions before outer layer growth, remove the definition that epitaxial loayer can improve alignment mark equally.
The embodiment of the present invention is by after outer layer growth processing step, photoetching and etching is utilized to remove the epitaxial loayer of alignment mark position, the alignment mark of bottom is revealed, lithography step for follow-up fleet plough groove isolation structure provides alignment mark clearly, thus significantly improve the accuracy of photoetching contraposition, eliminate the problem of contraposition failure.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various change and change.All do within spirit of the present invention and principle any amendment, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. improve a method for alignment mark definition, comprising:
At crystal column surface etching alignment mark;
Described wafer carries out the growth of epitaxial loayer;
Remove the epitaxial loayer covering alignment mark part, the alignment mark of crystal column surface is exposed;
Described alignment mark is used for providing the reference with front layer contraposition for fleet plough groove isolation structure lithography step;
Wherein, the described epitaxial loayer removing covering alignment mark upper section, makes the alignment mark of crystal column surface expose, comprising:
According to the position of described alignment mark, photoetching is carried out to described epitaxial loayer;
Carry out the etching of the epitaxial loayer after photoetching to described, the epitaxial loayer covering alignment mark part is etched away, the alignment mark of crystal column surface is revealed;
The described position according to described alignment mark, photoetching is carried out to described epitaxial loayer and comprises:
Evenly apply photoresist at crystal column surface, described photoresist thickness is 0.5 ~ 1.5 μm, and uniformity is ± 0.01 μm;
Successively described photoresist cured, locate aligning and exposure imaging, make to be dissolved away the photoresist of telltale mark position.
2. the method improving alignment mark definition as claimed in claim 1, is characterized in that, etch alignment mark by laser ablation at crystal column surface.
3. the method improving alignment mark definition as claimed in claim 1, is characterized in that, described method, after crystal column surface etching alignment mark, also comprises:
Carry out photoetching and ion implantation to form buried regions at crystal column surface.
4. the as claimed in claim 1 method improving alignment mark definition, is characterized in that, described to carry out to described epitaxial loayer the region that lithographic definition covers alignment mark be the region needing to remove epitaxial loayer.
5. method according to claim 1, is characterized in that, the epitaxial loayer area removed is identical with area shared by alignment mark.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105914131A (en) * | 2016-04-27 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Processing method for optical waveguide semiconductor devices |
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| CN104280261A (en) * | 2013-07-08 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of cross-sectional sample |
| CN104078405A (en) * | 2014-06-24 | 2014-10-01 | 上海天英微系统科技有限公司 | Photoetching alignment method and wafers |
| CN104882436B (en) * | 2015-03-31 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Twice in epitaxy technique photoetching alignment mark preparation method |
| CN107505816B (en) * | 2017-09-11 | 2019-07-23 | 深圳市华星光电技术有限公司 | Substrate and liquid crystal display panel |
| CN109742054A (en) * | 2019-01-10 | 2019-05-10 | 信利半导体有限公司 | Display panel manufacturing method and display panel |
| CN112542413B (en) * | 2020-12-03 | 2021-09-28 | 中国电子科技集团公司第五十五研究所 | Alignment method for heterogeneous substrate semiconductor thin film device |
| CN113471061A (en) * | 2021-06-30 | 2021-10-01 | 颀中科技（苏州）有限公司 | Preparation method of wafer surface dielectric layer, wafer structure and forming method of bump |
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