CN112542413B - Alignment method for heterogeneous substrate semiconductor thin film device - Google Patents
Alignment method for heterogeneous substrate semiconductor thin film device Download PDFInfo
- Publication number
- CN112542413B CN112542413B CN202011413182.7A CN202011413182A CN112542413B CN 112542413 B CN112542413 B CN 112542413B CN 202011413182 A CN202011413182 A CN 202011413182A CN 112542413 B CN112542413 B CN 112542413B
- Authority
- CN
- China
- Prior art keywords
- alignment
- thin film
- semiconductor thin
- alignment mark
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Abstract
The invention discloses a heterogeneous substrate semiconductor thin film device alignment method, which comprises the following steps in sequence: completing the preparation of a device circuit and the preparation of an alignment mark A array and an alignment mark B array on the front side of a target substrate; peeling and transferring the semiconductor film to be transferred to the front surface of the target substrate wafer; exposing at least two alignment marks A on the semiconductor film transferred onto the target substrate by exposure; carrying out alignment exposure through the mask and the alignment mark A to expose the alignment mark B array; and performing device tape-out and heterogeneous interconnection of the semiconductor film and the target substrate device structure on the front surface of the transferred semiconductor film by using the alignment mark B array through a standard microelectronic processing process. The invention solves the high-precision alignment problem of the heterogeneous substrate integrated non-transparent semiconductor thin film material, lays a foundation for the subsequent heterogeneous integration technology based on the standard microelectronic process, and is beneficial to further improving the heterogeneous integration density.
Description
Technical Field
The invention belongs to the technical field of semiconductor processes, and particularly relates to an alignment method of a heterogeneous substrate semiconductor thin film device.
Background
The heterogeneous integration technology is to mix InP, GaAs, GaN, Si and LiNbO3、Ga2O3The circuits of semiconductor devices made of different materials and with different processes are integrated on the same chip substrate by a specific technical means, so that the limitation of a single material is broken through, the integration of devices in different types and different fields such as microelectronic devices, optoelectronic devices, MEMS devices and the like can be realized on the same chip, and the method is one of important ways for the development of semiconductor technology in the later molar times. To maximize the performance advantages of different materials and devicesThe integration density is increased as much as possible, and the interconnection pitch between these heterogeneous material devices is shortened. In order to avoid alignment deviation caused by thermal expansion coefficient and obtain higher alignment precision, one of the most effective methods is to peel off the semiconductor film from the original substrate, transfer the semiconductor film to a target substrate for completing a device circuit process, and then use a fine microelectronic process to prepare a device on the transferred semiconductor film and interconnect the device with a device structure on the target substrate. The alignment accuracy of the semiconductor thin film and the device structure on the target substrate determines the integration density and functional complexity of the integrated circuit. However, semiconductor thin film materials such as InP, GaAs, Si, and the like are not transparent under visible light and infrared light, and the mark on the target substrate cannot be directly detected and used. In view of the above problem, it is necessary to develop an alignment method for a heterogeneous substrate semiconductor thin film device, in which the semiconductor thin film device and a device on a target substrate are incorporated into the same alignment reference system, so as to solve the problem of high-precision alignment and alignment of heterogeneous substrates integrated with different semiconductor material devices.
Disclosure of Invention
In order to solve the technical problems mentioned in the background technology, the invention provides an alignment method of a foreign substrate semiconductor thin film device.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a foreign substrate semiconductor thin film device alignment method includes the following steps:
(1) completing the preparation of a device circuit and the preparation of an alignment mark A array and an alignment mark B array on the front side of a target substrate;
(2) peeling and transferring the semiconductor film to be transferred to the front surface of the target substrate wafer;
(3) exposing at least two alignment marks A on the semiconductor film transferred onto the target substrate by exposure;
(4) carrying out alignment exposure through the mask and the alignment mark A to expose the alignment mark B array;
(5) and performing device tape-out and heterogeneous interconnection of the semiconductor film and the target substrate device structure on the front surface of the transferred semiconductor film by using the alignment mark B array through a standard microelectronic processing process.
Further, the shape of alignment mark A includes bar, cross and meter font, the shape of alignment mark B includes bar, cross and meter font.
Further, the device circuit comprises a semiconductor device and a corresponding matching transmission circuit thereof, and the size range of the minimum repeating unit of the device circuit is 100-20000 mu m.
Further, the spacing distance of the alignment mark A array is the same as the size of the minimum repeating unit of the device circuit, and the spacing distance of the alignment mark B array is the same as the size of the minimum repeating unit of the device circuit.
Further, in the step (2), the modes of peeling and transferring the semiconductor film to be transferred to the front surface of the target substrate wafer comprise a peeling-first bonding-then-peeling mode and a bonding-first peeling-then-bonding mode.
Further, the thickness of the semiconductor thin film after transfer is 50nm to 20 μm.
Further, in the step (3), at least two exposure windows are exposed through photoetching at any position on the epitaxial layer of the semiconductor thin film transferred onto the target substrate, and then the semiconductor epitaxial layer material and the stop layer material in the exposure windows are removed through etching or corrosion methods, so that the alignment mark A is exposed in the exposure windows.
Further, the size of the exposure window is not less than 2 times the size of the smallest repeating unit of the device circuit.
Further, in the step (4), the mask includes a pattern which is consistent with the distribution of the alignment marks a and B, after the alignment marks a are identified by a lithography machine and are subjected to overlay, a small window array is exposed in the minimum repeating unit of each device circuit, then the semiconductor epitaxial layer material and the stop layer material in each small window are removed by etching or corrosion, the alignment marks B in each small window are exposed, and an array of the alignment marks B is formed.
Further, in step (5), the alignment mark B is first identified by a photolithography machine and is subjected to overlay, followed by standard microelectronic processing.
Adopt the beneficial effect that above-mentioned technical scheme brought:
the invention solves the high-precision alignment method of the heterogeneous substrate integrated non-transparent semiconductor thin film material through two times of mark transfer, thereby bringing the transferred epitaxial thin film device and the target substrate device into the same alignment reference system, laying a foundation for the subsequent heterogeneous integration technology based on the standard microelectronic process, and being beneficial to further improving the heterogeneous integration density.
Drawings
FIG. 1 is a flow chart of a method of the present invention;
FIG. 2 is a schematic top view of an embodiment of a target substrate wafer and a wafer of material to be transferred;
FIG. 3 is a schematic diagram of the completed device circuit fabrication on a target substrate wafer in an embodiment;
FIG. 4 is a schematic view of alignment mark A and alignment mark B in the embodiment;
FIG. 5 is a schematic cross-sectional view of an integrated structure after transfer in an embodiment;
FIG. 6 is a schematic diagram illustrating exposure of alignment mark A after exposure in one embodiment;
fig. 7 is a schematic diagram of exposure of the alignment mark B array after alignment exposure through the mask and the alignment mark a.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention by specific embodiments thereof with reference to the accompanying drawings. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
The invention designs an alignment method of a heterogeneous substrate semiconductor thin film device, which comprises the following steps as shown in figure 1:
step S01: and completing the preparation of a device circuit and the preparation of an alignment mark A array and an alignment mark B array on the front side of the target substrate.
Specifically, the fabrication of the device circuit is completed on a target substrate 201 as shown on the left side of fig. 2, the material type of the target substrate 201 including, but not limited to, one of semiconductor materials such as InP, GaAs, GaN, Si, SiC, Diamond, etc. In this example, a Si material.
Further preferably, the target substrate 201 shown on the left side of fig. 2 may be a standard wafer size of 3 inches, 4 inches, 5 inches, 6 inches, etc., or may be a small piece having a length of no more than 10 cm. In this embodiment, 4 inch wafers.
Further preferably, the device circuit completed on the target substrate 201 as shown on the left side of fig. 2 includes, but is not limited to, one of semiconductor devices such as Si CMOS, Si PIN, Si BJT, InP HBT, GaAs HBT, GaN HEMT, SiC MOS, Ga2O3 MOS, LiNbO3 SAW, and the corresponding matched transmission circuit. In this embodiment, a Si CMOS device circuit.
It is further preferred that the size of the smallest repeating unit 301 of the device circuitry on the target substrate 201 is in the range of 100 μm to 20000 μm. In this embodiment, 1000 μm × 1000 μm, and the target substrate after completing the device circuit fabrication is shown in fig. 3.
Further preferably, the shape of the alignment mark a is a special shape such as a bar, a cross, a Chinese character 'mi', and as shown in fig. 4, the size of the alignment mark a ranges from 50 μm × 50 μm to 200 μm × 200 μm, and in this embodiment, is 100 μm × 100 μm. The array of alignment marks A is spaced apart by a distance corresponding to the size of the smallest repeating unit 301 of the device circuit on the target substrate, which is 100 μm to 20000 μm, in this embodiment 1000 μm in the x-direction and 1000 μm in the y-direction.
Further preferably, the shape of the alignment mark B is a special shape such as a bar, a cross, a meter shape, and the like, as shown in fig. 4, the size of the alignment mark B ranges from 50 μm × 50 μm to 1000 μm × 1000 μm, and in this embodiment, is 500 μm × 200 μm. The array of alignment marks B is spaced apart by a distance consistent with the size of the smallest repeating unit of the device circuit on the target substrate, 100 μm to 20000 μm, in this embodiment 1000 μm in the x-direction and 1000 μm in the y-direction.
Step S02: and peeling and transferring the semiconductor film to be transferred to the front side of the target substrate wafer.
Specifically, the semiconductor thin film 202 to be transferred is transferred from the original epitaxial substrate to the front surface of the target substrate 201 by peeling.
Further preferably, the semiconductor thin film 202 to be transferred is shown on the right side of fig. 2, and includes but is not limited to one of semiconductor materials such as Si, InP, GaAs, GaN, SiC, Ga2O3, LiNbO3, and the like. In this embodiment, the epitaxial layer is made of GaAs pHEMT material.
Further preferably, the thickness of the semiconductor thin film 202 after transfer is between 50nm and 20 μm.
It is further preferable that the method for peeling and transferring the semiconductor thin film 202 to be transferred from the original substrate to the front surface of the target substrate 201 includes, but is not limited to, peeling before bonding, bonding before peeling, and the like. In this embodiment, a semiconductor substrate to be transferred is bonded with a target substrate with its front surface facing downward, then the back surface of the original semiconductor substrate is thinned to a certain thickness, then the semiconductor material is etched by a dry method to an etching stop layer, and then the stop layer is removed to the semiconductor thin film, so that the semiconductor thin film 202 is transferred to the target substrate 201, and a schematic cross-sectional view of the integrated structure after the transfer is shown in fig. 5.
Step S03: at least two alignment marks A are exposed by exposure on the semiconductor thin film transferred onto the target substrate.
Specifically, as shown in fig. 6, two or more windows 601 are lithographically exposed by a contact lithography machine or a stepper lithography machine at arbitrary positions on the epitaxial layer of semiconductor material transferred onto the target substrate. Wherein the upper part of figure 6 shows a schematic view of an exposure window on a target substrate 201 and the lower part of figure 6 shows an enlarged detail of a lithographic exposure pattern. In this embodiment, the number of the windows 601 is 2, and then the semiconductor epitaxial layer material and the stop layer material in the windows 601 are removed by etching or etching, in this embodiment, the GaAs pHEMT material is removed by chlorine-based etching, and the InGaP stop layer is removed by etching with a phosphate-based material.
It is further preferable that the length and width of each exposure window 601 is not less than twice the size of the minimum repeating unit 301 of the device circuit on the target substrate 201, the size of the window 601 in this embodiment is 2000 μm × 2000 μm, and the alignment mark a and the size of the minimum repeating unit 301 of the device circuit on the target substrate 201 are schematically illustrated in the lower half of fig. 6.
It is further preferred that two windows 601 and corresponding dimensions as shown in fig. 6 already satisfy the subsequent high precision overlay requirement, but those skilled in the art will appreciate that the number of windows 601 and the size of the windows 601 may be increased without increasing the process complexity but sacrificing effective device circuit area.
Step S04: and carrying out alignment exposure through the mask and the alignment mark A to expose the alignment mark B array.
Specifically, the mask includes a pattern corresponding to the distribution of the alignment marks a and B, the alignment mark a is identified by a stepper, and after overlay, an array of small windows 701 is exposed in each minimal repeating circuit unit 301 on the target substrate 201, as shown in fig. 7.
Further preferably, the relative position of the small window 701 in each minimal repeating unit 301 on the target substrate and the size of the small window 701 may be determined by layout design, where the size of the small window 701 is 700 μm × 400 μm in this embodiment.
Further preferably, the semiconductor epitaxial layer material and the stop layer material in the small windows 701 are removed by etching or etching, etc., to expose the alignment marks B in each small window 701, so as to form an array of alignment marks B. In this example, the GaAs pHEMT material was etched by chlorine-based etching, and the InGaP stop layer was etched by a phosphate-based material.
Step S05: and performing device tape-out and heterogeneous interconnection of the semiconductor film and the target substrate device structure on the front surface of the transferred semiconductor film by using the alignment mark B array through a standard microelectronic process.
Specifically, the alignment mark B is identified by a stepping photoetching machine, and is subjected to alignment, and then the device flow sheet and the heterogeneous interconnection of the device flow sheet and a device structure on a target substrate are carried out on the front surface of the transferred semiconductor thin film material by a standard microelectronic process.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.
Claims (10)
1. A foreign substrate semiconductor thin film device alignment method is characterized by comprising the following steps:
(1) completing the preparation of a device circuit and the preparation of an alignment mark A array and an alignment mark B array on the front side of a target substrate;
(2) peeling and transferring the semiconductor film to be transferred to the front surface of the target substrate wafer;
(3) exposing at least two alignment marks A on the semiconductor film transferred onto the target substrate by exposure;
(4) carrying out alignment exposure through the mask and the alignment mark A to expose the alignment mark B array;
(5) and performing device tape-out and heterogeneous interconnection of the semiconductor film and the target substrate device structure on the front surface of the transferred semiconductor film by using the alignment mark B array through a standard microelectronic processing process.
2. The foreign substrate semiconductor thin film device alignment method of claim 1, wherein the shape of the alignment mark a includes a stripe shape, a cross shape and a meter shape, and the shape of the alignment mark B includes a stripe shape, a cross shape and a meter shape.
3. The foreign substrate semiconductor thin film device alignment method as claimed in claim 1, wherein the device circuit comprises a semiconductor device and its corresponding matched transfer circuit, and the size of the smallest repeating unit of the device circuit is in the range of 100 to 20000 μm.
4. The foreign substrate semiconductor thin film device alignment method of claim 2, wherein the spacing distance of the alignment mark A array is the same as the size of the minimum repeating unit of the device circuit, and the spacing distance of the alignment mark B array is the same as the size of the minimum repeating unit of the device circuit.
5. The foreign substrate semiconductor thin film device alignment method of claim 1, wherein in the step (2), the peeling and transferring of the semiconductor thin film to be transferred to the front surface of the target substrate wafer comprises a peeling-first bonding-then-bonding mode and a bonding-first peeling-then-bonding mode.
6. The foreign substrate semiconductor thin film device alignment method as claimed in claim 1, wherein the thickness of the semiconductor thin film after transfer is 50nm to 20 μm.
7. The foreign substrate semiconductor thin film device alignment method as claimed in claim 1, wherein in step (3), at least two exposure windows are exposed by photolithography at arbitrary positions on the epitaxial layer of the semiconductor thin film transferred onto the target substrate, and then the semiconductor epitaxial layer material and the stop layer material in the exposure windows are removed by etching, and the alignment mark a is exposed in the exposure windows.
8. The foreign substrate semiconductor thin film device alignment method of claim 7, wherein the size of the exposure window is not less than 2 times the size of the smallest repeating unit of the device circuit.
9. The method for aligning a foreign substrate semiconductor thin film device according to claim 1, wherein in step (4), the mask comprises a pattern which is consistent with the distribution of the alignment marks A and B, the alignment marks A are identified by a lithography machine and are subjected to overlay, a small window array is exposed in the minimal repeating unit of each device circuit, then the semiconductor epitaxial layer material and the stop layer material in each small window are removed by an etching method, and the alignment marks B in each small window are exposed to form the array of the alignment marks B.
10. The foreign substrate semiconductor thin film device alignment method of claim 1, wherein in step (5), the alignment mark B is first identified by a photolithography machine and is subjected to an overlay, followed by a standard microelectronic process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011413182.7A CN112542413B (en) | 2020-12-03 | 2020-12-03 | Alignment method for heterogeneous substrate semiconductor thin film device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011413182.7A CN112542413B (en) | 2020-12-03 | 2020-12-03 | Alignment method for heterogeneous substrate semiconductor thin film device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112542413A CN112542413A (en) | 2021-03-23 |
| CN112542413B true CN112542413B (en) | 2021-09-28 |
Family
ID=75016121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011413182.7A Active CN112542413B (en) | 2020-12-03 | 2020-12-03 | Alignment method for heterogeneous substrate semiconductor thin film device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112542413B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113808985A (en) * | 2021-09-02 | 2021-12-17 | 中国电子科技集团公司第五十五研究所 | Heterogeneous substrate thin film transfer alignment method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0762492A1 (en) * | 1995-08-25 | 1997-03-12 | Sony Corporation | Semiconductor device manufacturing method |
| CN102386322A (en) * | 2010-08-25 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for improving aligning accuracy |
| CN102856164A (en) * | 2012-09-07 | 2013-01-02 | 无锡华润上华科技有限公司 | Method for improving clearness of alignment marks |
| CN108117043A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN111916427A (en) * | 2020-08-24 | 2020-11-10 | 福建省晋华集成电路有限公司 | Photoetching alignment mark, photoetching alignment method and semiconductor device preparation method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105645347B (en) * | 2014-11-18 | 2017-08-08 | 无锡华润上华半导体有限公司 | The localization method of bulk-micromachining |
| CN104460243B (en) * | 2014-12-26 | 2017-03-01 | 上海集成电路研发中心有限公司 | Double-pattern lithography alignment method |
-
2020
- 2020-12-03 CN CN202011413182.7A patent/CN112542413B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0762492A1 (en) * | 1995-08-25 | 1997-03-12 | Sony Corporation | Semiconductor device manufacturing method |
| CN102386322A (en) * | 2010-08-25 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for improving aligning accuracy |
| CN102856164A (en) * | 2012-09-07 | 2013-01-02 | 无锡华润上华科技有限公司 | Method for improving clearness of alignment marks |
| CN108117043A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN111916427A (en) * | 2020-08-24 | 2020-11-10 | 福建省晋华集成电路有限公司 | Photoetching alignment mark, photoetching alignment method and semiconductor device preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112542413A (en) | 2021-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3963489A (en) | Method of precisely aligning pattern-defining masks | |
| EP0126621A2 (en) | Alignment marks on semiconductor wafers and method of manufacturing the marks | |
| US20080248600A1 (en) | Method and device for wafer backside alignment overlay accuracy | |
| US8563202B2 (en) | Single field zero mask for increased alignment accuracy in field stitching | |
| US7401549B2 (en) | Arrangement for transferring information/structures to wafers | |
| CN112542413B (en) | Alignment method for heterogeneous substrate semiconductor thin film device | |
| CN113341664A (en) | Concave SOI substrate electron beam alignment mark structure and preparation method thereof | |
| US6632575B1 (en) | Precision fiducial | |
| TWI302348B (en) | ||
| CN116360223A (en) | Measurement pattern structure and method of using the same | |
| CN113808985A (en) | Heterogeneous substrate thin film transfer alignment method | |
| CN113611670B (en) | Device including gate oxide layer and alignment mark and method of forming the same | |
| CN114284243A (en) | Bonding wafer, bonding structure and bonding method | |
| CN101354528B (en) | Mask and related photo-etching method | |
| KR20090099871A (en) | Alignment key of semiconductor device and method for forming of the same | |
| CN101504510A (en) | Photoetching technology | |
| US20070184580A1 (en) | Method of making a small substrate compatible for processing | |
| US20230350309A1 (en) | Identification codes on semiconductor chips | |
| US11892774B2 (en) | Lithography | |
| CN114068312A (en) | Die traceability using backside mask layer | |
| CN115793413A (en) | Super-resolution pattern realization method and device based on alignment difference and double photoetching | |
| JPS623944B2 (en) | ||
| Chen | Multifinger gallium arsenide MESFET design and fabrication for MMIC applications | |
| CN117912938A (en) | Dual patterning method, semiconductor device and electronic equipment | |
| CN114624960A (en) | Large-size chip photoetching splicing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |