JPS623944B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photomask substrate used in a photolithography (hereinafter abbreviated as photolithography) process in manufacturing a semiconductor integrated circuit device.

In the manufacture of a standard semiconductor integrated circuit device, an average of eight to ten photoetching steps are performed. Therefore, a glass photomask substrate with 6 to 8 layers is required;
8 to 8 alignment marks are required.

However, when designing a semiconductor integrated circuit device, it is always required to minimize the chip area, so it is not always possible to secure a space for the alignment mark at a predetermined position in the chip area. Rather, each alignment mark is often arranged in a dispersed manner.

A conventional photomask substrate is shown in FIG. In FIG. 1, reference numeral 1 is a transparent glass substrate made of quartz or the like, and the surface of this substrate 1 is made of a material that is opaque to the light that exposes the photoresist film, and has X Grid line 2 in the axial direction and grid line 3 in the same Y-axis direction
, an alignment mark 4 to the mark on the wafer, a layer display number 5, and a pattern 6 for configuring the circuit.
is formed. Also, in Figure 1, 7
is the space for alignment marks used in later steps, 8 is the microscope field of view, 9 is one chip area, 1
0 is a space for the alignment mark used in the previous process, and 12 is an example of the alignment mark used in the next process.

For the reasons mentioned above and as illustrated in Figure 1, near the used mark in the previous process,
Since there is not always an exposure mark for the relevant process, as the wafer processing process progresses, it becomes difficult to detect the alignment mark and determine whether it is a used mark or not. Therefore, in order to take these measures, it has become an essential condition for conventional photomask substrates to attach layer display numbers near the alignment marks, but these have the problem of increasing the area occupied by the alignment marks. occurs. For example, when aligning with an accuracy of 2 μm, a microscope with a magnification of about 400 times is used, but the field of view of this microscope is up to 30,000 μm ²
Considering a chip with an area of 5 mm x 5 mm, the current situation is that only 0.1% of the area can be seen in one field of view. In other words, in conventional photomask substrates where it is essential to attach layer numbers to alignment marks, one 20 to 30 μm x 20
Even with ~30μm alignment marks, 30000
Since it was impossible to aggregate them in an area of µm ² or less, it took time to align them, which was a major obstacle to shortening the processing time of the photolithography process. FIG. 4 shows time data required for alignment using a conventional photomask substrate. From the data shown by the solid line in FIG. 4, it is clear that with the conventional photomask substrate, it is difficult to shorten the processing time for one silicon wafer to at least 67 seconds or less.

The present invention aims to solve the above-mentioned conventional problems, and by providing a second alignment mark such as a frame surrounding the first alignment mark, layer display numbers are not required, The second alignment mark is used as an auxiliary alignment mark, and the alignment marks of each layer can be provided at closer positions than conventional ones, reducing the alignment mark area and improving alignment work efficiency. The purpose of this invention is to provide a photomask substrate that can be used.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the invention. In FIG. 2, 1 is a transparent glass substrate, and this substrate 1
The surface is made of a material that is opaque to the light that exposes the photoresist film, and has grid lines 2 in the X-axis direction that divide the chip area, grid lines 3 in the Y-axis direction, and a first alignment mark to the mark on the wafer. A mark 4 and a second alignment mark 11 forming an outer frame surrounding the entire alignment mark area including the area of the mark 4 are formed. Also, 7
is the alignment mark space used in the subsequent process, 9 is one chip area, 10 is the alignment mark space used in the previous process, and 12 is an example of the first alignment mark used in the next process. be.

Next, an example of a photolithography process using the photomask substrate of the above embodiment will be explained with reference to FIGS. 3a to 3e. In Figure 3 a, b, d, e, 13
14 is a silicon wafer, 14 is an insulating film such as silicon oxide, and 15 is a photoresist.

As shown in FIGS. 3a and 3b, the entire alignment mark area provided on the transparent glass substrate 1 and the silicon wafer 13 is brought into the field of view of the microscope in an area of 25000 μm ² or less surrounded by the second alignment mark 11. .
Next, the second alignment mark 11 is placed on the wafer 1.
Align with mark 3. Thereafter, the first alignment mark 4 is already aligned with the alignment mark 10 on the wafer 13.
Align it with the alignment mark formed on . and,
Exposure is performed as shown in FIG. 3c. At this time, alignment marks 12 to be used in the next process are transferred onto the wafer 13. Next, etching is performed to grow a second insulating film. Thereafter, the same process as described above is repeated, but this time,
As shown in e, the alignment mark 12 to be used in the next process is transferred to a different location on the wafer 13 from that in the previous process.

As described above, in this embodiment, by surrounding the alignment mark area with the second alignment mark, the area of the mark area can be reduced, and for this reason, all the alignment marks can be included in the field of view of the microscope. becomes possible. Since the second alignment mark roughly aligns the photomask substrate and the wafer, it is easy to distinguish the pattern from a used pattern. Therefore, this embodiment has the advantage that the processing time of the photolithography process can be significantly shortened. That is, as shown by the broken line in FIG. 4, when the photomask substrate of this embodiment is used, the wafer 1
The average processing time for each sheet is about 57 seconds, which is 25 seconds faster than before.
It can be seen that the time can be reduced by more than %.

As explained above, in the photomask substrate of the present invention, since the second alignment mark is provided surrounding at least one first alignment mark, the area of the alignment mark region can be reduced.
It also has the effect of obtaining good alignment work efficiency, and can be used for manufacturing all semiconductor circuit devices.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an alignment mark portion of a conventional photomask substrate, FIG. 2 is an explanatory diagram of an alignment mark portion of a photomask substrate according to an embodiment of the present invention, and FIGS. A vertical sectional view and a plan view for explaining the mask alignment process using the photomask substrate of the example, FIG. 3c is a block diagram explaining the process after mask alignment of FIGS. e is a vertical cross-sectional view and a plan view for explaining the mask alignment process after the step in FIG. It is a figure which compares and shows combined time processing time. DESCRIPTION OF SYMBOLS 1... Transparent glass substrate, 2, 3... Grid line, 4... Alignment mark, 9... One chip area, 11... Second alignment mark.

Claims (1)

[Scope of Claims] 1. A transparent substrate made of a material through which light for exposing a photoresist film passes, and a surface of this transparent substrate defined by grid lines in the X-axis direction and Y-axis direction made of a material opaque to the light. a plurality of chip regions, at least one first alignment mark made of the opaque material formed on a surface of the chip regions, and surrounding the first alignment mark within the chip region; and a second alignment mark formed of the opaque material. 2 The area surrounded by the second alignment mark is
The photomask substrate according to claim 1, which has a size of 25000 μm ² or less.