JPH11297777A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it easier length measurement using a scanning electron microscope(SEM) in a step of etching an insulation film after a planarization step and to reduce an occupied area of length measurement pattern. SOLUTION: This method comprises the steps of forming a first insulation film 14 on a silicon substrate 11 in an SEM length measurement region, forming a first contact hole 15' connecting to the substrate 11 in a first insulation film 14, filling the first contact hole 15' and forming a base conductive film 16' on the first insulation film 14, forming a second insulation film 17 on the base conductive film 16' and flattening the second insulation film 17, forming a second contact hole 18' connecting to the second insulation film 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device (hereinafter abbreviated as LSI) and a method of manufacturing the LSI.

[0002]

2. Description of the Related Art There is a strong demand for LSIs to achieve electrical performance such as high speed, high integration, and multiple functions with a small occupied area. To meet this requirement, LS
In the process of forming a circuit pattern such as an electrode, a wiring, and a contact hole required in I, it is essential to always maintain high processing accuracy.

[0003] A basic element process of an LSI will be outlined below. Semiconductor silicon wafer (hereinafter abbreviated as wafer)
An insulating film or a conductive film was formed on the surface of
After that, a photosensitive polymer material called photoresist is applied to the wafer. Thereafter, a desired circuit pattern is transferred to the photoresist by an optical method (hereinafter, abbreviated as a photolithography process).

Using the transferred photoresist pattern as a mask material, an insulating film or a conductive film generated in a CVD process is removed (hereinafter, abbreviated as an etching process) to form a desired circuit pattern on a wafer. When impurity ions are implanted in the vicinity of the surface of a wafer, a pattern of an implantation region is formed on a photoresist by a photolithography process, and then ion implantation is performed to form a diffusion layer region.

[0005] The LSI manufacturing process is configured by combining the above-described element processes. Although high processing accuracy is required in any of the element processes, it is particularly important to maintain the processing accuracy of the circuit pattern formed in the photolithography step and the etching step. As a method of managing the processing accuracy in these steps, dimension measurement using a scanning electron microscope (hereinafter abbreviated as a length measuring SEM machine) is generally performed.

In order to measure a fine circuit pattern formed on a wafer by destruction, the length measuring SEM machine transports the wafer as it is to a vacuum chamber, and directly reads a primary electron from immediately above a designated measuring position. And captures the secondary electrons emitted from the vicinity of the measurement location, performs electrical signal processing based on this information, and displays the SE near the measurement location on the CRT screen.
An M image is displayed. Although this SEM image is a black-and-white screen, it has a slight contrast due to the difference in the material of the wafer surface, the unevenness of the wafer surface, the shape of the formed circuit pattern, and the like.

The SEM length measurement work in the LSI manufacturing process is as follows.
The length measuring person recognizes the SEM image near the length measuring point displayed on the CRT screen of the length measuring SEM machine, searches for and identifies the specified length measuring point, and then performs the measurement. In a general-purpose LSI having a large number of repetitive circuit patterns, such as a DRAM, the length of an actual LSI circuit pattern is measured. However, ASIC / LSI products such as logic products (semiconductor devices for specific applications)
In this case, since the circuit pattern differs for each product type, it is difficult to measure the actual length of the circuit pattern.

Therefore, in such a case, a pattern for a length measurement SEM (hereinafter, abbreviated as a length measurement pattern) is placed at a specific place in an LSI chip or on a scribe line.
The processing accuracy is managed by the dimension measurement work of this pattern. In order to secure both requirements for the stability of the process processing and the convenience of the SEM length measurement operation, the SEM length measurement pattern is often formed in a different region for each process. In the length measurement pattern in the same step, a plurality of patterns formed in the step are formed.

[0009]

In the conventional method described above, a desired circuit pattern of an LSI is formed in a photolithography process by applying an optical technique to a resist pattern, and the resist pattern is used as a mask material to form a base film. Is formed by performing an etching process. However, as the demand for miniaturization of circuit patterns has progressed, a flattening process different from the conventional elemental process has become indispensable in order to secure the characteristics in the photolithography process. This flattening process is a process for ensuring flatness over the entire surface of the wafer, as typified by CMP (chemical mechanical polishing). By employing this process, it is possible to form a fine resist pattern without significantly improving characteristics such as resolution and depth of focus in the photolithography process.

[0010] This flattening process uses an ASIC such as a logic product rather than a general-purpose LSI represented by a DRAM.
It is frequently used in product LSIs. A plurality of layers of metal wiring are formed on the circuit pattern of the ASIC / LSI in order to satisfy the requirements of individual users for high functionality and high performance. The possibility of the photolithography process for forming these wiring layers depends largely on the irregularities of the underlying film. Therefore ASI
In the case of a C / LSI product, since a stable wiring layer photolithography process needs to be performed, a flattening process for reducing the influence of the unevenness of the underlying film is an essential technology.

However, in the process after the flattening process, when performing the SEM length measurement work after performing the etching process (via hole contact etching) for forming the connection port between the metal wirings, Problems occur. The first problem will be described below by showing a cross-sectional structure in which a method of forming an actual circuit pattern and a measurement pattern of a via hole are compared.

FIG. 3 is a sectional view of a conventional LSI manufacturing process (part 1), and FIG. 4 is a sectional view of the LSI manufacturing process (part 2).
It is. (1) First, as shown in FIG. 3A, after forming a gate electrode having an LDD structure, an actual circuit pattern A and a length measurement pattern B in a state where an insulating film is formed by a CVD method are formed. Here, 1 is a silicon substrate, 2 is a field thermal oxide film formed for the purpose of element isolation, and its thickness is 200
It is about 0 to 6000 °. Reference numeral 3 denotes a gate electrode having an LDD structure.

The gate electrode 3 has a thickness of 1000 ° to 30 °.
The gate electrode 3 and the silicon substrate 1 are formed of a eutectic film of silicon and a high melting point metal such as tungsten, molybdenum, titanium or the like having a thickness of about 00 ° and silicon (not shown in the figure). Between them, there is a thermal oxide film having a thickness of about 100 ° called a gate oxide film). Reference numeral 4 denotes an insulating film formed by a CVD method,
G film or O ₃ -TEOS.BPSG film. Its thickness is about 4000-9000 °.

(2) Next, as shown in FIG. 3B, the gate electrodes 3 or the gate electrode 3 and the silicon substrate 1
Contact hole 5 is formed to electrically connect. (3) Next, as shown in FIG. 3C, a metal wiring 6 is formed in the contact hole 5. A first metal wiring (base metal film) 6 ′ formed for the purpose of making an electrical connection with the gate electrode 3, the silicon substrate 1, and the like is formed on the insulating film 4 on the length measurement pattern forming region B side. Form. The film thickness of the first metal wiring 6 'is about 3000 to 7000 mm, and an alloy of aluminum, silicon and copper, an alloy of aluminum and copper, or the like is used.

In some cases, titanium or titanium nitride is formed on these alloys. Further, the first metal wiring 6 'is formed simultaneously with the metal wiring 6 of the contact hole in the formation region of the length measurement pattern as a base film of the via hole contact. Its planar pattern dimension is 30,000
It is often a square of about 正方形 to 80000Å. (4) Next, as shown in FIG. 4A, an insulating film 7 is formed to ensure insulation of the first metal wirings 6, 6 '. The insulating film 7 has a thickness of about 4000 to 9000 °, and a plasma TEOS film or an O ₃ -TEOS-NSG film is used.

(5) Next, as shown in FIG. 4B, the insulating film 7 is flattened (for example, by CMP (chemical mechanical polishing)). Therefore, the surface irregularities seen in FIG. 4A are eliminated. That is, the inclined portion of the insulating film at the end of the metal film, which reflects the shape of the metal film underlying the length measurement pattern, also disappears. (6) Next, as shown in FIG. 4C, the first metal wirings 6, 6 'formed in FIG. 3C and the second metal wiring (not shown) generated in the next step are formed. For connection, first via hole contacts 8, 8 'are formed. Here, 8 is a via hole contact for connecting the first metal wiring 6 and a second metal wiring (not shown), and 8 'is a via hole of a length measurement pattern formed for measuring the length of the via hole contact. It is a contact group. The diameter of the via-hole contacts of the first via-hole contacts 8 and 8 'is 3
It is about 000 to 8000.

The SEM length measurement operation after etching the via hole contacts 8 and 8 'is performed by using an electron beam (acceleration voltage: 10) directly above the length measurement pattern shown in FIG.
00 to 1500 V, current: 5 to 10 nA) to capture secondary electrons generated from the irradiated area, process the signal as an electric signal, and then process the CRT.
An SEM image near the length measurement point is displayed on the screen.

Then, in order to specify the length measuring point, the SEM image near the length measuring point is first displayed on the CRT screen at a low magnification of about 100 to 1000 times. Then, after searching and identifying the designated length measuring point, the length measuring operation is performed at the designated magnification (usually about 50,000 to 100,000 times). However, since the unevenness on the surface near the length measurement pattern has been eliminated, FIGS.
As shown in (c), no subtle contrast occurs in the low-magnification SEM image displayed on the CRT screen. Furthermore,
Electrons are captured by the insulating film 7 by irradiation of the electron beam for about several seconds, and a phenomenon called so-called charge-up appears.
In the SEM image on the CRT screen, it is difficult to obtain information on the surface state near the length measurement point on the wafer. Therefore,
A group of length measurement patterns of via holes having minute dimensions cannot be recognized on the CRT screen.

In other words, the flattening process of the wafer eliminates irregularities that should be in the vicinity of the measurement position.
For this reason, there is a problem that a subtle contrast does not appear in the SEM image displayed on the CRT screen, and the length measuring portion itself cannot be recognized by the length measuring person. As a result, a significant stagnation occurred in the SEM length measuring operation in the LSI manufacturing process, and the productivity was greatly reduced.

Further, even if the measurement position can be searched and identified, the contrast of the SEM image is reduced.
It has been difficult to obtain a pattern at the designated length measurement location as a clear SEM image on a CRT screen, and this has reduced the length measurement accuracy. Therefore, it has been difficult to maintain high processing accuracy (dimensional accuracy). This problem occurs more remarkably in the SEM length measurement of the etching of the insulating film in which the charge-up phenomenon is more likely to occur than after the etching of the conductive film in which the charge-up phenomenon is less likely to occur.

Next, the second problem will be described below. As the structure of the LSI becomes more complicated, the number of steps is increasing. In proportion to the increase in the number of steps, S
The number of EM measurement patterns also increases. For this, SEM
The area required for forming a length measurement pattern also increases, and when a length measurement pattern is provided inside an LSI, it has become one of the factors that hinders a reduction in the LSI chip area. In addition, when a length measurement pattern is provided on a scribe line, the required area of the line increases, so that the number of LSI chips that can be mounted on one wafer decreases.

The restrictions on the SEM measurement pattern are as follows:
A configuration that facilitates search and identification of length measurement patterns required for length measurement work, and a structure that maintains stability in process processing
Need to meet one at a time. In order to satisfy this restriction, a plurality of the same patterns are formed at the measurement position. This will be described below with reference to FIG.

FIG. 5 is a diagram showing a state in which a via hole contact group of a conventional length measurement pattern is viewed from directly above. In this figure, reference numeral 7 denotes the surface of the insulating film shown in FIG. Reference numeral 6 'denotes a state in which the same underlying metal film as in FIG. 4C is viewed from directly above. However, since the underlying metal film 6' is covered with the insulating film 7, it is indicated by dotted lines. Also,
Reference numeral 8 'denotes a via hole contact group for measuring the length of the first via hole contact shown in FIG.
Individual via holes are formed.

However, as described in the first problem, in the SEM length measurement operation after the flattening process is performed, it is difficult to even specify the measurement position. Therefore, when such a phenomenon occurs, it is necessary to ensure the convenience of the length measurement work.Therefore, measures such as increasing the occupied area of the length measurement pattern and securing the number of the length measurement patterns as much as possible are taken. Was needed. However, such countermeasures have been one of the factors that hinder LSI miniaturization.

According to the present invention, the above problems can be eliminated, the SEM length measuring operation in the etching step of the insulating film after the flattening process can be facilitated, and the area occupied by the length measuring pattern can be reduced. It is an object to provide a semiconductor device and a method for manufacturing the same.

[0026]

In order to achieve the above object, the present invention provides: [1] In a semiconductor device, an SEM measurement area having a planarized surface over a silicon substrate via an insulating film is provided. The SEM length measurement pattern has a structure in which the length measurement pattern is electrically connected to the silicon substrate.

[2] In the semiconductor device according to the above [1], the SEM measurement area is subjected to a flattening process,
Further, it has a structure in which a second contact hole leading to the underlying conductive film serving as the length measurement pattern is formed. [3] The semiconductor device according to the above [2], wherein the underlying conductive film has a planarized structure.

[4] In the method of manufacturing a semiconductor device, S
Forming a first insulating film on the silicon substrate in the EM length measurement region, forming a first contact hole in the first insulating film communicating with the silicon substrate;
Filling a contact hole and forming a base conductive film on the first insulating film, forming a second insulating film on the base conductive film, and planarizing the second insulating film. A step of performing a process and a step of forming a second contact hole communicating with the underlying conductive film in the second insulating film.

[5] The method of manufacturing a semiconductor device according to the above [4], wherein the step of flattening the underlying conductive film in the step (c) is performed.

[0030]

Embodiments of the present invention will be described below in detail. FIG. 1 shows an LSI showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a manufacturing process of the LSI (No. 1), and FIG. 2 is a cross-sectional view of the manufacturing process of the LSI (No. 2).

(1) First, as shown in FIG. 1A, after forming a gate electrode 13 having an LDD structure on a silicon substrate 11, an insulating film 14 is formed. Here, A indicates an actual circuit pattern formation area, and B indicates a length measurement pattern formation area. Reference numeral 12 denotes a field thermal oxide film. The major difference from the conventional one is that the region B for forming the length measurement pattern is not on the field oxide film 12 but on the silicon substrate 11.

Although it is not particularly necessary to positively implant impurity ions in the region of the silicon substrate 11 where this length measurement pattern is to be formed, active implantation of impurity ions does not pose any problem. (2) Next, as shown in FIG. 1B, similarly to FIG. 3B, a contact hole 1 for electrically connecting the gate electrodes 13 or between the gate electrode 13 and the silicon substrate 11 is formed.
5, 15 'are formed. Here, the difference from FIG. 3B is that the contact hole 15 ′ is also formed in the area B where the length measurement pattern is formed. This contact hole 15 ′ is a contact hole formed for the purpose of connecting the underlying metal film required for the SEM length measurement pattern after via-hole contact etching to the silicon substrate 11, similarly to the contact hole 15. In this embodiment, only one contact hole 15 'is formed, but a plurality of contact holes may be formed.

(3) Next, as shown in FIG.
As in FIG. 3C, the first metal wiring 16 and the underlying metal film 1 are formed.
6 'is formed. The underlying metal film 16 'is connected to the silicon substrate 11 via the contact hole 15' formed in FIG. (4) Next, as shown in FIG. 2A, similarly to FIG. 4A, the first metal wiring 16, the base metal film 16 ', and the second metal wiring formed next An insulating film 17 is formed for the purpose of ensuring insulation from the semiconductor device (not shown).

(5) Next, as shown in FIG. 2B, a flattening process is performed on the insulating film 17 as in FIG. 4B. (6) Next, as shown in FIG. 2C, a via hole contact 18 'is formed. The underlying metal film 16 'of the length measurement pattern of the via hole contact 18' is connected to the silicon substrate 11 via the contact hole 15 '.

When performing the SEM length measurement operation of the length measurement pattern of the via hole contact 18 'having the structure shown in FIG. 2C obtained in this manner, the length measurement location is specified as in the conventional example. For this purpose, an electron beam is applied to the vicinity of the measurement position to capture secondary electrons at the position, and electrical signal processing is performed to display a low-magnification SEM image on a CRT screen.

The underlying metal film 16 'of the length measurement pattern of the via hole contact 18' shown in FIG. 2C is electrically connected to the silicon substrate 11 via the contact hole 15 '. Due to this connection, electrons of the irradiated electron beam that have reached the bottom of the via hole contact 18 'flow into the silicon substrate 11 via the contact hole 15'.

Therefore, a difference occurs between the charged state of the bottom of the via hole contact 18 'and the surface of the insulating film 17 by the irradiated electron beam, and the SE obtained on the CRT screen is obtained.
Contrast appears in the M image. In the case of the length measurement pattern of the contact hole 15 'having the structure shown in FIG. 4C, when the electron beam is irradiated for several seconds, a so-called charge-up phenomenon occurs, and information on the surface state near the length measurement location is obtained. It became difficult to obtain on a CRT screen.

However, by providing the length measurement pattern with a structure as shown in FIG.
Since the bottom of via-hole contact 18 'is electrically connected to silicon substrate 11 via 5',
There is a clear difference in the degree of occurrence of the charge-up phenomenon between the surface of the wide insulating film 17 and the vicinity of the via hole contact.

Accordingly, even in the SEM image at a low magnification, the measurement position can be easily recognized. Furthermore, even in the case of a high magnification measurement magnification, since contrast can be easily obtained,
A clear CRT image of the length measuring section can be obtained, and more accurate length measurement can be performed. In addition, since the SEM length measurement pattern can be easily recognized at a low magnification, search / identification of the length measurement pattern, which is a restriction of the SEM length measurement pattern, can be achieved with a smaller number of length measurement patterns. .

Therefore, the number of patterns required for maintaining the stability in the processing is sufficient for the length measurement pattern (at least one contact hole is sufficient), and the occupied area can be reduced. Become. Further, in the case of forming the second and third via hole contacts, the same effect can be obtained by electrically connecting to the silicon substrate directly or via the conductive portion formed in the previous via hole contact step. .

In the above embodiment, description has been made mainly on the length measurement pattern in the case of the SEM length measurement operation in the via hole contact etching step which is the etching step of the insulating film after the flattening process. However, a similar effect can be expected even when applied to a length-measuring SEM pattern in a wiring process formed after performing a flattening process. Further, the description has been made mainly on ASICs / LSIs represented by logic products. However, as circuit patterns become finer, there is a concern that an electron beam irradiated by a length-measuring SEM may have an adverse effect. Therefore, D
It is expected that the actual measurement of a circuit pattern, such as a RAM, will shift to the measurement of a dummy pattern on a scribe line, for example.

The present invention is not limited to ASIC products, but can be applied to LSIs in general. In addition,
The present invention is not limited to the above embodiments, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0043]

As described above in detail, according to the present invention, the underlying metal film is formed on the silicon substrate by the SEM measurement pattern after the etching of the via hole contact after the planarization process is performed. By electrically connecting,
The following effects can be obtained.

(A) The charge-up phenomenon of the insulating film occurs due to the electron beam. However, since the underlying metal film is electrically connected to the silicon substrate, the charge-up phenomenon occurs on the surface of the wide insulating film and near the via hole contact. There is a difference in the degree of occurrence of, and contrast appears in the SEM image displayed on the CRT screen. By this operation, the search and identification of the SEM length measurement location become easy, and the productivity of the LSI is improved.

(B) Since a contrast appears in the SEM image displayed on the CRT screen, a clear SEM image can be obtained even at a high designated measurement magnification. As a result, an improvement in the length measurement accuracy is expected. (C) Since search and identification of the SEM length measurement pattern can be performed with a small number of length measurement patterns, the area occupied by the relevant portion in the LSI can be reduced. Therefore, LSI
Chip can be reduced.

(D) When a SEM length measurement pattern is provided on a scribe line, a predetermined object can be achieved with a small occupied area, and therefore, a decrease in the number of LSIs that can be mounted on one wafer can be prevented. .

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of an LSI manufacturing process showing an embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of an LSI manufacturing process showing the embodiment of the present invention;

FIG. 3 is a sectional view (part 1) of a conventional LSI manufacturing process;

FIG. 4 is a sectional view (part 2) of a conventional LSI manufacturing process;

FIG. 5 is a diagram showing a state in which a via hole contact group of a conventional length measurement pattern is viewed from directly above.

[Explanation of symbols]

 Reference Signs List A actual circuit pattern formation region B length measurement pattern formation region 11 silicon substrate 12 field thermal oxide film 13 gate electrode 14, 17 insulating film 15, 15 'contact hole 16 first metal wiring 16' base metal film 18, 18 'via hole contact

Claims (5)

[Claims] (A) a SEM length measurement region in which a planarization process is performed above a silicon substrate via an insulating film; and (b) the SEM measurement region.
A semiconductor device having a structure in which a length measurement pattern in an EM length measurement region is electrically connected to the silicon substrate. 2. The semiconductor device according to claim 1, wherein the SEM length measurement region has been subjected to a flattening process, and a second contact hole leading to an underlying conductive film serving as a length measurement pattern has been formed. A semiconductor device having: 3. The semiconductor device according to claim 2, wherein said underlying conductive film has a planarized structure. 4. A step of (a) forming a first insulating film on a silicon substrate in an SEM length measurement region, and (b) forming a first contact hole in the first insulating film that communicates with the silicon substrate. (C) filling the first contact hole and forming a base conductive film on the first insulating film; and (d) forming a second insulating film on the base conductive film. A step of performing a planarization process on the second insulating film; and (e) a step of forming a second contact hole in the second insulating film, which leads to the underlying conductive film. Manufacturing method of a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 4, wherein a step of flattening the underlying conductive film in the step (c) is performed.