CN1838446A - 独立式静电掺杂碳纳米管器件及其制造方法 - Google Patents

独立式静电掺杂碳纳米管器件及其制造方法 Download PDF

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CN1838446A
CN1838446A CNA2006100041079A CN200610004107A CN1838446A CN 1838446 A CN1838446 A CN 1838446A CN A2006100041079 A CNA2006100041079 A CN A2006100041079A CN 200610004107 A CN200610004107 A CN 200610004107A CN 1838446 A CN1838446 A CN 1838446A
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J·U·李
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Abstract

一种用于形成独立式静电掺杂碳纳米管器件的方法和相关联的结构。所述方法包括将碳纳米管设置在基底上以便具有独立部分。形成所述碳纳米管的独立部分的一种方式是去除所述基底的一部分。形成所述碳纳米管的独立部分的另一种方式是将一对金属电极设置在第一基底部分上、去除所述第一基底部分与所述金属电极接近的部分以及将第二基底部分一致地设置在所述第一基底部分上以形成沟槽。

Description

独立式静电掺杂碳纳米管器件及其制造方法
对相关申请的交叉参考
本申请是于2003年10月10日申请的序号为No.10/683,895的美国专利申请的部分继续申请且要求所述专利申请的优先权，所述专利申请的整体内容在此作为参考被引用。
技术领域
本发明主要涉及纳米技术领域。更具体而言，本发明涉及一种用于形成独立式静电掺杂碳纳米管器件的方法和相关联的结构。
背景技术
碳纳米管由于其具有用作纳米级电子器件如二极管、晶体管和半导体电路的可能性而因此近年来已经吸引了大量注意。在结构上，碳纳米管类似于卷成圆筒的碳的六方晶格且可能属于两个品种，即单壁品种和多壁品种，中的一种。这些品种中的任一种可根据其手性(即构象几何)整体或部分地呈现出金属材料或半导体材料行为。
呈现出半导体材料行为的碳纳米管通常使用多种化学方法进行掺杂。换句话说，使用不同的化学品以在碳纳米管中形成p型(空穴多数载流子)区域和n型(电子多数载流子)区域。这导致产生P-N结，当施加适当电压时，所述P-N结发出光线(在发光二极管(“LED”)的情况下)。然而，对碳纳米管进行掺杂的化学方法受到p型区域和n型区域通常不精确定性从而导致纳米级电子器件性能特征减弱的问题的困扰。
因此，所需要的是一种用于形成静电掺杂碳纳米管的方法和相关联的结构，所述静电掺杂碳纳米管具有精确定性的p型区域和n型区域且允许形成具有增强的性能特征的纳米级电子器件如光电二极管、光电探测器、光生伏打器件、传感器和功率器件。
发明内容
本发明的实施例提供了一种包括碳纳米管的静电掺杂碳纳米管器件，所述碳纳米管被设置在基底(substrate)上以使得至少一部分所述碳纳米管是独立的。
本发明的实施例提供了一种包括静电掺杂碳纳米管器件的光生伏达器件。
本发明的实施例提供了一种用于形成独立式静电掺杂碳纳米管器件的方法。所述方法包括在基底上设置碳纳米管。所述碳纳米管具有第一端、第二端和其间的独立部分。
从结合附图提供的对本发明的优选实施例的下列详细描述中将更易于理解这些和其它优点和特征。
附图说明
图1是根据本发明的实施例构造的静电掺杂碳纳米管器件的剖面图；
图2是表示图1中所示的静电掺杂碳纳米管器件的电路图；
图3-图7是示出了根据本发明的实施例的一种用于形成静电掺杂碳纳米管器件的方法的剖面图；
图8是根据本发明的实施例构造的独立式静电掺杂碳纳米管器件的剖面图；
图9是表示图8中所示的独立式静电掺杂碳纳米管器件的电路图；
图10是示出了图8中所示的独立式静电掺杂碳纳米管器件的光生伏达结果的曲线图；
图11-图16是示出了根据本发明的实施例的一种用于形成独立式静电掺杂碳纳米管器件的方法的剖面图；和
图17-图21是示出了根据本发明的实施例的一种用于形成独立式静电掺杂碳纳米管器件的方法的剖面图。
具体实施方式
本发明的所述实施例提供了一种用于形成静电掺杂碳纳米管的方法和相关联的结构，所述静电掺杂碳纳米管具有精确定性的p型区域和n型区域且允许形成具有增强的性能特征的纳米级电子器件如光生伏达二极管、功率器件、光电二极管、光电探测器、发光二极管(“LEDs”)和类似器件。静电掺杂碳纳米管器件的一种具体形式是独立式静电掺杂碳纳米管器件。更具体而言，本发明的实施例提供了使用与多个偏压电极去耦分离的多个掺杂电极的功能。因此，可通过改变多个偏压电极中的每个电极的偏压而精确调节对碳纳米管的掺杂。有利地，所述方法和相关联的结构能够提供具有P-N结、P-I-P结、P-I-N结、N-I-P结、N-I-N结、P-N-P结或N-P-N结的碳纳米管。
参见图1，图中示出静电掺杂碳纳米管器件10包括具有第一端14和第二端16的碳纳米管12。碳纳米管12可以是单壁碳纳米管(“SWCNT”)或多壁碳纳米管(“MWCNT”)。碳纳米管12具有约0.1微米与约10微米之间的长度和约0.4nm与约20nm之间的直径，然而可使用其它适当尺寸。通常，碳纳米管可根据其手性(即构象几何)用作金属材料或半导体材料。本发明的碳纳米管12优选用作半导体材料。碳纳米管12的第一端14被设置在第一金属触点18附近且直接与第一金属触点18电接触。同样地，碳纳米管12的第二端16被设置在第二金属触点20附近且直接与第二金属触点20电接触。第一金属触点18和第二金属触点20分别由Ti、Mo、Au、Cr或相似物制成，且分别具有约0.1微米乘约10微米与约1微米乘约10微米之间的面积或尺寸。通常，可使用提供了与碳纳米管12的第一端14和碳纳米管12的第二端16形成足够电接触的任何尺寸。第一金属触点18和第二金属触点20可分别被设置在碳纳米管12的第一端14和碳纳米管12的第二端16的上面或下面。
第一金属触点18和第二金属触点20被设置在介电材料22的表面上。介电材料22包括SiO2、Si3N4、Al2O3、ZrO2或类似物。第一金属电极24和第二金属电极26被设置在介电材料22内，分别与第一金属触点18和第二金属触点20接近且相隔一定距离。由于这种隔离，因此第一金属电极24被电容性地耦接至碳纳米管12的第一端14且第二金属电极26被电容性地耦接至碳纳米管12的第二端16。第一金属电极24与碳纳米管12的第一端14之间的距离和第二金属电极26与碳纳米管12的第二端16之间的距离优选分别在约2nm与约100nm之间。第一金属电极24和第二金属电极26分别由Mo、Ti、Pt、Au、Cr或类似物制成，且分别具有约0.1微米乘约10微米与约1微米乘约10微米之间的面积或尺寸。有利地，可选择第一金属电极24和第二金属电极26的面积或尺寸以实现第一金属电极24与第二金属电极26之间的所需间隔。该间隔的重要性在下面进行详细描述。第一金属电极24优选与第二金属电极隔开约100nm与约1微米之间的距离。
介电材料22被设置在半导体材料28如Si、SiC或类似物的表面上。另一种可选方式是，介电材料22被设置在金属层28如Al、Cr、Mo、Ti、Pt或类似物的表面上。如上所述，碳纳米管12具有第一端14和第二端16。因此，中心部分30被设置在碳纳米管12的第一端14与碳纳米管12的第二端16之间。在本发明的一个实施例中，一部分半导体材料28被设置在接近碳纳米管12的中心部分30且与其相隔一定距离的位置处，且介电材料22、一部分第一金属电极24和一部分第二金属电极26被设置在半导体材料28与碳纳米管12的中心部分30之间。在本发明的另一个可选实施例中，一部分半导体材料28被设置在接近碳纳米管12的中心部分30且与其相隔一定距离的位置处，且仅介电材料22被设置在半导体材料28与碳纳米管12的中心部分30之间。再一次地，该差别涉及第一金属电极24与第二金属电极26之间的间隔且在下面对其重要性进行详细描述。
参见图2，用于形成静电掺杂碳纳米管器件10的结构(图1)由电路图表示。第一金属触点(“M1”)18被电耦接至碳纳米管12的第一端14且第二金属触点(“M2”)20被电耦接至碳纳米管12的第二端16。相似地，第一金属电极(“VC1”)24被电容性地耦接至碳纳米管12的第一端14且第二金属电极(“VC2”)26被电容性地耦接至碳纳米管12的第二端16。在这方面，VC1 24和VC2 26分别形成第一栅和第二栅。在上述本发明的另一个可选实施例中，通过仅使介电材料22(图1)设置在半导体材料28与碳纳米管12的中心部分30之间，半导体材料(“SI”)28被电容性地耦接至碳纳米管12的中心部分30且形成第三栅，要不然所述第三栅不存在。
在工作中，第一偏压被施加到VC1 24上，导致对碳纳米管12的第一端14进行静电掺杂。同样地，第二偏压被施加到VC2 26上，导致对碳纳米管12的第二端16进行静电掺杂。根据施加的偏压，碳纳米管12的第一端14和碳纳米管12的第二端16可分别被制成p型半导体(空穴多数载流子)或n型半导体(电子多数载流子)。如果碳纳米管12的第一端14被制成p型半导体且碳纳米管12的第二端16被制成n型半导体或情况相反，那么结果是形成P-N结。P-N结可用以形成发光二极管(“LED”)，正如本领域的技术人员众所周知地。对于VC1 24和VC2 26而言，用于形成静电掺杂碳纳米管器件10的结构的优选电压范围在约+/-1V与约+/-30V之间。
在上述本发明的另一个可选实施例中，通过仅使介电材料22设置在SI 28和碳纳米管12的中心部分30之间，SI 28被用以调节对碳纳米管12的中心部分30进行的掺杂。因此，碳纳米管12的中心部分30可被制成p型半导体、I型(本征)半导体或n型半导体。这导致存在如下表1中总结出的多种可能的构造，和对于本领域的技术人员众所周知的多种可能的器件。
 偏压模式  结   器件
 VC1   SI   VC2
 低   ---   低  P-I-P   背对背结
 低   ---   高  P-I-N   发光二极管(“LED”)
 高   ---   低  N-I-P   发光二极管(“LED”)
 高   ---   高  N-I-N   背对背结
 低   高   低  P-N-P   双极结
 高   低   高  N-P-N   双极结
表1.静电掺杂碳纳米管结和器件
参见图3和图4，在本发明的另一个实施例中，一种用于形成静电掺杂碳纳米管器件的方法包括：首先设置如上所述的半导体层28。再一次地，半导体层28包括Si、SiC或类似物。另一种可选方式是，可设置金属层28如Al、Cr、Mo、Ti、Pt或类似物。半导体层28优选具有约1微米与约550微米之间的厚度。使用热氧化物、化学气相沉积电介质、等离子体增强化学气相沉积电介质、低压化学气相沉积电介质或类似物使第一绝缘层40在半导体层28的表面上沉积或生长。第一绝缘层40包括SiO2、Si3N4、Al2O3、ZrO2或类似物。第一绝缘层40优选具有约2nm与约100nm之间的厚度。在第一绝缘层40的沉积或生长之后，金属电极材料在第一绝缘层40的表面上成型和沉积以形成上述第一金属电极24和第二金属电极26。金属电极材料包括Mo、Ti、Pt、Au、Cr或类似物。第一金属电极24和第二金属电极26优选分别具有约10nm与约100nm之间的厚度。
参见图5，随后使用化学气相沉积电介质、等离子体增强化学气相沉积电介质、低压化学气相沉积电介质或类似物使第二绝缘层42在第一绝缘层40的表面上沉积或生长，所述第二绝缘层大体上围绕第一金属电极24和第二金属电极26。第二绝缘层42包括SiO2、Si3N4、Al2O3、ZrO2或类似物。第二绝缘层42优选具有约2nm与约100nm之间的厚度。第一绝缘层40和第二绝缘层42共同形成了上述介电层22。在第二绝缘层42的沉积或生长之后，金属触点材料在第二绝缘层42的表面上成型和沉积以形成上述第一金属触点18和第二金属触点20。金属触点材料包括Ti、Mo、Au、Cr或类似物。第一金属触点18和第二金属触点20优选分别具有约10nm与约100nm之间的厚度。
参见图6，随后例如使用本领域的技术人员众所周知的焊接升离技术使适用于使碳纳米管生长的催化剂材料44在第一金属触点18和第二金属触点20的表面上成型和沉积。催化剂材料44可采取薄膜或纳米颗粒的形式且包括Ni、Fe、Co、Mo、铁硝酸盐中的Al2O3或类似物。催化剂材料44优选具有约0.1nm与约1nm之间的厚度。在将催化剂材料44沉积在第一金属触点18和第二金属触点20的表面上之前，第一金属触点18和第二金属触点20以及介电层22的表面可选择性地涂覆有光致抗蚀剂。该光致抗蚀剂形成了用于沉积催化剂材料44的适当图案且随后被去除。应该注意到，催化剂材料可选择性地被沉积在第一金属触点18和第二金属触点20中仅一个的表面上。在沉积催化剂材料44之后，上述碳纳米管12生长，如图7所示。碳纳米管12优选被对齐使得大体上与介电层22的表面平行。通常，碳纳米管12在约700摄氏度与约1000摄氏度之间的温度下在联接至流动碳(烃)源如甲烷源或乙炔源的化学气相沉积(CVD)管中生长。催化剂材料44在这些温度下形成了多个“岛”且产生碳过饱和。最终，碳纳米管12自这些催化剂岛部生长出来。该工艺对于本领域的技术人员是众所周知的。
参见图8，图中示出了具有碳纳米管112的独立式静电掺杂碳纳米管器件110。该独立式静电掺杂碳纳米管器件110可用于光生伏达器件、传感器和/或功率器件中。当碳纳米管112如图所示悬挂时，所得的二极管具有更理想的行为，且这种构型通常更适用于电子器件且更具体而言适用于光生伏达器件。碳纳米管112具有第一端114和第二端116。碳纳米管112在第一金属触点18与第二金属触点20之间延伸且通过第一端114接触第一金属触点18并通过第二端116接触第二金属触点20。碳纳米管112可以是单壁碳纳米管(“SWCNT”)或多壁碳纳米管(“MWCNT”)。碳纳米管112在物理外观、构造和尺寸上与碳纳米管12(图1)相似。第一金属触点18和第二金属触点20可包括Ti、Mo、Au、Cr或类似物且分别可包括约0.1微米乘约10微米与约1微米乘约10微米之间的面积或尺寸。然而，通常应该意识到，可使用提供了与碳纳米管112的端部形成充分电接触的任何尺寸。第一金属触点18和第二金属触点20可被设置在碳纳米管112的端部114、116上面或下面。
第一金属触点18和第二金属触点20被设置在基底22如介电材料的表面上。介电材料22可由SiO2、Si3N4、Al2O3、ZrO2或类似物形成。第一金属电极24和第二金属电极26被设置在介电材料22内，分别接近第一金属触点18和第二金属触点20且与其相隔一定距离。由于这种隔离，因此第一金属电极24被电容性地耦接至碳纳米管112的第一端114且第二金属电极26被电容性地耦接至碳纳米管112的第二端116。在某些实施例中，第一金属电极24与碳纳米管112的第一端114之间的距离和第二金属电极26与碳纳米管112的第二端116之间的距离分别在约2nm与约100nm之间。第一金属电极24和第二金属电极26分别由Mo、Ti、Pt、Au、Cr或类似物制成，且分别具有约0.1微米乘约10微米与约1微米乘约10微米之间的面积或尺寸。有利地，可选择第一金属电极24和第二金属电极26的面积或尺寸以实现第一金属电极24与第二金属电极26之间的所需间隔。已经对该间隔的重要性进行了详细描述。
介电材料22被设置在底部材料28的表面上。底部材料28可以是由Si、SiC或类似物形成的半导体材料。另一种可选方式是，底部材料28可以是金属层28如包括Al、Cr、Mo、Ti、Pt或类似物的层。在介电材料22中形成沟槽128，由此允许碳纳米管112在该位置处是独立的。当给碳纳米管112加偏压成为P-N结二极管时，使碳纳米管112能够与介电材料22相互独立允许获得增强的发光性能。
具体参见图9，独立式静电掺杂碳纳米管器件110由电路图表示。第一金属触点(“M1”)18被电耦接至碳纳米管112的第一端114且第二金属触点(“M2”)20被电耦接至碳纳米管112的第二端116。相似地，第一金属电极(“VC1”)24被电容性地耦接至碳纳米管112的第一端114且第二金属电极(“VC2”)26被电容性地耦接至碳纳米管112的第二端116。在这方面，VC1 24和VC2 26分别形成第一栅和第二栅。
在工作中，第一偏压被施加到VC1 24上，导致对碳纳米管112的第一端114进行静电掺杂。同样地，第二偏压被施加到VC2 26上，导致对碳纳米管112的第二端116进行静电掺杂。根据所施加的偏压，碳纳米管112的第一端114和碳纳米管112的第二端116可分别被制成p型半导体(空穴多数载流子)和n型半导体(电子多数载流子)。如果碳纳米管112的第一端114被制成p型半导体且碳纳米管112的第二端116被制成n型半导体或情况相反，那么结果是形成P-N结。P-N结可用以形成发光二极管(“LED”)、光生伏达二极管、功率器件、光电二极管、光电探测器或类似器件。对于VC1 24和VC2 26而言，用于形成静电掺杂碳纳米管器件10的结构的优选电压范围在约+/-1V与约+/-30V之间。
单壁碳纳米管为直接禁带半导体且因此一个或多个独立式静电掺杂碳纳米管器件110可用于光生伏达器件、传感器和/或功率器件中。图10示出了单个独立式静电掺杂碳纳米管器件110的光生伏达响应。曲线图中示出了在逐渐更高的照明强度下独立式静电掺杂碳纳米管器件110的电流电压特征的偏移。向第四象限逐渐偏移意味着二极管正在产生更大的功率。
现在参见图11-图16，图中示出了用于形成独立式静电掺杂碳纳米管器件110的工艺步骤。作为初始步骤(图11和图12)，绝缘层40在半导体层28的表面上沉积或生长。可使用热氧化物、化学气相沉积电介质、等离子体增强化学气相沉积电介质、低压化学气相沉积电介质或类似物形成第一绝缘层40。第一绝缘层40可包括SiO2、Si3N4、Al2O3、ZrO2或类似物。第一绝缘层40优选具有约2nm与约1000nm之间的厚度。在第一绝缘层40的沉积或生长之后，金属电极材料在第一绝缘层40的表面上成型和沉积以形成上述第一金属电极24和第二金属电极26。金属电极材料可由Mo、Ti、Pt、Au、Cr或类似物形成。第一金属电极24和第二金属电极26优选分别具有约10nm与约100nm之间的厚度。
参见图13，第二绝缘层42随后在第一绝缘层40的表面上沉积或生长，大体上围绕第一金属电极24和第二金属电极26。可使用化学气相沉积电介质、等离子体增强化学气相沉积电介质、低压化学气相沉积电介质或类似物形成第二绝缘层42。第二绝缘层42包括SiO2、Si3N4、Al2O3、ZrO2或类似物。第二绝缘层42优选具有约2nm与约100nm之间的厚度。第一绝缘层40和第二绝缘层42共同形成上述介电层22。在第二绝缘层42的沉积或生长之后，金属触点材料在第二绝缘层42的表面上成型和沉积以形成上述第一金属触点18和第二金属触点20(图15)。金属触点材料可包括Ti、Mo、Au、Cr或类似物。第一金属触点18和第二金属触点20优选分别具有约10nm与约100nm之间的厚度。
参见图14，随后例如使用本领域的技术人员众所周知的焊接升离技术使适用于使碳纳米管生长的催化剂材料44在第一金属触点18和第二金属触点20的表面上成型和沉积。催化剂材料44可采取薄膜或纳米颗粒的形式且可包括元素如Ni、Fe、Co或Mo，或混合物如铁硝酸盐中的Al2O3或类似物。在一些实施例中，催化剂材料44具有约0.1nm与约1nm之间的厚度。在将催化剂材料44沉积在第一金属触点18和第二金属触点20的表面上之前，第一金属触点18和第二金属触点20以及介电层22的表面可选择性地涂覆有光致抗蚀剂。该光致抗蚀剂用以形成用于沉积催化剂材料44的适当图案且随后被去除。应该注意，催化剂材料44可选择性地被沉积在第一金属触点18和第二金属触点20中仅一个的表面上。
在沉积催化剂材料44之后，上述碳纳米管112生长，如图15所示。碳纳米管112优选被对齐使得大体上与介电层22的表面平行。通常，碳纳米管112在约700摄氏度与约1000摄氏度之间的温度下在联接至流动碳(烃)源如甲烷源或乙炔源的化学气相沉积(CVD)管中生长。催化剂材料44在这些温度下形成了多个“岛”且产生碳过饱和。最终，碳纳米管112自这些催化剂岛部中生长出来。该工艺对于本领域的技术人员众所周知。最终，如图16所示，在介电层22中蚀刻出沟槽128以使得碳纳米管112能够独立。
现在参见图17至图21，图中示出了用于形成独立式静电掺杂碳纳米管器件110的另一种可选方法。作为初始步骤(图17)，绝缘层40在半导体层28的表面上沉积或生长。可使用热氧化物、化学气相沉积电介质、等离子体增强化学气相沉积电介质、低压化学气相沉积电介质或类似物形成第一绝缘层40。在第一绝缘层40的沉积或生长之后，金属电极材料在第一绝缘层40的表面上成型和沉积以形成上述第一金属电极24和第二金属电极26。
参见图18，去除一部分第一绝缘层40以形成改变的第一绝缘层40a。适当的去除工艺包括蚀刻和光刻技术。第一金属电极24与第二金属电极26在蚀刻或光刻工艺过程中可用作掩模。用于蚀刻第一绝缘层40a的适当蚀刻剂材料包括湿性蚀刻剂如用于SiO2的缓冲氧化物蚀刻剂或等离子体干性蚀刻剂。通过蚀刻工艺在第一金属电极24与第二金属电极26之间形成开口区域127。参见图21，第二绝缘层42a随后在蚀刻的第一绝缘层40a的表面上沉积或生长，大体上围绕第一金属电极24和第二金属电极26。第二绝缘层42a与蚀刻的第一绝缘层40a相一致。第二绝缘层42a在开口区域127处的一致性允许在第一金属电极24与第二金属电极26之间形成沟槽128。在第二绝缘层42a的沉积或生长之后，金属触点材料在第二绝缘层42的表面上成型和沉积以形成第一金属触点18和第二金属触点20。
参见图20，随后例如使用本领域的技术人员众所周知的焊接升离技术使适用于使碳纳米管生长的催化剂材料44在第一金属触点18和第二金属触点20的表面上成型和沉积。在将催化剂材料44沉积在第一金属触点18和第二金属触点20的表面上之前，第一金属触点18和第二金属触点20以及介电层22的表面可选择性地涂覆有光致抗蚀剂。该光致抗蚀剂用以形成用于沉积催化剂材料44的适当图案且随后被去除。应该注意，催化剂材料44可选择性地被沉积在第一金属触点18和第二金属触点20中仅一个的表面上。在沉积催化剂材料44之后，上述碳纳米管112生长，如图21所示。
尽管已经仅结合有限数量的实施例对本发明进行了详细描述，但是应该易于理解本发明不限于在此所披露的实施例。而是，本发明可进行修改以包括此前未进行描述但与本发明的精神和范围相称的任何数量的变型、改型、代替物或等效布置。例如，尽管已经根据单个静电掺杂碳纳米管对本发明的实施例进行了描述，但应该意识到静电掺杂碳纳米管12、112的阵列和序列可被布置以形成多种功率器件。此外，尽管已经描述了本发明的多个实施例，但应该理解本发明的多个方面可仅包括一些所述的实施例。因此，本发明不被视作受到前面描述的限制，而仅受到所附技术方案范围的限制。
新的且需要受到美国专利证书保护的技术方案如下。

Claims (10)

1、一种静电掺杂碳纳米管器件(110)，包括碳纳米管(112)，所述碳纳米管被设置在基底(22)上以使得至少一部分所述碳纳米管是独立的。
2、根据权利要求1所述的静电掺杂碳纳米管器件，其中所述基底包括沟槽(128)。
3、根据权利要求1所述的静电掺杂碳纳米管器件，其中所述碳纳米管具有第一端(114)和第二端(116)，所述器件进一步包括：
直接设置在接近所述碳纳米管的所述第一端的位置处的第一金属触点(18)；和
直接设置在接近所述碳纳米管的所述第二端的位置处的第二金属触点(20)，其中所述碳纳米管被电耦接至所述第一和第二金属触点。
4、根据权利要求3所述的静电掺杂碳纳米管器件，进一步包括：
设置在所述基底中且接近所述碳纳米管的所述第一端且与其相隔一定距离的第一金属电极(24)，其中所述第一金属电极被电容性地耦接至所述碳纳米管的所述第一端且可操作以接收第一偏压以对所述碳纳米管的所述第一端进行静电掺杂；和
设置在所述基底中且接近所述碳纳米管的所述第二端且与其相隔一定距离的第二金属电极(26)，其中所述第二金属电极被电容性地耦接至所述碳纳米管的所述第二端且可操作以接收第二偏压以对所述碳纳米管的所述第二端进行静电掺杂。
5、根据权利要求3所述的静电掺杂碳纳米管器件，其中所述第一金属电极和所述第二金属电极分别包括从包括Mo、Ti、Pt和Au的组群中选择出来的金属。
6、根据权利要求3所述的静电掺杂碳纳米管器件，其中所述第一偏压可操作以将所述碳纳米管的所述第一端制成p型半导体(空穴多数载流子)或n型半导体(电子多数载流子)。
7、根据权利要求3所述的静电掺杂碳纳米管器件，其中所述第二偏压可操作以将所述碳纳米管的所述第二端制成p型半导体(空穴多数载流子)和n型半导体(电子多数载流子)中的一种。
8、一种包括根据权利要求1所述的静电掺杂碳纳米管器件的光生伏达器件。
9、一种包括根据权利要求1所述的静电掺杂碳纳米管器件的功率器件。
10、一种包括根据权利要求1所述的静电掺杂碳纳米管器件的传感器。
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