CN1835245A

CN1835245A - Image sensor with embedded photodiode region and fabrication method thereof

Info

Publication number: CN1835245A
Application number: CNA2005101200631A
Authority: CN
Inventors: 井上忠夫; 山本克义; 大川成实
Original assignee: Fujitsu Ltd
Current assignee: Socionext Inc
Priority date: 2005-03-17
Filing date: 2005-11-08
Publication date: 2006-09-20
Anticipated expiration: 2025-11-08
Also published as: JP4224036B2; EP1703564B1; US7417273B2; JP2006261411A; US20060208285A1; KR20060101187A; EP1703564A3; EP1703564A2; KR100758321B1; CN1835245B

Abstract

An image sensor in which a plurality of pixels (PX1, PX2) having at least a photodiode (PD), a reset transistor (RST), and source follower transistor (SF) are formed, wherein each pixel comprises an electrical-charge transfer gate transistor (TG), between the photodiode and reset transistor, and a floating diffusion region (FD) constituting a node connecting the reset transistor and transfer gate transistor which is connected to the gate of the source follower transistor (SF). Further, a photodiode region (PD) is embedded below a well region in which the reset transistor (RST) and source follower transistor (SF) of each pixel are formed. However, no photodiode region is formed below at least part of the floating diffusion region.

Description

Be embedded with the imageing sensor and the manufacture method thereof of photodiode region

The reference of related application

The application based on and require the rights and interests of the No.2005-077237 of Japanese patent application formerly of on March 17th, 2005 application, quote its full content in this mode by reference.

Technical field

The present invention relates to a kind of imageing sensor and manufacture method thereof that is embedded with photodiode region, relate more particularly to a kind of imageing sensor and manufacture method thereof, in this imageing sensor, embed photodiode region so that extend its bottom at transistor formation region.

Background technology

Imageing sensor comprises CCD (charge coupled device), APS (CMOS active pixel sensor) and as the cmos image sensor of APS representative instance.CCD is used in video camera or the like, and cmos image sensor is used in digital camera of low price or the like.In these two kinds of transducers, cmos image sensor can utilize CMOS technology to make, and has low manufacturing cost, owing to compare cmos image sensor with ccd image sensor and consume a spot of electric energy, so cmos image sensor is used in the battery operated device such as mobile phone or portable data assistance.

Cmos image sensor comprises the photodiode as O/E (light /) conversion element, and extracts incident intensity as the signal of telecommunication by reading the quantity of electric charge of assembling in the photodiode by source follower transistor etc.Already used cmos image sensor is three transistor-type imageing sensors, and it comprises photodiode, reset transistor, source follower transistor and selection transistor.In addition, also propose a kind of four transistor-type APS recently, between photodiode and the reset transistor transfer gate transistor is set therein.

In four transistor-type APS, the tie point place between transfer gate transistor and reset transistor is provided with the floating diffusion region (FD) that is made of the diffusion layer that floats.In addition, make by reset transistor after floating diffusion region reaches reset level, the electric charge of assembling in photodiode region is transferred to floating diffusion region, and by making the transfer gate transistor conducting change electromotive force, and the variation of electromotive force is transferred to holding wire via source follower transistor.Electromotive force during the electromotive force by detecting the floating diffusion region reseting period and the transfer of the electric charge in the photodiode poor can be extracted the signal of therefrom having removed noise.

For example, in the open No.2002-16243 of (on January 18th, 2002 is disclosed) Japan special permission three transistor-types and four transistor-type APS are disclosed.

In addition, a kind of five transistor-type APS that add over flow drain(OFD) transistor (overflow drain transistor) in order to prevent overflowing of photodiode have been proposed.By control over flow drain(OFD) transistor, can control the integration start-up time (integral start time) of photodiode, and can realize adopting the panorama shutter system.

Thereby along with the continuous enhancing of performance, (in-pixel) transistorized quantity increases in the pixel, and the ratio of the surface area of photodiode region and elemental area descends, and it causes so-called aperture than descending.In order to address this problem, just propose shared element between neighbor as transistor and so on.

In addition,, also propose a kind of structure, wherein photodiode region is embedded in the pixel under the transistor formation region in order to prevent the aperture than descending.For example, in the open No.2002-16243 of (on January 18th, 2002 is disclosed) Japan special permission this structure is disclosed.

Fig. 1 is the cross-sectional view of disclosed cmos image sensor in the open No.2002-16243 of (on January 18th, 2002 is disclosed) Japan special permission.The grid 61 of the grid 55 of transfering transistor TG, the grid 58 of reset transistor and source follower transistor is formed on the P type epitaxial loayer 52 via

grid oxidation film

56,63 and 64, this P type epitaxial loayer 52 is formed on the P type semiconductor substrate 51, and source area and

drain region

57,59,60 and 62 are arranged on the both sides of grid.In addition, form high concentration N type photodiode region 53, and embed photodiode region 53 so that extend its bottom in transfer gate transistor, reset transistor and source follower transistor from the surface of epitaxial loayer 52 at depth direction.In addition, high concentration P+ district and surface insulating film 54 interval embeddings that photodiode region 53 forms by the surface at epitaxial loayer 52, thus can suppress the dark current that the leakage current by dielectric film 54 causes.

Thereby in the open No.2002-16243 of Japan special permission under the situation of disclosed cmos image sensor, the bottom by transistor formation region in pixel embeds the reduction that photodiode region prevents the aperture ratio with overlap mode, improves light sensitivity thus.

But disclosed cmos image sensor has the N type photodiode region 53 that the whole regional bottom of transistor formation region embeds in pixel in the open No.2002-16243 of Japan's special permission.More particularly, because N type photodiode region 53 is formed directly into the bottom of transfer gate transistor TG and floating diffusion region 57, thus be difficult to keep the threshold voltage vt h of transfer gate transistor TG lower, and the junction capacitance of floating diffusion region 57 is increased.This be because: isolate for the N type photodiode region 53 and surperficial N type source area and the drain region electricity that make embedding, just need to increase the N type photodiode region 53 that embeds and the impurity concentration of the P type epitaxial loayer 52 between surperficial N type source area and the drain region.Because high concentration P type epitaxial loayer, the concentration of the channel region of transfer gate transistor increases, and threshold voltage uprises.When the threshold voltage of transfer gate transistor TG uprised, 57 charge transfer effciency just reduced from photodiode region 53 to floating diffusion region, and caused sensitivity to reduce.In addition, because wherein form P type epitaxial loayer 52 dense of N type floating diffusion region 57, so that the junction capacitance of floating diffusion region 57 becomes is big.When junction capacitance becomes big, just very little with the ratio of the change in voltage of the corresponding floating diffusion region of electric charge that shifts from photodiode region 53, thus cause sensitivity to reduce.

In addition, because in the open No.2002-16243 of Japan special permission in the disclosed cmos image sensor, N type photodiode region 53 is embedded in the bottom of floating diffusion region 57, so such cmos image sensor is not suitable for thisly waiting the structure that improves the aperture ratio by share transfer gate transistor, reset transistor and source follower transistor between neighbor.That is to say that in transistors share type cmos image sensor, the photodiode region of neighbor is shared floating diffusion region 57.But, when the photodiode region 53 of a pixel is arranged on the bottom of floating diffusion region 57, the photodiode region of another pixel can't be arranged on the there, and the shape of the photodiode region of two pixels is just inequality, and the shape of the photodiode of such pixel and next pixel is just inconsistent.This inconsistent detection signal of each pixel that causes is inconsistent, and this is worthless.

Summary of the invention

Therefore, the purpose of this invention is to provide a kind of cmos image sensor and manufacture method thereof, wherein can increase actual aperture ratio, and improve light sensitivity.

To achieve these goals, first scheme of the present invention is a kind of imageing sensor, wherein form a plurality of pixels, described pixel has a photodiode, a reset transistor and one source pole follower transistor at least, wherein, each pixel comprises the electric charge transfer gate transistor, and it and constitutes the floating diffusion region of the node that reset transistor is connected with transfer gate transistor is connected with the grid of this source follower transistor between photodiode and reset transistor.In addition, photodiode region is embedded in the bottom of well region, forms the reset transistor and the source follower transistor of each pixel in this well region.In addition, do not form this photodiode region in the regional bottom of the part of this floating diffusion region at least.

According to this structure, form photodiode region in the bottom of the well region that forms reset transistor and source follower transistor.Therefore, can increase the area of photodiode region, and can the hole diameter enlargement ratio.In addition, do not form this photodiode region in a part of zone of the well region bottom that forms floating diffusion region at least.As a result, need not to increase the impurity concentration of well region, thereby can reduce the junction capacitance of floating diffusion region, and can increase the change in voltage of electric charge, can strengthen the light detection sensitivity thus.

According to first scheme of the present invention, in a preferred embodiment, do not form photodiode region in the regional bottom of the part in transfer gate transistor district at least.For this reason, need not to increase the impurity concentration of well region, thereby can reduce the threshold voltage of transfer gate transistor, and can improve charge transfer effciency.

To achieve these goals, alternative plan of the present invention is a kind of imageing sensor, it comprises a plurality of pixels, each pixel has photodiode, reset transistor and source follower transistor at least, wherein, each pixel comprises the electric charge transfer gate transistor, and it and constitutes the floating diffusion region of the node that reset transistor is connected with transfer gate transistor is connected with the grid of this source follower transistor between photodiode and reset transistor.In addition, photodiode region is embedded in the bottom of well region, forms the reset transistor and the source follower transistor of each pixel in this well region.In addition, the first and second adjacent pixels are shared reset transistor, floating diffusion region and source follower transistor at least, and do not form the photodiode region of described first and second pixels at least in the regional bottom of the part of the floating diffusion region of sharing.

Because this structure, for described first and second pixels, can be identical via the formation of each transfer gate transistor and the described photodiode region of the floating diffusion region connection of sharing, can make the detection signal unanimity between pixel thus.

Under the situation of alternative plan, in the situation of preferred embodiment, on the floating diffusion region of sharing, form optical screen film.Photodiode region is not formed at the bottom at floating diffusion region, therefore, even form optical screen film on floating diffusion region, the reduction of light sensitivity can not take place also.In addition, inject incident light on the floating diffusion region, can suppress noise and append on the detection signal by cut-out.

According to the present invention, the effective aperture of the pixel in imageing sensor ratio increases, and can improve light sensitivity.

Description of drawings

Fig. 1 is the cross-sectional view of disclosed cmos image sensor among the open No.2002-16243 of Japan's special permission:

Fig. 2 is the circuit diagram of four transistor-type APS;

Fig. 3 is the work wave of four transistor-type APS;

Fig. 4 is the circuit diagram of the four transistor-type APS that share;

Fig. 5 is the layout of the pixel of first embodiment;

Fig. 6 is the layout of the pixel of second embodiment;

Fig. 7 A-7C is the detailed placement figure of the pixel of second embodiment;

Fig. 8 is the detailed cross sectional view of the pixel of second embodiment;

Fig. 9 is the cross-sectional view of the operation of second embodiment;

Figure 10 is the cross-sectional view of the operation of second embodiment;

Figure 11 is the cross-sectional view of the operation of second embodiment;

Figure 12 is the layout of the pixel of the 3rd embodiment;

Figure 13 is the layout of the pixel of the 4th embodiment;

Figure 14 is the layout of the pixel of the 5th embodiment;

Figure 15 A-C is the detailed placement figure of the pixel of the 5th embodiment;

Figure 16 is the detailed cross sectional view of the pixel of the 5th embodiment;

Figure 17 is the layout of the pixel of the 6th embodiment;

Figure 18 is the layout of the pixel of the 7th embodiment;

Figure 19 A-C is the detailed placement figure of the pixel of the 7th embodiment;

Figure 20 is the layout of the pixel of the 8th embodiment;

Figure 21 is the cross-sectional view of the pixel of the 9th embodiment;

Figure 22 is the cross-sectional view of the pixel of the tenth embodiment;

Figure 23 is the layout of the pixel of the 11 embodiment;

Figure 24 is the layout of the pixel of the 12 embodiment;

Figure 25 is the layout of the pixel of the 13 embodiment;

Figure 26 A-B is the layout of the pixel of the 14 embodiment; And

Figure 27 is the layout of the pixel of the 15 embodiment.

Embodiment

Below in conjunction with the description of drawings embodiments of the invention.But technical scope of the present invention is not limited to these embodiment, but covers the project that occurs in claim and the equivalent scope thereof.

Fig. 2 is the cross-sectional view of four transistor-type APS.Fig. 2 is illustrated in two pixel PX1 and the PX2 that is provided with in two row one row.Pixel PX1 and PX2 are made up of photodiode PD1 and PD2 and four transistors respectively.These four transistors are: reset transistor RST, and it is connected with resetting voltage VR; Source follower transistor SF, similarly, it is connected with resetting voltage VR; Select transistor SLCT, it is between source follower transistor SF and holding wire SGL; And transfer gate transistor TG, it is arranged between reset transistor RST and the photodiode PD.In addition, transfer gate transistor TG is connected with the negative electrode of photodiode PD.In addition, the node that connects reset transistor RST and transfer gate transistor TG is respectively floating diffusion region FD1 and FD2, and its grid with source follower transistor SF is connected.

Fig. 3 is the working waveform figure of four transistor-type APS.Suppose and select the situation of pixel PX1 to describe.At first, make to high level under the state of selecting transistor SLCT conducting by driving selection wire SLCT1 (Select among Fig. 3), make reset transistor RST conducting by driving reset line RST1 to high level, and floating diffusion region FD1 is reset to reset voltage level VR.Reset level is output to holding wire SGL (Signal among Fig. 3) via source follower transistor SF and selection transistor SLCT as noise signal.Subsequently, when transfer gate transistor TG conducting, the electric charge of being made up of the electronics in the negative electrode that accumulates in photodiode PD is transferred to floating diffusion region FD1, and the voltage of floating diffusion region FD descends.The quantity of electric charge Q that is transferred obtains voltage drop Δ V divided by the parasitic capacitance C of floating diffusion region FD.The level of the floating diffusion region FD that reduces is output to holding wire SGL as detection signal.Level difference Δ V between output circuit (not shown) detected noise signal and the detection signal, and it is exported as the pixel light strength signal.

Like this, in order to increase detected thus detection light intensity signal Δ V, just need improve the O/E conversion efficiency, and reduce the parasitic capacitance C of floating diffusion region FD by the light amount of incident that increases on the photodiode.

Fig. 4 is the circuit diagram of the four transistor-type APS that share.In four transistor-type APS shown in Fig. 2, four transistors are set for each pixel.For this reason, constitute the aperture ratio decline of surface area with the ratio of pixel surface area of photodiode formation.In order to address this problem, in the transducer of Fig. 4, adjacent pixels is shared reset transistor RST, source follower transistor SF and is selected transistor SLCT.If in shared region SHARED, form three transistors, then can be two pixels five transistors are set, that is,, can suppress the decline of aperture ratio thus for each pixel is provided with 2.5 transistors.

Similar among the work of the four transistor-type APS that share and Fig. 3, make under the state of selecting transistor SLCT conducting, by reset transistor RST floating diffusion region FD1 and FD2 are resetted, read noise signal in this state, by make the transfer gate transistor TG conducting of photodiode PD1 by transfer gate signal TG1, read detection signal thus then.In addition, in order to read more picture element signals, repeat identical operations.That is to say that three shared transistors all are used to read the signal of each pixel.

First embodiment

Fig. 5 is the layout of the pixel of first embodiment.First embodiment is corresponding to four transistor-type APS among Fig. 2.Fig. 5 illustrates respectively has the layout of two pixel PX1 and PX2 at top and bottom.Each pixel PX1 and PX2 are isolated from the isolation trench structure STI that (STI) constitutes by shallow trench isolation, for example, each pixel is provided with floating diffusion region FD, transfer gate transistor TG, reset transistor RST, source follower transistor SF and selects transistor SL (being abbreviated as " SL " in layout).Each transistor comprises grid TGg, RSTg, SFg and SLg, shows source electrode and drain electrode with thick frame, and isolation trench structure is shown as " STIp " in the pixel.In addition, the source electrode of transfer gate transistor TG is photodiode region PD.The drain electrode of same transistor T G is corresponding to floating diffusion region FD.

In addition, in each pixel PX1 and PX2, photodiode region PD be formed on do not form floating diffusion region FD and transistorized substrate surface near, and photodiode region PD is embedded in the zone except the bottom of floating diffusion region FD and transfer gate transistor TG.That is to say the bottom that photodiode PD also is embedded in reset transistor RST, source follower transistor SF and selects transistor SL.In this layout, utilize shallow hatching pattern to show photodiode region PD.Its cross-sectional structure describes in detail with (explanation subsequently) second embodiment.

In first embodiment, in the pixel photodiode region PD near being embedded in the substrate surface that does not form transistor etc., the bottom that also is embedded in reset transistor RST, source follower transistor SF and selects transistor SL, thus can the hole diameter enlargement ratio.In addition, shallow hatching pattern PD is not arranged among TG or the FD.That is to say that the photodiode region PD of embedding is not formed on the bottom of floating diffusion region FD and transfer gate transistor TG.Therefore, can reduce to form the impurity concentration of the P type trap of floating diffusion region FD and transistor T G.As a result, the threshold voltage of transfer gate transistor TG can be kept lower, and keep the junction capacitance of floating diffusion region FD very little.

Second embodiment

Fig. 6 is the layout of the pixel of second embodiment.Second embodiment is corresponding to the four transistor-type APS that share among Fig. 4.Fig. 6 also illustrates two pixel PX1 laying respectively at top and bottom and the layout of PX2.For example, each pixel PX1 and PX2 are isolated from the isolation trench structure STI that constitutes by shallow trench isolation.In addition, two pixel PX1 and PX2 share floating diffusion region FD, reset transistor RST, source follower transistor SF and select transistor SL, and two pixels are included in the transfer gate transistor TG on the upper and lower side of shared floating diffusion region FD.In addition, the floating diffusion region FD of Gong Xianging is set on the border between two pixel PX1 and the PX2.

Still in Fig. 6, each transistor comprises grid TGg, RSTg, SFg and SLg.Its source electrode and drain region show with thick frame, and isolation trench structure is shown as STIp in the pixel.The source electrode of transfer gate transistor TG is photodiode region PD.The drain electrode of same transistor T G is corresponding to floating diffusion region FD, and formation is by the shared node of two pixels.

Still in a second embodiment, photodiode region PD be formed on that part of substrate surface that do not form transistor etc. near, and be formed on the bottom that source follower transistor SF, part reset transistor RST and part are selected transistor SL.But photodiode region PD is not embedded in the source area of floating diffusion region FD, transfer gate transistor TG1 and TG2, reset transistor RST and the bottom of selecting the drain region of transistor SL.Because do not embed photodiode region PD, thus the junction capacitance of floating diffusion region FD can be kept lower, and the threshold voltage of transfer gate transistor TG1 and TG2 can be kept lower.In addition, do not form photodiode region FD in the bottom of the source area of the reset transistor RST that is connected with floating diffusion region FD.In addition, for the shape that makes the photodiode region PD in top pixel and the bottom pixel is identical, do not form photodiode region FD in the bottom of the source area of the selection transistor SL of pixel PX2 yet.In addition, remove denoising by forming optical screen film, this optical screen film stops the source area of shared reset transistor RST and selects incident light on the drain region of transistor SL.In detailed view subsequently, show this optical screen film.

Fig. 7 A-C is the detailed placement figure of the pixel of second embodiment.In addition, Fig. 8 is its cross-sectional view.Fig. 7 A illustrates the layout of the structure with all layers except that the 3rd metal level.Fig. 7 B is the layout that isolation trench structure, photodiode region PD and each transistorized polysilicon gate are shown.Fig. 7 C illustrates the layout that shows photodiode region PD and the 3rd metal level M3L.In addition, the left side of Fig. 8 illustrates the cross-sectional view of pixel, and the centre illustrates the cross-sectional view of the periphery of pel array PXARY, and the right side illustrates the cross-sectional view of peripheral circuit.

Illustrate along the cross-sectional view of single-point line A-B among Fig. 7 A-C in the left side of Fig. 8.Basic identical with Fig. 6 of layout among Fig. 7 A-C, just it is arranged on floating diffusion region FD1 in each pixel and FD2 in two upper and lower pixels, and this point is with different with FD2 by polysilicon layer POLY connection floating diffusion region FD1.To illustrate below along the structure of single-point line A-B.

In the cross-sectional view of Fig. 8, point A is positioned on the pixel sides isolation trench structure STI2, thereafter, polysilicon layer POLY is connected with the N type contact zone FDN0 of floating diffusion region FD, and forms polysilicon gate, the first photodiode region PHD1 and the second photodiode region PHD2 of N type light doping section NLD, transfer gate transistor TG among the 3rd P type well region PW3.Here, as shown in Figure 8, photodiode region PD comprises: the N type first photodiode region PHD1, its be formed on substrate surface near, and extend along depth direction; And the N type second photodiode region PHD2, it is embedded in the substrate very darkly.In addition, shown in Fig. 7 A-C, extend on the whole area of the second photodiode region PHD2 in the pixel except the subregion.More particularly, the second district PHD2 is set to the bottom of the bottom of source follower transistor SF, selection transistor SLCT and the regional bottom extension except that the source area of reset transistor RST in pixel respectively.

The bottom of the bottom of floating diffusion region FD1 and FD2 or transfer gate transistor TG1 and TG2 in pixel (the district R1 among Fig. 8) is not provided with the second photodiode region PHD2, and is provided with in the bottom (the district R2 among Fig. 8) of the source area S1 of reset transistor RST yet.The source area S1 of reset transistor RST is connected with floating diffusion region FD via M1C1, and therefore, the not crossover of the second district PHD2 is desirable.Therefore, in lower pixel, select the bottom of a part of region S 2 of transistor SLCT that the second photoelectric crystal area under control PHD2 is not set.As a result, make the shape of the second photoelectric crystal area under control PHD2 of upper and lower pixel identical.

In addition, in the cross section A-B of Fig. 8, there is the N type contact zone FDN be connected with path (via) M1C1, and is provided with gate polysilicon layer and the N type contact zone FDN0 of N type contact zone FDN, the source follower transistor SF of the gate polysilicon layer of reset transistor RST, the path M1C1 that is connected with resetting voltage VR.Do not form the source area S1 of the district R2 of the second photodiode region PHD2 corresponding to Fig. 7 A-C.By the metal line (not shown) source area S1 is connected with floating diffusion region FD.

Shown in the layout of Fig. 7 B, the floating diffusion region FD1 of upper and lower pixel is connected with the grid of source follower transistor SF via polysilicon layer POLY with FD2.In addition, the source area of source follower transistor SF is connected with the drain region of selecting transistor SLCT via polysilicon layer POLY.In addition, select the source area of transistor SLCT to be connected with holding wire SGL via the metal level (not shown).

Shown in the layout of Fig. 7 B, the first and second photodiode region PHD1 and the PHD2 that constitute photodiode region respectively all are provided with at interval with isolation trench structure STI2.This helps to prevent that near the leakage current the isolation trench structure STI2 from flowing as dark current.

Shown in the layout of Fig. 7 C, constitute the gate line of transfer gate transistor TG1 and TG2 and the gate line of selecting transistor SLCT by the first metal layer M1L that extends in the horizontal direction.The first metal layer M1L is connected with two transistorized gate polysilicon layers.In addition, constitute the holding wire SGL that is connected with the source area of selecting transistor SLCT by the second metal level M2L that extends in vertical direction.In addition, form the optical screen film OPS of the 3rd metal level M3L in the pixel in not forming each pixel on the zone of photodiode region PHD1 and PHD2.More particularly, by optical screen film OPS is set on floating diffusion region FD1 and FD2, can prevent because the generating noise that the incident light on floating diffusion region FD1 and the FD2 causes.In addition, also on the source area S1 of the reset transistor RST that is connected with floating diffusion region FD1, form the optical screen film OPS of the 3rd metal level M3L, similarly, on the source area S2 that selects transistor SLCT, form optical screen film OPS similarly.The optical screen film OPS of the 3rd metal level also is set on the outer peripheral areas between the pixel in addition.This helps suppressing crosstalking between pixel.

The optical screen film OPS of the 3rd metal level among Fig. 7 C has the shape that is the line symmetry with respect to the boundary line of upper and lower pixel.As a result, incident light is incident on the upper and lower pixel of extending on the identical table area, can eliminate the inconsistent of detection signal between two pixels thus.Shown in the cross-sectional view among Fig. 8, optical screen film OPS is positioned on the district R1 that forms floating diffusion region FD and transfer gate transistor TG.

In addition, shown in the cross-sectional view of the layout of Fig. 7 A and Fig. 8, between the first photodiode region PHD1 and substrate surface, form high concentration P type blind zone P+shield.Because this blind zone the silicon oxide film of substrate surface and the first photodiode region PHD1 are isolated, and photodiode region is by all embedding.By isolating the silicon oxide film of photodiode region and substrate surface, can suppress the dark current of the leakage current of silicon oxide film.

Under the situation of first embodiment shown in Figure 5, floating diffusion region FD and transistor RST, SF and SLCT are set in two pixel PX1 and PX2.But, identical among its cross-sectional structure and Fig. 8.That is to say, constitute photodiode region by near first photodiode region PHD1 of the N type the substrate surface and the N type second photodiode region PHD2 that is embedded in the substrate, and the second photodiode region PHD2 also is embedded under transistor RST, SF and the SLCT, but is not arranged on the bottom of floating diffusion region FD and transfer gate transistor TG.In others, the cross-sectional structure of this structure and second embodiment is basic identical.

The technology of second embodiment

Fig. 9 to Figure 11 is the cross-sectional view that the operation of second embodiment is shown, and it describes the structural manufacturing process of imageing sensor.By the description of manufacturing process, it is clearer that the structure of imageing sensor will become.

In the technology (b) of Fig. 9, in the surface of P type silicon substrate P-Sub, in peripheral circuit region and pixel region, form element isolation zone STI1 and STI2 respectively.More particularly, in peripheral circuit part, the etching of about 400nm on silicon substrate, and in pixel region, the etching of about 200nm on silicon substrate.Form silicon oxide film by the high concentration plasma CVD, carry out chemistry and mechanical polishing, and in etched groove, imbed silicon oxide film, to form component isolation structure STI1 and STI2.Here, in pixel region, form component isolation structure STI2 than the more shallow degree of depth of peripheral circuit region, the degree of depth that this means the second photodiode region PHD2 that forms in the bottom of reading transistor (read transistor) in the step that will make subsequently in pixel is shallow as much as possible, improves light sensitivity thus.

In the technology (c) of Fig. 9, the ion of carrying out a P type well region PW1 in peripheral circuit region injects.At first, by the energy, 3 * 10 of boron, 300keV ¹³Cm ^-2The concentration and the ion at 0 degree inclination angle inject the degree of depth and form P type well region PW1-1.In order to reduce the resistance of substrate, the P type well region PW1 that forms the N channel transistor of peripheral circuit must have about 3 * 10 ¹³Cm ^-2High impurity concentration.In addition, by the energy, about 5 * 10 of boron, 30keV ¹²Cm ^-2Concentration and the ion at 7 degree inclination angles inject, in peripheral circuit part, form shallow P type well region PW1-2.For the threshold voltage vt of the N channel transistor of controlling peripheral circuit, carry out ion and inject.

On the other hand, by the energy, 3 * 10 of phosphorus P, 600keV ¹³Cm ^-2Concentration and the ion at 0 degree inclination angle inject and the energy of arsenic AS, 160keV, 2 * 10 ¹³Cm ^-2To 3 * 10 ¹³Cm ^-2Concentration and the ion at 7 degree inclination angles inject, form the N type well region (not shown) of peripheral circuit.

In addition, form the 2nd P type well region PW2 of pixel portion.Energy, 3 * 10 by boron, 80keV ¹³Cm ^-2Concentration and the ion at 7 degree inclination angles inject to form the 2nd P type well region PW2.In addition, the ion of not carrying out the 2nd P type well region PW2 in the bottom of the floating diffusion region FD of the grid of transfer gate transistor TG and pixel portion injects.In addition, realize that this ion injects the injection employed energy of the energy of use less than a P type well region PW1-1 who realizes first peripheral circuit part, thereby the 2nd P type well region PW2 forms more shallowly than a P type well region.As a result, can form the second photodiode region PHD2 that forms subsequently more shallowly.

In addition, the ion that carries out the 2nd P type well region PW2 injects, to read transistorized threshold voltage vt in the control pixel.

In addition, by the energy, 2 * 10 of boron, 30keV ¹²Cm ^-2Concentration and the ion at 7 degree inclination angles inject, for photodiode PD, transfer gate transistor TG and floating diffusion region FD in the pixel form special-purpose the 3rd P type well region PW3.Form the 3rd P type well region PW3 by injecting boron with such concentration, this concentration be peripheral circuit N channel transistor in the first well region PW1 of preceding formation threshold value control concentration half or less than half, reduce the threshold voltage vt of transfer gate transistor TG thus.By reducing the threshold voltage vt of transfer gate transistor TG, can improve charge transfer effciency from photodiode PF to floating diffusion region FD.Simultaneously, be higher than substrate concentration, increase the electron potential of the channel part of transfer gate transistor TG, and then increase the saturation charge of photodiode PD by the concentration that makes the 3rd P type well region PW3.In addition, the 3rd P type well region PW3 has the lower impurity concentration than the 2nd P type well region PW2, therefore, the threshold voltage of transfer gate transistor can be controlled at low level.

The ion that technology among Figure 10 (d) is carried out in order to form the first photodiode region PHD1 in the pixel region injects.Ion injects and comprises the energy, 1 * 10 that utilizes phosphorus P, 207keV ¹²Cm ^-2To 2 * 10 ¹²Cm ^-2Concentration and the ion at the 7 degree inclination angles energy, 1 * 10 that injects and utilize phosphorus P, 135keV ¹²Cm ^-2To 2 * 10 ¹²Cm ^-2Concentration and the ion at 7 degree inclination angles inject.Because this ion injects, will make the 3rd P type well region PW3 inoperative (negated) that early forms, and form shallow district the one N type diffusion region PHD1 that constitutes photodiode PD.

Subsequently, has the mask against corrosion of opening by use, by the energy, 1 * 10 of phosphorus P, 325keV ¹²Cm ^-2To 5 * 10 ¹²Cm ^-2Concentration and the ion at 7 degree inclination angles inject to form the 2nd N type diffusion region PHD2 (dark photodiode), this mask against corrosion and the first photodiode region PHD1 crossover and extend to the bottom of district PHD1 isolation structure STI2 on every side.This just becomes the second photodiode region PHD2.The zone that ion injects is as shown in top layout.In pixel region, isolation structure STI2 forms more shallowly, and forms more shallowly than the 2nd P type well region PW2.Therefore, can make the degree of depth of the second photodiode region PHD2 more shallow relatively.

In the technology in Figure 10 (e),, on substrate surface, form the grid oxidation film GOX of about 8nm, and on grid oxidation film GOX, generate the polysilicon film POLY of about 180nm by CVD by about 800 ℃ thermal oxidation.In addition, on the polysilicon film of the polysilicon film of the N of peripheral circuit channel transistor part and pixel, utilize the energy, 4 * 10 of phosphorus P, 20keV ¹⁵Cm ^-2Concentration and 7 degree inclination angles carry out ions and inject, and by carrying out about 60 minutes annealing down at 800 ℃, polysilicon membrane-coating admixture impurity is to become N type polysilicon film.Form grid by patterned polysilicon film POLY then.

Subsequently, in the technology (f) of Figure 10, in the N of peripheral circuit channel transistor part and pixel, utilize grid, utilize the energy, 4 * 10 of phosphorus, 20keV as mask ¹³Cm ^-2Concentration and 0 degree inclination angle carry out ion and inject (LDD: lightly doped drain injects), form source electrode and drain region NLD thus.

Subsequently, in forming pixel on the substrate surface of the first photodiode region PHD1, by the energy, 1 * 10 that utilizes boron, 10keV ¹³Cm ^-2Concentration and 7 degree inclination angles carry out ions and inject and form this structure: form shielding diffusion layer P+shield in this structure, and embed the n type diffused layer PHD1 of photodiode PD.That is to say that the first photodiode region PHD1 is a kind of like this structure: the oxide film spacer of itself and substrate surface is opened, and can suppress because the dark current that the leakage current of oxide-film causes.

Because this structure, the degree of depth of the light receiving area of formation photodiode is as follows.In the first photodiode region PHD1, form diffusion layer PHD1 at place, shallow district near substrate surface, therefore, the depletion layer of photodiode extends to the dark side of substrate from the degree of depth of the about 0.1 μ m of shallow side.On the one hand, in the second photodiode region PHD2, the 2nd P type well region PW2 has the degree of depth of about 0.3 μ m, therefore, the depletion layer of the second photodiode region PHD2 extends to the dark side of substrate from the degree of depth of the about 0.4 μ m of shallow side, and extends to the about 1.0 μ m of dark side.That is to say that the first photodiode region PHD1 is 0.1-0.4 μ m, and the second photodiode region PHD2 is 0.4-1.0 μ m.

Therefore, when each light launching curve in the silicon near the time, the light sensitivity of the first photodiode region PHD1 (per unit area) approximately reaches ruddiness 65%, green glow 58%, blue light 36% with the ratio of the light sensitivity of the second photodiode region PHD2 (per unit area) only.On the other hand, shallow the 2nd P type well region PW2 in the replacement pixels district and form a dark P type well region PW1 and form under the situation of the similar second photodiode region PHD2 in the bottom of a dark P type well region PW1, the second photodiode region PHD2 are greatly about the degree of depth of 1.0-1.4 μ m.In this case, compare with the situation of shallow PHD2, the light sensitivity of the second photodiode region PHD2 (per unit area) is ruddiness 55%, green glow 48%, blue light 14%.That is to say, according to this embodiment, can understand: when the second photodiode region PHD2 was embedded in the bottom of shallow the 2nd P type well region PW2, light sensitivity can improve more significantly.

In the technology (g) of Figure 10, on the grid of peripheral circuit part, form sidewall SW.Thus, the silicon oxide film by thermal oxidation formation 100nm forms the resist layer that covers transistor, photodiode PD and floating diffusion region FD in the pixel, and utilizes this resist layer as the whole surface execution etching of mask to silicon oxide film.As a result, forming sidewall SW to the grid wiring of pixel region and peripheral circuit transfer gate transistor partly and to the grid place in the grid wiring of pixel region and peripheral circuit reset transistor partly.In addition, in pixel, keep sidewall oxidation silicon fiml SW-SIO.

Subsequently, in pixel, utilize on the source electrode of the source electrode of reset transistor RST and drain region and source follower transistor SF and the drain region phosphorus P, 15keV energy, reach 2 * 10 ¹⁵Cm ^-2The high concentration contact zone FDN of concentration, carry out N type ion and inject, to form contact.

In the technology (h) of Figure 11,, utilize the energy, 2 * 10 of phosphorus P, 13keV in order in the N of peripheral circuit channel transistor district, to form high concentration source electrode and drain region NSD ¹⁵Cm ^-2The concentration and the inclination angles of 7 degree carry out ion and inject.In addition, in hydrofluoric acid HF, handle after the surface of silicon, form cobalt Co, and on the silicon face of source electrode and drain region NSD and grid, form cobalt silicide CoSi by the rapid thermal annealing that reaches 520 ℃ by sputter.In addition, remove unreacted cobalt film on the silicon oxide film, and execution reaches 840 ℃ rapid thermal annealing.

In the technology (i) of Figure 11, form dielectric film, and form contact hole.At first, will be formed up to about 20nm, and will be formed up to about 70nm by the silicon nitride film PSIN that plasma CVD forms by the silicon oxide film P-SIO that plasma CVD forms.To on two-layer dielectric film, be formed up to about 1000nm by the silicon oxide film HDP-SIO that HDP-CVD (high-density plasma CVD) forms, and polishing makes smooth surface by CMP.In addition, be used for carrying out the district PDN formation contact hole M1C1 that contact is injected in the pixel.In addition, be formed for the contact hole of P type well region PW2 in the pixel and the contact hole M1C2 in the peripheral circuit.Simultaneously, also be formed for the contact hole M1C2 of P type well region PW1.In addition, contact hole M1C2 is the contact hole that is used for forming therein the zone of (early forming) cobalt silicide CoSi, and silicide becomes etching stopping layer.Therefore, realize forming process by the technology that is different from contact hole M1C1.

In the technology (j) of Figure 11, form titanium Ti (reaching 30nm) and titanium nitride TiN (reaching 50nm) by after the opening of contact position, carrying out sputter, and, embed contact hole thus by CVD deposits tungsten W film (reaching 300nm); Remove the trilamellar membrane Ti/TiN/W on surface by the CMP polishing; And in contact hole, form the tungsten plug.Subsequently, sputtered film deposition and the photoetching process by Ti (reaching 30nm)/TiN (reaching 50nm)/Al (reaching 400nm)/Ti (reaching 5nm)/TiN (reaching 50nm) forms the first metal line M1L.

In addition, deposition and the CMP by HDP plasma oxide film HDP-SIO (reaching 750nm) and plasma oxide film P-SIO (reaching 1100nm) polishes the interlayer dielectric that is formed on the first metal line M1L.In interlayer dielectric, form path Via1, and form the W plug and the second metal line M2L among the path Via1 by the technology identical with W plug that is formed for contacting and the technology that forms first metal line.

In addition, form the 3rd metal line M3L, to make optical screen film OPS.In the zone as shown in Fig. 7 C, form optical screen film OPS.Form coverlay COV at last, shown in Fig. 9 (a), on coverlay COV, form optical color filter OCF and microlens MLZ.

As mentioned above, by constituting photodiode region near first district PHD1 that extends at depth direction the substrate surface and the second district PHD2 that is positioned at the bottom that forms the transistorized P type of pixel well region PW2.The second district PHD2 is not arranged on the bottom of floating diffusion region FD and transfer gate transistor TG.In addition, the P type well region PW3 that forms floating diffusion region FD and transfer gate transistor TG has lower concentration, reduces to distinguish the junction capacitance of FD thus, and can make the threshold voltage of transistor T G lower than other transistorized threshold voltage.

The 3rd embodiment

Figure 12 is the layout of the pixel of the 3rd embodiment.Second embodiment of image pattern 6 is the same, and two upper and lower pixel PX1 and PX2 share floating diffusion region FD and transistor RST, SF and SL.The difference of the 3rd embodiment and second embodiment is: the photodiode region PD that does not form shallow hatching pattern in the bottom of source follower transistor SF, on pixel boundary line BNDRY, source follower transistor SF is set, and upper and lowerly in the boundary line reset transistor RST is set and selects transistor SL.Because photodiode region PD (PHD2) is not arranged on the bottom of source follower transistor SF, so can reduce the substrate bias effect of photodiode region PD to the P type well region PW2 of the channel region of transistor formed SF.

In addition, the layout of transistor T G, RST, SL and SF has the line symmetrical structure with respect to boundary line BNDRY, and pixel layout is consistent, and can eliminate the inconsistent of detection signal.Remaining structure is identical with the structure of second embodiment.

The 4th embodiment

Figure 13 is the layout of the pixel of the 4th embodiment.In this layout, isolation structure STI along the right among the first pixel PX1 is provided with floating diffusion region FD, transfer gate transistor TG1, source follower transistor SF and selects transistor SL, and along the isolation structure STI on the right among the second pixel PX2 floating diffusion region FD, transfer gate transistor TG2 and reset transistor RST is set.That is to say that similar with second embodiment, two pixels are shared floating diffusion region FD and transistor RST, SF and SL.

In addition, in the zone except the lower area of floating diffusion region FD and transfer gate transistor TG1 and TG2, photodiode region PD is set.In addition, do not form photodiode region PD in the bottom of the source area of reset transistor RST.In addition, share by being connected to each other of metal line etc. or shared each pixel in floating diffusion region FD.

The advantage of this layout is that the layout of upper and lower pixel does not have the line symmetrical structure, and has essentially identical shape.Therefore, even directivity is arranged in technology is inconsistent, inconsistent between the pixel also is identical.

The 5th embodiment

Figure 14 is the layout of the pixel of the 5th embodiment.In this layout, on pixel boundary line BNDRY, source follower transistor SF, reset transistor RST and selection transistor SL are positioned at a row, and they are isolated by three isolation structure STI on the BNDRY of boundary line.In addition, in the zone that forms photodiode region PD, do not form isolation structure STI.That is to say that the floating diffusion region FD that shares between pixel and transistor SF, RST and SL are arranged on the BNDRY of boundary line, and transfer gate transistor TG1 and the TG2 that provides separately in each pixel is set near the upper and lower part of floating diffusion region FD.

The buried region PHD2 that constitutes photodiode region PD not with isolation structure STI crossover, therefore, can eliminate near the influence of the leakage current that isolation structure STI, produces, and can suppress dark current.Photodiode region PD is the line symmetrical structure with respect to the boundary line BNDRY that plants between them and arranges.In addition, photodiode region PD is not arranged on the bottom of the source area of district FD, transistor T G1 and TG2 and reset transistor RST.

Figure 15 A-C is the detailed placement figure of the pixel of the 5th embodiment.Similar with Fig. 7 A-C, Figure 15 A illustrates the layout that shows the structure with all layers except the 3rd metal level.Figure 15 B is the layout that isolation trench structure, photodiode region PD and each transistorized polysilicon gate are shown.Figure 15 C illustrates the layout that shows photodiode region PD and the 3rd metal level M3L.

Similar to Figure 14, on the boundary line of upper and lower pixel, arrange shared floating diffusion region FD, source follower transistor SF, reset transistor RST and select transistor SL.But floating diffusion region FD is arranged in each pixel, and shares by being connected by polysilicon layer.As shown in detailed view 15B, the isolation structure STI of isolated transistor is set on the boundary line, and the described embedding second photodiode region PHD2 is not set in the bottom of isolation structure STI.In addition, in a part of regional bottom of selecting transistor SLCT and source follower transistor SF the second photodiode region PHD2 is set also.In addition, utilize a plurality of square frames to show the second photodiode region PHD2, form the second photodiode region PHD2 but in fact inject by identical ion.

Figure 16 is the detailed cross sectional view of the pixel of the 5th embodiment, and is the cross-sectional view along A-B line among Figure 15 A-C.From cross-sectional view obviously as can be known, the embedding second photodiode region PHD2 not with pixel in isolation structure STI crossover.In addition, in the regional bottom of the part of floating diffusion region FD, transfer gate transistor TG and source follower transistor SF the second photodiode region PHD2 is not set.

The 6th embodiment

Figure 17 is the layout of the pixel of the 6th embodiment.The layout difference of this layout and Figure 14 is: the bottom at source follower transistor SF does not embed photodiode region PD.Other local layout is identical.

The 7th embodiment

Figure 18 is the layout of the pixel of the 7th embodiment.In this layout, floating diffusion region FD and source follower transistor SF are set above the BNDRY of boundary line, and reset transistor RST are set and select transistor SL along the left side of pixel.As a result, pixel width W D is transversely narrowed down, thus, in pixel, only form isolation structure STIp.

In addition, do not embed photodiode region PD in the raceway groove bottom of source follower transistor SF.As a result, can suppress substrate bias effect, can eliminate the fluctuation of threshold value, and can exempt inconsistent in the detection signal transistor SF.

Figure 19 A-C is the detailed placement figure of the pixel of the 7th embodiment.Shown in Figure 19 C,, the optical screen film OPS of the 3rd metal line M3L is set on the zone that floating diffusion region FHD1 and FHD2 are not provided also except being provided with on the floating diffusion region FD.

The 8th embodiment

Figure 20 is the layout of the pixel of the 8th embodiment.In this layout, floating diffusion region FD and source follower transistor SF are set on the BNDRY of boundary line, and source follower transistor SL and reset transistor RST are set along the left side of the pixel of the upper and lower of source follower transistor SF.Arrange transistor SL and RST by upper and lower part, pixel width W D is transversely further narrowed down at transistor SF.Perhaps, can increase the surface area of floating diffusion region FD and source follower transistor SF etc.

The 9th embodiment

Figure 21 is the cross-sectional view of the pixel of the 9th embodiment.The layout of second embodiment among the layout of pixel and Fig. 6 is identical.But, as shown in this cross-sectional view, P type blind zone is not set between the first photodiode region PHD1 and substrate surface.In addition, on the both sides of transfer gate transistor TG, form N type lightly mixed drain area NLD.Because there is not P type blind zone,, thus, can improve the transfer efficiency of transfer gate transistor TG near grid so lightly mixed drain area NLD is set.

As shown in figure 21, if use the structure that does not need to embed fully photodiode region PHD1 and PHD2 by isolating with substrate surface, then also can be with this structure applications in three transistor-type APS.Three transistor-type APS have such structure: the transfer gate transistor of four transistor-type APS wherein is not provided, and the negative electrode (N type district) of photodiode PD is used as floating diffusion region, wherein negative electrode is connected with reset transistor.

The tenth embodiment

Figure 22 is the cross-sectional view of the pixel of the tenth embodiment.The layout of second embodiment among the layout of pixel and Fig. 6 is identical.But this cross-sectional structure has such structure: wherein by silicon oxide film SIO in the substrate P type well region PW2 that forms transistor RST and SF is separated with the embedding second photodiode region PHD2.As a result, the P type well region PW2 of formation transistor RST and SF just can not be subjected to influence of electric potential and the substrate bias effect of the second photodiode region PHD2.Therefore, can suppress the fluctuation of the threshold voltage of transistor RST and SF.Thereby, suppress the fluctuation of the threshold voltage of transistor RST, SF and SLCT according to the quantity of electric charge assembled among the photodiode region PHD2, can improve the accuracy of detection signal thus.

Carry out the method that ion injects by depths, bottom at substrate surface, and as shown in figure 22, go up the method that the substrate S UB2 of formation silicon oxide film SIO is pasted together by forming transistorized substrate S UB1 and its surface, can form silicon oxide film SIO in the substrate.

The 11 embodiment

Figure 23 is the layout of the pixel of the 11 embodiment.In the 11 embodiment, four adjacent pixels PX1 to PX4 share transistor RST, SF and SL, and shared floating diffusion region FD.Floating diffusion region FD on the boundary line of shared pixel PX1 of pixel PX1 and PX2 and PX2, and each transfer gate transistor TG1 and TG2 of the setting of floating diffusion region FD upper and lower part.In addition, in pixel PX1, provide reset transistor RST and source follower transistor SF.In addition, pixel PX3 and PX4 share the floating diffusion region FD on the boundary line between pixel PX3 and the PX4, and each transfer gate transistor TG3 and TG4 of the setting of floating diffusion region FD upper and lower part.In addition, in pixel PX4, provide selection transistor SL.

Still in this embodiment, the photodiode region PD in each pixel is arranged on the place except the bottom of floating diffusion region FD and transfer gate transistor TG.But photodiode region PD is not arranged on the source area bottom of the reset transistor RST that is connected with floating diffusion region FD.

In this embodiment, in having the pattern of point symmetry structure, form photodiode region PD in four pixels.That is to say that the district PD of pixel PX1 and PX4 is of similar shape, the district PD of pixel PX2 and PX3 is of similar shape.Bayer array (Bayer-array) filter is provided on each pixel.Because the district PD of pixel PX1 and PX4 is narrower, all be green G so district PD goes up the filter that forms.On the other hand, blue B or red R filter are set on pixel PX2, red R or blue B filter are set on pixel PX3.Because compare with other color, the light transmittance of green G filter is higher usually, thus for the equilibrium of other color B and R, preferably, green G filter is set on pixel PX1 with narrower photodiode region and PX4.Filter such as blue B or red R filter with low-transmittance is set on pixel PX2 with broad photodiode region and PX3.

The 12 embodiment

Figure 24 is the layout of the pixel of the 12 embodiment.The layout of the 11 embodiment is basic identical among this layout and Figure 23, just the array difference of RGB filter.In this example, green G filter is set on pixel PX2 and PX3, red R or blue B filter are set on pixel PX1 and PX4.By green G filter is set on pixel PX2 with broad photodiode region PD and PX3, can improve the light sensitivity that luminance signal is applied the green of maximum effect, and can make full use of the characteristic of Bayer array.More particularly, can improve brightness value when dark image occurring.

The 13 embodiment

Figure 25 is the layout of the pixel of the 13 embodiment.In this layout, also share transistor by four pixels.But the layout of the pixel PX1 of the 4th embodiment and PX2 is identical among the layout of pixel PX1 and PX4 and Figure 13, just is provided with floating diffusion region FD and transfer gate transistor TG on pixel PX2 and PX3.That is to say, in each pixel, form each floating diffusion region FD, and the connection by the wiring (not shown) is shared each floating diffusion region FD or shared.

This layout example does not have point symmetry structure, and the photodiode region of first to fourth pixel is arranged on the equidirectional of same relatively each transfer gate of pixel.When occur handling in the horizontal direction when inconsistent, each pixel obtains identical repugnancy, and unbalanced between pixel can not taken place.In addition, under the situation of the filter of Bayer array, for example pixel PX1 and PX4 are green G, and pixel PX2 and PX3 are blue B or red R.Perhaps, pixel PX1 and PX4 can be blue B or red R, and pixel PX2 and PX3 can be green G.

The 14 embodiment

Figure 26 A-B is the layout of the pixel of the 14 embodiment.Figure 26 A illustrates the optical screen film pattern in the middle of the pel array, and Figure 26 B illustrates the optical screen film pattern in the pel array periphery.Because light is near injecting directly over the pixel at pel array center, so for layout in the substrate (in-substratelayout), form optical screen film OPS with identical pattern.That is to say, shown in Figure 26 A, directly over the source area of floating diffusion region FD, transfer gate transistor TG and reset transistor RST, optical screen film OPS is set.On the other hand, the center of light in the periphery of pel array tilts to inject, and therefore, optical screen film OPS also is arranged on than layout in the substrate further on the position of off-centring.That is to say that shown in Figure 26 B, the optical screen film OPS of the pixel of upper right edge is set to offset downward towards the left side.But according to layout in the substrate, contact patterns CNT is not set to offset downward towards the left side.

The 15 embodiment

Figure 27 is the layout of the pixel of the 15 embodiment.In this embodiment, apply the present invention to five transistor-type APS, over flow drain(OFD) transistor OFD wherein is provided in pixel.Therefore, each pixel comprises floating diffusion region FD, transfer gate transistor TG, reset transistor RST, source follower transistor SF, selects transistor SL and over flow drain(OFD) transistor OFD.In addition, photodiode region PD also is embedded in the transistorized bottom except the bottom of floating diffusion region FD and transfer gate transistor TG.

In addition, under the situation of five transistor-type APS, between the cathode terminal of photodiode PD and reset voltage line, over flow drain(OFD) transistor OFD is set.By making transistor OFD conducting obtain electric charge from cathode terminal through the opto-electronic conversion of photodiode PD, and by making the not conducting of transistor OFD can be with accumulation at cathode terminal.Therefore, can control pel array all pixels the time of integration startup regularly, that is, provide so-called panorama shutter function.Thereby, even transistorized quantity increases in the pixel, because photodiode region PD can extend to transistorized bottom in the pixel, so also can avoid the reduction of aperture ratio.

The foregoing description has illustrated by common ion injection method and need not to adhere to using manufacture method to make the example of the cross-sectional structure of being made up of transistor and photodiode.That is to say, can set up this cross-sectional structure by having wafer 1 that is used for transistorized structure than shallow portion and the method that wherein is pasted together by the wafer 2 that utilizes SOI (silicon on the insulator) technology for applying that dark PD part is set.In this case, by alternative condition suitably, can infer those cross sections that draw as among Fig. 8, Figure 16 and Figure 22 at an easy rate.

In addition, when using the SOI technology for applying, in the photodiode region of transistor formation region bottom, between the photodiode region of transistor formation region and bottom, keep dielectric film such as oxide-film, and can infer the fact that to strengthen the insulation between the photodiode of transistor AND gate bottom at an easy rate.In addition, substitute the SOI technology for applying, also can realize this structure by utilizing SIMOX technology (annotating oxygen isolates).

Claims

1, a kind of imageing sensor, it has a plurality of pixels, and each pixel has a photodiode, a transfer gate transistor, a reset transistor and one source pole follower transistor at least,

Wherein, in described pixel, floating diffusion region constitutes the node that this transfer gate transistor is connected with this reset transistor, and is connected with the grid of this source follower transistor; And

Described pixel comprises photodiode region, and it is embedded in the bottom of this reset transistor and this source follower transistor, does not form this photodiode region in the regional bottom of the part of this floating diffusion region at least.

2, imageing sensor as claimed in claim 1, wherein this photodiode region comprises:

First photodiode region of second conduction type, it extends at depth direction from the position near the substrate surface of first conduction type; And

Second photodiode region of second conductivity type embeds this second photodiode region by this way, that is, it is extended in the bottom of this reset transistor and this source follower transistor from this first photodiode region,

Wherein, do not form this second photodiode region in the regional bottom of the part of this floating diffusion region at least.

3, imageing sensor as claimed in claim 1 wherein, in described pixel, does not form this photodiode region in the regional bottom of the part of this transfer gate transistor at least.

4, imageing sensor as claimed in claim 1, wherein,

The first and second adjacent pixels are shared this reset transistor, floating diffusion region and source follower transistor at least, and do not form the photodiode region of described first and second pixels at least in the regional bottom of the part of the floating diffusion region of sharing.

5, imageing sensor as claimed in claim 1 wherein, forms the optical screen film that stops incident light on this floating diffusion region.

6, imageing sensor as claimed in claim 1, wherein, this reset transistor comprises:

Drain region that is connected with reset voltage line and the source area that is connected with this floating diffusion region; And

This photodiode region is not formed at the bottom at the source area of this reset transistor; And

On this source area, form the optical screen film that stops incident light.

7, imageing sensor as claimed in claim 4, wherein, this photodiode region comprises:

Second photodiode region of second conduction type embeds this second photodiode region by this way, that is, it is extended in the bottom of this reset transistor and this source follower transistor from this first photodiode region,

8, imageing sensor as claimed in claim 7 wherein, does not form this second photodiode region in the bottom of the source follower transistor of described first and second pixels.

9, imageing sensor as claimed in claim 7 also comprises:

Select transistor, it is connected with this source follower transistor, and is shared by described first and second pixels,

Wherein, in each first and second pixel region, any or two that this transfer gate transistor, floating diffusion region are set and from this reset transistor, source follower transistor and selection transistor, select along a side vertical with the boundary line of described first and second pixel regions; And

Second photodiode region in described first and second pixels is of similar shape with respect to the boundary line of planting between them.

10, imageing sensor as claimed in claim 7 wherein, forms the floating diffusion region of sharing, and form described transfer gate transistor in first and second pixel region adjacent with this floating diffusion region of sharing on the boundary line of first and second pixel regions; And

Second photodiode region in described first and second pixels has the shape of line symmetry with respect to the boundary line of planting between them.

11, imageing sensor as claimed in claim 10 also comprises:

Wherein, on the both sides of this boundary line and this boundary line, form described shared reset transistor, source follower transistor and selection transistor; And

Second photodiode region in described first and second pixels is embedded in this reset transistor, source follower transistor and selects any bottom in the transistor.

12, imageing sensor as claimed in claim 10 also comprises:

Wherein, via isolation trench structure in the substrate this reset transistor, source follower transistor and selection transistor are set on this boundary line; And

Form this second photodiode region in the zone in described first and second pixel regions except this isolation trench structure.

13, imageing sensor as claimed in claim 11 wherein, does not form this second photodiode region in the bottom of this source follower transistor.

14, imageing sensor as claimed in claim 10 also comprises:

Wherein, on this boundary line, form this source follower transistor, and this reset transistor and selection transistor are set in the both sides of this boundary line.

15, imageing sensor as claimed in claim 10 also comprises:

Wherein, on this boundary line, form this source follower transistor, and this reset transistor is set in each pixel region of these source follower transistor both sides and selects transistor.

16, imageing sensor as claimed in claim 7 wherein, in each pixel region, forms the blind zone of first conduction type between this first photodiode region and this substrate surface.

17, imageing sensor as claimed in claim 7, wherein, each pixel region comprises the first conduction type well region, forms this reset transistor and source follower transistor in this first conduction type well region; And

This first conduction type well region is plugged between this substrate surface and this second photodiode region.

18, imageing sensor as claimed in claim 7 wherein, in each pixel region, forms the drain region of first conduction type of this transfer gate transistor between this first photodiode region and this substrate surface.

19, imageing sensor as claimed in claim 7, wherein, each pixel region comprises the first conduction type well region, forms this reset transistor and source follower transistor in this first conduction type well region;

Wherein, between this first conduction type well region and this second photodiode region, form dielectric film.

20, a kind of imageing sensor, it has a plurality of pixels, and each pixel has a photodiode, a transfer gate transistor, a reset transistor, one source pole follower transistor and a selection transistor at least,

Wherein, in described pixel, floating diffusion region constitutes the node that this transfer gate transistor is connected with this reset transistor, and is connected with the grid of this source follower transistor;

Described pixel comprises photodiode region, and it is embedded in this reset transistor, source follower transistor or selects transistorized bottom;

First to fourth adjacent pixel is shared this reset transistor, source follower transistor and selection transistor;

Described first and second pixels are shared first floating diffusion region, and described third and fourth pixel is shared second floating diffusion region, and do not form the photodiode region of each pixel at least in the regional bottom of the part of the floating diffusion region of sharing;

Boundary in described first and second pixels forms this first floating diffusion region, and forms this second floating diffusion region at the boundary of described third and fourth pixel; And

The both sides of first or second floating diffusion region in described first to fourth pixel are provided with each transfer gate transistor.

21, imageing sensor as claimed in claim 20 wherein, is not provided with shared reset transistor, source follower transistor and selection transistor in the first and the 4th pixel of adjacency mutually on the side; And

On the described first and the 4th pixel, form green filter respectively, on the described second and the 3rd pixel, form redness and blue filter.

22, imageing sensor as claimed in claim 20 wherein, is not provided with shared reset transistor, source follower transistor and selection transistor in the first and the 4th pixel of adjacency mutually on the side; And

On the described second and the 3rd pixel, form green filter respectively, on the described first and the 4th pixel, form redness and blue filter.

23, as the described imageing sensor of claim 20 to 22, wherein, the photodiode region of described first to fourth pixel has point symmetry structure with respect to the center of described first to fourth pixel respectively.

24, a kind of imageing sensor, it has a plurality of pixels, and each pixel has a photodiode, a transfer gate transistor, a reset transistor, one source pole follower transistor and a selection transistor at least,

And first to fourth wherein, adjacent pixel is shared this reset transistor, source follower transistor and selection transistor;

In described first to fourth pixel, form this floating diffusion region and the transfer gate transistor adjacent respectively with this floating diffusion region;

Any one or two in this reset transistor, source follower transistor and the selection transistor are not set in the first and the 4th pixel of adjacency mutually on the side respectively; And

The photodiode region of described first to fourth pixel is positioned on the identical direction with respect to each transfer gate in the same pixel.

25, imageing sensor as claimed in claim 5, wherein, compare with the optical screen film in the pixel region of the core of the pel array of wherein arranging a plurality of pixels, the optical screen film in the pixel region of pel array periphery is set to be offset towards core.

26, imageing sensor as claimed in claim 1 wherein, is provided with the over flow drain(OFD) transistor in a pixel.

27, a kind of imageing sensor, it has a plurality of pixels, and each pixel has a photodiode, a transfer gate transistor, a reset transistor and one source pole follower transistor at least,

Wherein, the manufacture method of this imageing sensor comprises the steps:

Form photodiode region, it is embedded at least in the substrate except the bottom in the part zone of this floating diffusion region; And

On the photodiode region that embeds, form the source electrode and the drain region of this reset transistor and source follower transistor.